CY7C1009B-15VC

CY7C109B CY7C1009B 128K x 8 Static RAM Features • High speed — tAA = 12 ns • Low active power — 495 mW (max.) • Low CMOS standby power — 11 mW (max.) (L Version) • 2.0V Data Retention • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE1, CE2, and OE options • CY7C109B is available in standard 400-mil-wide SOJ and 32-pin TSOP type I packages. The CY7C1009B is available in a 300-mil-wide SOJ package Functional Description[1] The CY7C109B/CY7C1009B is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE1), an active HIGH Chip Enable (CE2), an active LOW Output Enable (OE), and tri-state drivers. Writing to the device is accomplished by taking Chip Enable One (CE1) and Write Enable (WE) inputs LOW and Chip Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable One (CE1) and Output Enable (OE) LOW while forcing Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW). CY7C109B is available in standard 400-mil-wide SOJ and 32pin TSOP type I packages. The CY7C1009B is available in a 300-mil-wide SOJ package. The CY7C109B and CY7C1009B are functionally equivalent in all other respects Logic Block Diagram Pin Configurations[2] SOJ Top View NC A16 A14 A12 A7 A6 A5 I/O0 INPUT BUFFER A4 A3 A2 A1 A0 A1 A2 A3 A4 A5 A6 A7 A8 I/O1 ROW DECODER I/O2 SENSE AMPS 128K x 8 ARRAY I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 I/O3 I/O4 CE1 CE2 WE OE COLUMN DECODER POWER DOWN A11 A9 A8 A13 WE I/O5 CE2 A15 VCC I/O6 NC A16 A14 I/O7 A12 A7 A6 A5 A4 TSOP I Top View (not to scale) Note: 1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com. 2. NC pins are not connected on the die. A9 A 10 A 11 A 12 A 13 A14 A15 A16 Cypress Semiconductor Corporation Document #: 38-05038 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 3, 2006 [+] [+] Feedback CY7C109B CY7C1009B Selection Guide Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Maximum CMOS Standby Current (L) 7C109B-12 7C1009B-12 12 90 10 7C109B-15 7C1009B-15 15 80 10 2 7C109B-20 7C1009B-20 20 75 10 Unit ns mA mA mA Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC to Relative GND[3] .... –0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[3] ....................................–0.5V to VCC + 0.5V DC Input Voltage[3] .................................–0.5V to VCC + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA Operating Range Range Commercial Industrial Ambient Temperature 0°C to +70°C −40°C to +85°C VCC 5V ± 10% 5V ± 10% Electrical Characteristics Over the Operating Range 7C109B-12 7C1009B-12 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 Description Test Conditions Min. 2.4 0.4 2.2 –0.3 GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC –1 –5 VCC + 0.3 0.8 +1 +5 90 45 2.2 –0.3 –1 –5 Max. Output HIGH Voltage VCC = Min., IOH = –4.0 mA Output LOW Voltage VCC = Min., IOL = 8.0 mA Input HIGH Voltage Input LOW Voltage[3] Input Leakage Current Output Leakage Current VCC Operating Supply Current 7C109B-15 7C1009B-15 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +5 80 40 2.2 –0.3 –1 –5 Max. 7C109B-20 7C1009B-20 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +5 75 30 Max. Unit V V V V µA µA mA mA ISB2 Automatic CE Max. VCC, CE1 > VIH Power-Down Current or CE2 < VIL,VIN > VIH or VIN < VIL, f = fMAX —TTL Inputs Automatic CE Max. VCC, Power-Down Current CE1 > VCC – 0.3V, L —CMOS Inputs or CE2 < 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 10 10 2 10 mA mA Capacitance[4] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 9 8 Unit pF pF Notes: 3. Minimum voltage is–2.0V for pulse durations of less than 20 ns. 4. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05038 Rev. *C Page 2 of 10 [+] [+] Feedback CY7C109B CY7C1009B AC Test Loads and Waveforms 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE (a) R2 255Ω R1 480Ω R1 480Ω 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE (b) Equivalent to: R2 255Ω GND ≤ 3 ns 3.0V 90% 10% 90% 10% ≤ 3 ns ALL INPUT PULSES THÉVENIN EQUIVALENT 167Ω 1.73V OUTPUT Switching Characteristics[5] 7C109B-12 7C1009B-12 Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW to Data Valid, CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z[6, 7] CE1 LOW to Low Z, CE2 HIGH to Low Z[7] Z[6, 7] 0 12 12 10 10 0 0 10 7 0 3 6 15 12 12 0 0 12 8 0 3 7 3 6 0 15 20 15 15 0 0 12 10 0 3 8 CE1 HIGH to High Z, CE2 LOW to High 0 6 3 7 0 20 3 12 6 0 7 3 8 12 12 3 15 7 0 8 15 15 3 20 8 20 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. 7C109B-15 7C1009B-15 Min. Max. 7C109B-20 7C1009B-20 Min. Max. Unit CE1 LOW to Power-Up, CE2 HIGH to Power-Up CE1 HIGH to Power-Down, CE2 LOW to Power-Down Write Cycle Time[9] CE1 LOW to Write End, CE2 HIGH to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z [7] [6, 7] Write Cycle[8] Notes: 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05038 Rev. *C Page 3 of 10 [+] [+] Feedback CY7C109B CY7C1009B Data Retention Characteristics Over the Operating Range (Low Power version only) Parameter VDR ICCDR tCDR tR Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Conditions No input may exceed VCC + 0.5V VCC = VDR = 2.0V, CE1 > VCC – 0.3V or CE2 < 0.3V, VIN > VCC – 0.3V or VIN < 0.3V Min. 2.0 150 0 200 Max. Unit V µA ns µs Data Retention Waveform DATA RETENTION MODE VCC 4.5V tCDR CE VDR > 2V 4.5V tR Switching Waveforms Read Cycle No. 1[10, 11] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[11, 12] ADDRESS tRC CE1 CE2 tACE OE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB ICC HIGH IMPEDANCE Notes: 10. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. Document #: 38-05038 Rev. *C Page 4 of 10 [+] [+] Feedback CY7C109B CY7C1009B Switching Waveforms (continued) Write Cycle No. 1 (CE1 or CE2 Controlled)[13, 14] tWC ADDRESS tSCE CE1 tSA CE2 tSCE tAW tPWE WE tSD DATA I/O DATA VALID tHD tHA Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13, 14] tWC ADDRESS tSCE CE1 CE2 tSCE tAW tSA WE tPWE tHA OE tSD DATA I/O NOTE 15 tHZOE DATAIN VALID tHD Notes: 13. Data I/O is high impedance if OE = VIH. 14. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state. 15. During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05038 Rev. *C Page 5 of 10 [+] [+] Feedback CY7C109B CY7C1009B Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW)[14] tWC ADDRESS tSCE CE1 CE2 tSCE tAW tSA WE tSD DATA I/O NOTE 15 tHZWE DATA VALID tLZWE tHD tPWE tHA Truth Table CE1 H X L L L CE2 X L H H H OE X X L X H WE X X H L H I/O0–I/O7 High Z High Z Data Out Data In High Z Power-Down Power-Down Read Write Selected, Outputs Disabled Mode Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Document #: 38-05038 Rev. *C Page 6 of 10 [+] [+] Feedback CY7C109B CY7C1009B Ordering Information Speed (ns) 12 Ordering Code CY7C109B-12VC CY7C1009B-12VC CY7C109B-12ZC CY7C109B-12ZXC 15 CY7C109BL-15VC CY7C109B-15VC CY7C109B-15VXC CY7C1009B-15VC CY7C1009B-15VXC CY7C109B-15ZC CY7C109B-15ZXC CY7C109B-15VI CY7C1009B-15VI 20 CY7C109B-20ZC CY7C1009B-20VC CY7C109B-20VI 51-85033 51-85041 51-85056 51-85041 51-85033 51-85056 51-85041 51-85033 Package Diagram 51-85033 51-85041 51-85056 Package Type 32-pin (400-Mil) Molded SOJ 32-pin (300-Mil) Molded SOJ 32-pin TSOP Type I 32-pin TSOP Type I (Pb-Free) 32-pin (400-Mil) Molded SOJ 32-pin (400-Mil) Molded SOJ 32-pin (400-Mil) Molded SOJ (Pb-Free) 32-pin (300-Mil) Molded SOJ 32-pin (300-Mil) Molded SOJ (Pb-Free) 32-pin TSOP Type I 32-pin TSOP Type I (Pb-Free) 32-pin (400-Mil) Molded SOJ 32-pin (300-Mil) Molded SOJ 32-pin TSOP Type I 32-pin (300-Mil) Molded SOJ 32-pin (400-Mil) Molded SOJ Industrial Commercial Industrial Commercial Operating Range Commercial Please contact local sales representative regarding availability of parts Package Diagrams 32-pin (300-Mil) Molded (51-85041) 51-85041-*A Document #: 38-05038 Rev. *C Page 7 of 10 [+] [+] Feedback CY7C109B CY7C1009B Package Diagrams (continued) 32-pin (400-Mil) Molded SOJ (51-85033) 51-85033-*B Document #: 38-05038 Rev. *C Page 8 of 10 [+] [+] Feedback CY7C109B CY7C1009B Package Diagrams (continued) 32-pin TSOP Type I (8 x 20 mm) (51-85056) 51-85056-*D All product and company names mentioned in this document may be the trademarks of their respective holders Document #: 38-05038 Rev. *C Page 9 of 10 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] [+] Feedback CY7C109B CY7C1009B Document History Page Document Title: CY7C109B/CY7C1009B 128K x 8 Static RAM Document Number: 38-05038 REV. ** *A *B ECN NO. 106832 116467 397875 Issue Date 09/22/01 09/16/02 See ECN Orig. of Change SZV CEA NXR Description of Change Change from Spec number: 38-00971 to 38-05038 Added applications foot note to data sheet, page 1 Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Updated the Ordering Information Table on page 7 Removed 25 ns and 35 ns speed bin from product offering Added note# 2 on page# 1 Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Removed IOS parameter from DC Electrical Characteristics table Updated the Ordering Information Table *C 493543 See ECN NXR Document #: 38-05038 Rev. *C Page 10 of 10 [+] [+] Feedback