CY7C1009D

CY7C109D CY7C1009D 1-Mbit (128 K × 8) Static RAM Features ■ ■ Functional Description [1] The CY7C109D/CY7C1009D is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE1), an active HIGH Chip Enable (CE2), an active LOW Output Enable (OE), and tri-state drivers.The eight input and output pins (I/O0 through I/O7) are placed in a high-impedance state when: ■ ■ ■ Pin- and function-compatible with CY7C109B/CY7C1009B High speed ❐ tAA = 10 ns Low active power ❐ ICC = 80 mA at 10 ns Low CMOS standby power ❐ ISB2 = 3 mA 2.0 V Data Retention Automatic power-down when deselected TTL-compatible inputs and outputs Easy memory expansion with CE1, CE2 and OE options CY7C109D available in Pb-free 32-pin 400-Mil wide Molded SOJ and 32-pin TSOP I packages. CY7C1009D available in Pb-free 32-pin 300-Mil wide Molded SOJ package ■ ■ ■ ■ ■ ■ ■ Deselected (CE1 HIGH or CE2 LOW), Outputs are disabled (OE HIGH), When the write operation is active (CE1 LOW, CE2 HIGH, and WE LOW) Write to the device by taking Chip Enable One (CE1) and Write Enable (WE) inputs LOW and Chip Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). Read from the device by taking Chip Enable One (CE1) and Output Enable (OE) LOW while forcing Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under these conditions, the contents of the memory location specified by the address pins appears on the I/O pins. Logic Block Diagram INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 IO0 IO1 ROW DECODER 128K x 8 ARRAY SENSE AMPS IO2 IO3 IO4 IO5 IO6 CE1 CE2 WE OE COLUMN DECODER POWER DOWN IO7 Note 1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com. A9 A10 A11 A12 A13 A14 A15 A16 Cypress Semiconductor Corporation Document #: 38-05468 Rev. *G • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised April 15, 2011 [+] Feedback CY7C109D CY7C1009D Contents Pin Configuration ............................................................. 3 Selection Guide ................................................................ 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics (Over the Operating Range) ... 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Switching Characteristics (Over the Operating Range) .. 6 Data Retention Characteristics (Over the Operating Range) ............................................... 7 Data Retention Waveform ................................................ 7 Switching Waveforms ...................................................... 7 Truth Table ........................................................................ 9 Ordering Information ...................................................... 10 Ordering Code Definitions ......................................... 10 Package Diagrams .......................................................... 11 Acronyms ........................................................................ 12 Document Conventions ................................................. 12 Units of Measure ....................................................... 12 Document History Page ................................................. 13 Sales, Solutions, and Legal Information ...................... 14 Worldwide Sales and Design Support ....................... 14 Products .................................................................... 14 Document #: 38-05468 Rev. *G Page 2 of 14 [+] Feedback CY7C109D CY7C1009D Pin Configuration [2] SOJ Top View A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND TSOP I Top View (not to scale) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 Selection Guide CY7C109D-10 CY7C1009D-10 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 10 80 3 Unit ns mA mA Note 2. NC pins are not connected on the die. Document #: 38-05468 Rev. *G Page 3 of 14 [+] Feedback CY7C109D CY7C1009D Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied ............................................ –55°C to +125°C Supply Voltage on VCC to Relative GND [3] ..–0.5 V to +6.0 V DC Voltage Applied to Outputs in High-Z State [3] ................................. –0.5 V to VCC + 0.5 V DC Input Voltage [3] ............................. –0.5 V to VCC + 0.5 V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage.......................................... > 2001 V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA Operating Range Range Industrial Ambient Temperature –40°C to +85°C VCC 5 V ± 0.5 V Speed 10 ns Electrical Characteristics (Over the Operating Range) Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage [3] Test Conditions IOH = –4.0 mA IOL = 8.0 mA 7C109D-10 7C1009D-10 Min 2.4 0.4 2.2 –0.5 VCC + 0.5 0.8 +1 +1 80 72 58 37 10 Max Unit V V V V μA μA mA mA mA mA mA Input Leakage Current Output Leakage Current GND < VI < VCC GND < VI < VCC, Output Disabled 100 MHz 83 MHz 66 MHz 40 MHz –1 –1 VCC Operating Supply Current VCC = Max, IOUT = 0 mA, f = fmax = 1/tRC ISB1 Automatic CE Power-Down Current—TTL Inputs Automatic CE Power-Down Current—CMOS Inputs Max VCC, CE1 > VIH or CE2 < VIL, VIN > VIH or VIN < VIL, f = fmax Max VCC, CE1 > VCC – 0.3 V, or CE2 < 0.3 V, VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0 ISB2 3 mA Note 3. VIL (min) = –2.0 V and VIH(max) = VCC + 1 V for pulse durations of less than 5 ns. Document #: 38-05468 Rev. *G Page 4 of 14 [+] Feedback CY7C109D CY7C1009D Capacitance [4] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0 V Max 8 8 Unit pF pF Thermal Resistance [4] Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 300-Mil Wide SOJ 57.61 40.53 400-Mil Wide SOJ 56.29 38.14 TSOP I 50.72 16.21 Unit °C/W °C/W AC Test Loads and Waveforms [5] ALL INPUT PULSES Z = 50Ω OUTPUT 50 Ω * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 1.5 V Rise Time: ≤ 3 ns 3.0 V 90% 90% 10% 30 pF* GND 10% (a) (b) Fall Time: ≤ 3 ns High-Z characteristics: R1 480Ω 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 255Ω (c) Notes 4. Tested initially and after any design or process changes that may affect these parameters. 5. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c). Document #: 38-05468 Rev. *G Page 5 of 14 [+] Feedback CY7C109D CY7C1009D Switching Characteristics (Over the Operating Range) [6] Parameter Read Cycle tpower [7] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD [10] [10] Description 7C109D-10 7C1009D-10 Min Max Unit VCC(typical) to the first access Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW to Data Valid, CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z [8, 9] CE1 LOW to Low Z, CE2 HIGH to Low Z [9] CE1 HIGH to High Z, CE2 LOW to High Z [8, 9] 100 10 10 3 10 5 0 5 3 5 0 10 μs ns ns ns ns ns ns ns ns ns ns ns CE1 LOW to Power-Up, CE2 HIGH to Power-Up CE1 HIGH to Power-Down, CE2 LOW to Power-Down [11, 12] Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Write Cycle Time CE1 LOW to Write End, CE2 HIGH to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z [9] [8, 9] 10 7 7 0 0 7 6 0 3 5 ns ns ns ns ns ns ns ns ns ns Notes 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 7. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed 8. tHZOE, tHZCE and tHZWE are specified with a load capacitance of 5 pF as in part (c) of “AC Test Loads and Waveforms [5]” on page 5. Transition is measured when the outputs enter a high impedance state. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 10. This parameter is guaranteed by design and is not tested. 11. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 12. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05468 Rev. *G Page 6 of 14 [+] Feedback CY7C109D CY7C1009D Data Retention Characteristics (Over the Operating Range) Parameter VDR ICCDR tCDR [4] tR [13] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Conditions VCC = VDR = 2.0 V, CE1 > VCC – 0.3 V or CE2 < 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V Min 2.0 Max Unit V 3 0 tRC mA ns ns Data Retention Waveform DATA RETENTION MODE VCC 4.5 V tCDR VDR > 2 V 4.5 V tR CE Switching Waveforms Figure 1. Read Cycle No. 1 (Address Transition Controlled) [14, 15] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Figure 2. Read Cycle No. 2 (OE Controlled) [15, 16] ADDRESS tRC CE1 CE2 OE tDOE tLZOE HIGH IMPEDANCE DATA OUT tLZCE VCC SUPPLY CURRENT tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB ICC HIGH IMPEDANCE tACE Notes 13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 μs or stable at VCC(min) > 50 μs. 14. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 15. WE is HIGH for read cycle. 16. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. Document #: 38-05468 Rev. *G Page 7 of 14 [+] Feedback CY7C109D CY7C1009D Switching Waveforms (continued) Figure 3. Write Cycle No. 1 (CE1 or CE2 Controlled) [17, 18] tWC ADDRESS tSCE CE1 tSA CE2 tAW tPWE WE tSD DATA I/O DATA VALID tHD tSCE tHA Figure 4. Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [17, 18] tWC ADDRESS tSCE CE1 CE2 tAW tSA WE tSCE tHA tPWE OE tSD DATA I/O NOTE 19 tHZOE DATAIN VALID t HD Notes 17. Data I/O is high impedance if OE = VIH. 18. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state. 19. During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05468 Rev. *G Page 8 of 14 [+] Feedback CY7C109D CY7C1009D Switching Waveforms (continued) Figure 5. Write Cycle No. 3 (WE Controlled, OE LOW) [12, 18] tWC ADDRESS tSCE CE1 CE2 tSCE tAW tSA WE tPWE tHA tSD DATA I/O NOTE 19 tHZWE DATA VALID tHD tLZWE Truth Table CE1 H X L L L CE2 X L H H H OE X X L X H WE X X H L H I/O0–I/O7 High Z High Z Data Out Data In High Z Power-down Power-down Read Write Selected, Outputs Disabled Mode Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Document #: 38-05468 Rev. *G Page 9 of 14 [+] Feedback CY7C109D CY7C1009D Ordering Information Speed (ns) 10 Ordering Code CY7C109D-10VXI CY7C109D-10ZXI CY7C1009D-10VXI Package Diagram 51-85033 51-85056 51-85041 Package Type 32-pin (400-Mil) Molded SOJ (Pb-free) 32-pin TSOP Type I (Pb-free) 32-pin (300-Mil) Molded SOJ (Pb-free) Operating Range Industrial Ordering Code Definitions CY 7 C 1 xx9 D - 10 XX I Temperature Range: I = Industrial Package Type: XX = VX or ZX VX = 32-pin Molded SOJ (Pb-free) ZX = 32-pin TSOP Type I (Pb-free) Speed: 10 ns D = C9, 90 nm Technology xx9 = 09 or 009 = (400-Mil / 300-Mil) 1-Mbit density 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS 7 = SRAM CY = Cypress Please contact your local Cypress sales representative for availability of these parts. Document #: 38-05468 Rev. *G Page 10 of 14 [+] Feedback CY7C109D CY7C1009D Package Diagrams Figure 6. 32-pin (300-Mil) Molded SOJ, 51-85041 51-85041 *B Figure 7. 32-pin (400-Mil) Molded SOJ, 51-85033 51-85033 *D Document #: 38-05468 Rev. *G Page 11 of 14 [+] Feedback CY7C109D CY7C1009D Package Diagrams (continued) Figure 8. 32-pin Thin Small Outline Package Type I (8 × 20 mm), 51-85056 51-85056 *F Acronyms Acronym CE CMOS I/O OE SRAM SOJ TSOP VFBGA chip enable Complementary metal oxide semiconductor Input/output output enable Static random access memory Small Outline J-Lead Thin Small Outline Package Very Fine-Pitch Ball Grid Array Description Document Conventions Units of Measure Symbol ns V µA mA mV mW MHz pF °C W nano seconds Volts micro Amperes milli Amperes milli Volts milli Watts Mega Hertz pico Farad degree Celcius Watts Unit of Measure Document #: 38-05468 Rev. *G Page 12 of 14 [+] Feedback CY7C109D CY7C1009D Document History Page Document Title: CY7C109D/CY7C1009D, 1-Mbit (128 K × 8) Static RAM Document Number: 38-05468 Revision ** *A *B ECN 201560 233722 262950 Submission Date See ECN See ECN See ECN Orig. of Change SWI RKF RKF Description of Change Advance Information data sheet for C9 IPP DC parameters are modified as per EROS (Spec # 01-2165) Pb-free offering in Ordering Information Added Data Retention Characteristics table Added Tpower Spec in Switching Characteristics Table Shaded Ordering Information Reduced Speed bins to -10 and -12 ns Converted from Preliminary to Final Removed Commercial Operating range Removed 12 ns speed bin Added ICC values for the frequencies 83MHz, 66MHz and 40MHz Updated Thermal Resistance table Updated Ordering Information Table Changed Overshoot spec from VCC+2 V to VCC+1 V in footnote #3 Changed ICC spec from 60 mA to 80 mA for 100MHz, 55 mA to 72 mA for 83MHz, 45 mA to 58 mA for 66MHz, 30 mA to 37 mA for 40MHz Added Ordering Code Definitions. Updated Package Diagrams. Updated template and styles as per current Cypress standards. Added Acronyms and units of measure. Updated package diagrams: 51-85033 to *D 51-85056 to *F *C *D See ECN 560995 See ECN See ECN RKF VKN *E *F *G 802877 3104943 3220123 See ECN 12/08/2010 04/08/2011 VKN AJU PRAS Document #: 38-05468 Rev. *G Page 13 of 14 [+] Feedback CY7C109D CY7C1009D Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-05468 Rev. *G Revised April 15, 2011 Page 14 of 14 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback