CY7C1019DV33-10VXIT

CY7C1018DV33 CY7C1019DV33 1-Mbit (128 K × 8) Static RAM 1-Mbit (128 K × 8) Static RAM Features Functional Description ■ Pin- and function-compatible with CY7C1018CV33 and CY7C1019CV33 ■ High speed ❐ tAA = 10 ns ■ Low Active Power ❐ ICC = 60 mA @ 10 ns The CY7C1018DV33/CY7C1019DV33 is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). ■ Low CMOS Standby Power ❐ ISB2 = 3 mA ■ 2.0 V Data retention ■ Automatic power-down when deselected ■ CMOS for optimum speed/power ■ Center power/ground pinout ■ Easy memory expansion with CE and OE options ■ Available in Pb-free 32-pin 400-Mil wide Molded SOJ, 32-pin TSOP II and 48-ball VFBGA packages Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1018DV33/CY7C1019DV33 are available in Pb-free 32-pin 400-Mil wide Molded SOJ, 32-pin TSOP II and 48-ball VFBGA packages. For a complete list of related documentation, click here. Logic Block Diagram I/O0 INPUTBUFFER I/O1 128K × 8 ARRAY I/O2 SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 I/O3 I/O4 I/O5 CE WE COLUMN DECODER I/O6 POWER DOWN I/O7 A9 A10 A11 A12 A13 A14 A15 A16 OE Cypress Semiconductor Corporation Document Number: 38-05481 Rev. *J • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 26, 2015 CY7C1018DV33 CY7C1019DV33 Contents Selection Guide ................................................................ 3 Pin Configurations ........................................................... 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 11 Document Number: 38-05481 Rev. *J Ordering Information ...................................................... 12 Ordering Code Definitions ......................................... 12 Package Diagrams .......................................................... 13 Acronyms ........................................................................ 17 Document Conventions ................................................. 17 Units of Measure ....................................................... 17 Document History Page ................................................. 18 Sales, Solutions, and Legal Information ...................... 20 Worldwide Sales and Design Support ....................... 20 Products .................................................................... 20 PSoC® Solutions ...................................................... 20 Cypress Developer Community ................................. 20 Technical Support ..................................................... 20 Page 2 of 20 CY7C1018DV33 CY7C1019DV33 Selection Guide Description -10 (Industrial) Unit Maximum Access Time 10 ns Maximum Operating Current 60 mA Maximum Standby Current 3 mA Pin Configurations Figure 1. 48-ball VFBGA pinout (Top View) [1] 2 3 4 5 6 NC OE A2 A6 A7 NC A I/O0 NC A1 A5 CE I/O7 B I/O1 NC A0 A4 NC I/O6 C VSS NC NC A3 NC VCC D VCC NC NC NC NC VSS E I/O2 NC A14 A11 I/O4 I/O5 F I/O3 NC A15 A12 WE A8 G NC A10 A16 A13 A9 NC H 1 SOJ/TSOPI Top View A0 A1 A2 A3 CE I/O0 I/O1 VCC V SS I/O2 I/O3 WE A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Figure 2. 32-pin SOJ / TSOP II pinout (Top View) A2 A6 A7 NC A A1 A5 CE I/O7 B A0 A4 NC I/O6 C NC A3 NC VCC D NC NC NC VSS E A14 A11 I/O4 I/O5 F A15 A12 WE A8 G A16 A13 A9 NC H A0 A1 A2 A3 CE I/O0 I/O1 VCC V SS I/O2 I/O3 WE A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE I/O7 I/O6 VSS VCC I/O5 I/O4 A12 A11 A10 A9 A8 Note 1. NC pins are not connected on the die. Document Number: 38-05481 Rev. *J Page 3 of 20 CY7C1018DV33 CY7C1019DV33 DC Input Voltage [2] ............................ –0.3 V to VCC + 0.3 V Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ............................... –65 C to +150 C Ambient Temperature with Power Applied ......................................... –55 C to +125 C Supply Voltage on VCC to Relative GND [2] ...............................–0.3 V to +4.6 V Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage (per MIL-STD-883, Method 3015) .......................... > 2001 V Latch-up Current .................................................... > 200 mA Operating Range DC Voltage Applied to Outputs in High Z State [2] ................................ –0.3 V to VCC + 0.3 V Range Ambient Temperature VCC Speed Industrial –40 C to +85 C 3.3 V  0.3 V 10 ns Electrical Characteristics Over the Operating Range Parameter Description -10 (Industrial) Test Conditions VOH Output HIGH voltage Min VCC, IOH = –4.0 mA VOL Output LOW voltage Min VCC, IOL = 8.0 mA VIH Input HIGH voltage [2] Unit Min Max 2.4 – V – 0.4 V 2.0 VCC + 0.3 V VIL Input LOW voltage –0.3 0.8 V IIX Input leakage current GND < VIN < VCC –1 +1 A IOZ Output leakage current GND < VIN < VCC, output disabled –1 +1 A ICC VCC operating supply current VCC = Max, IOUT = 0 mA, f = fMAX = 1/tRC 100 MHz – 60 mA 83 MHz – 55 mA 66 MHz – 45 mA 40 MHz – 30 mA ISB1 Automatic CE power-down current – TTL inputs Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX – 10 mA ISB2 Automatic CE power-down current – CMOS inputs Max VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V, f = 0 – 3 mA Note 2. VIL(min) = –2.0 V and VIH(max) = VCC + 1 V for pulse durations of less than 5 ns. Document Number: 38-05481 Rev. *J Page 4 of 20 CY7C1018DV33 CY7C1019DV33 Capacitance Parameter [3] Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = 3.3 V Max Unit 8 pF 8 pF Thermal Resistance Parameter [3] Description JA Thermal Resistance (Junction to Ambient) JC Thermal Resistance (Junction to Case) Test Conditions 32-pin SOJ 32-pin TSOP II 48-ball VFBGA Unit Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 56.29 62.22 36 C/W 38.14 21.43 9 C/W AC Test Loads and Waveforms Figure 3. AC Test Loads and Waveforms [4] ALL INPUT PULSES 3.0 V Z = 50  90% OUTPUT 50  * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT GND 30 pF* 90% 10% 10% 1.5V Rise Time: 1 V/ns (a) (b) Fall Time: 1 V/ns High-Z characteristics: R1 317  3.3 V OUTPUT R2 351 5 pF (c) Notes 3. Tested initially and after any design or process changes that may affect these parameters. 4. AC characteristics (except High Z) are tested using the load conditions shown in Figure 3 (a). High Z characteristics are tested for all speeds using the test load shown in Figure 3 (c). Document Number: 38-05481 Rev. *J Page 5 of 20 CY7C1018DV33 CY7C1019DV33 Data Retention Characteristics Over the Operating Range Parameter Description Conditions VDR VCC for data retention ICCDR Data retention current tCDR [5] Chip deselect to data retention time tR[6] Operation recovery time VCC = VDR = 2.0 V, CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V Min Max Unit 2.0 – V – 3 mA 0 – ns tRC – ns Data Retention Waveform Figure 4. Data Retention Waveform DATA RETENTION MODE VCC 3.0 V VDR > 2 V tCDR 3.0 V tR CE Notes 5. Tested initially and after any design or process changes that may affect these parameters. 6. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s. Document Number: 38-05481 Rev. *J Page 6 of 20 CY7C1018DV33 CY7C1019DV33 Switching Characteristics Over the Operating Range Parameter [7] Description -10 (Industrial) Min Max Unit Read Cycle tpower[8] VCC(typical) to the first access 100 – s tRC Read cycle time 10 – ns tAA Address to data valid – 10 ns tOHA Data hold from address change 3 – ns tACE CE LOW to data valid – 10 ns tDOE OE LOW to data valid – 5 ns 0 – ns – 5 ns 3 – ns – 5 ns tLZOE OE LOW to low Z [9] [9, 10] tHZOE OE HIGH to high Z tLZCE CE LOW to low Z [9] [9, 10] tHZCE CE HIGH to high Z tPU[11] tPD[11] CE LOW to power-up 0 – ns CE HIGH to power-down – 10 ns Write Cycle [12, 13] tWC Write cycle time 10 – ns tSCE CE LOW to write end 8 – ns tAW Address set-up to write end 8 – ns tHA Address hold from write end 0 – ns tSA Address set-up to write start 0 – ns tPWE WE pulse width 7 – ns tSD Data set-up to write end 5 – ns tHD Data hold from write end 0 – ns WE HIGH to low Z [9] 3 – ns WE LOW to high Z [9, 10] – 5 ns tLZWE tHZWE Notes 7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V. 8. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 10. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in Figure 3 on page 5 (c). Transition is measured when the outputs enter a high impedance state. 11. This parameter is guaranteed by design and is not tested. 12. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 13. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 38-05481 Rev. *J Page 7 of 20 CY7C1018DV33 CY7C1019DV33 Switching Waveforms Figure 5. Read Cycle No. 1 (Address Transition Controlled) [14, 15] tRC RC ADDRESS tOHA DATA I/O tAA PREVIOUS DATA VALID DATA OUT VALID Figure 6. Read Cycle No. 2 (OE Controlled) [15, 16] ADDRESS tRC CE tACE OE tHZOE tDOE DATA I/O tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZCE HIGH IMPEDANCE DATA OUT VALID tPD tPU 50% ICC 50% ISB Notes 14. Device is continuously selected. OE, CE = VIL. 15. WE is HIGH for Read cycle. 16. Address valid prior to or coincident with CE transition LOW. Document Number: 38-05481 Rev. *J Page 8 of 20 CY7C1018DV33 CY7C1019DV33 Switching Waveforms (continued) Figure 7. Write Cycle No. 1 (CE Controlled) [17, 18] tWC ADDRESS tSCE CE tSA tSCE tAW tHA tPWE WE tSD DATA I/O tHD DATA IN VALID Figure 8. Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [17, 18] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE OE tSD DATA I/O tHD DATA IN VALID NOTE 19 tHZOE Notes 17. Data I/O is high impedance if OE = VIH. 18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 19. During this period the I/Os are in the output state and input signals should not be applied. Document Number: 38-05481 Rev. *J Page 9 of 20 CY7C1018DV33 CY7C1019DV33 Switching Waveforms (continued) Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW) [20, 21] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA I/O NOTE 22 tHD DATA IN VALID tHZWE tLZWE Notes 20. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 21. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 22. During this period the I/Os are in the output state and input signals should not be applied. Document Number: 38-05481 Rev. *J Page 10 of 20 CY7C1018DV33 CY7C1019DV33 Truth Table CE OE WE H X X High Z Power-Down Standby (ISB) L L H Data Out Read Active (ICC) L X L Data In Write Active (ICC) L H H High Z Selected, Outputs Disabled Active (ICC) Document Number: 38-05481 Rev. *J I/O0–I/O7 Mode Power Page 11 of 20 CY7C1018DV33 CY7C1019DV33 Ordering Information Speed (ns) 10 Ordering Code Package Diagram Package Type CY7C1018DV33-10VXI 51-85041 32-pin (300-Mil) Molded SOJ (Pb-free) CY7C1019DV33-10VXI 51-85033 32-pin (400-Mil) Molded SOJ (Pb-free) CY7C1019DV33-10ZSXI 51-85095 32-pin TSOP Type II (Pb-free) CY7C1019DV33-10BVXI 51-85150 48-ball VFBGA (Pb-free) Operating Range Industrial Please contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions CY 7 C 1 01 X D V33 - 10 XX X I Temperature Range: I = Industrial Pb-free Package Type: XX = V or ZS or BV V = 32-pin Molded SOJ ZS = 32-pin TSOP Type II BV = 48-ball VFBGA Speed: 10 ns Voltage range: V33 = 3 V to 3.6 V Process Technology: D = C9, 90 nm Data width: X = 8 or 9 8/9 = × 8-bits Density: 01 = 1-Mbit density Family Code: 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 38-05481 Rev. *J Page 12 of 20 CY7C1018DV33 CY7C1019DV33 Package Diagrams Figure 10. 32-pin SOJ (400 Mils) V32.4 (Molded SOJ V33) Package Outline, 51-85033 51-85033 *E Document Number: 38-05481 Rev. *J Page 13 of 20 CY7C1018DV33 CY7C1019DV33 Package Diagrams (continued) Figure 11. 32-pin SOJ (300 Mils) V32.3 (Catalog 32.3 Molded SOJ) Package Outline, 51-85041 51-85041 *D Document Number: 38-05481 Rev. *J Page 14 of 20 CY7C1018DV33 CY7C1019DV33 Package Diagrams (continued) Figure 12. 32-pin TSOP II (20.95 × 11.76 × 1.0 mm) ZS32 Package Outline, 51-85095 51-85095 *D Document Number: 38-05481 Rev. *J Page 15 of 20 CY7C1018DV33 CY7C1019DV33 Package Diagrams (continued) Figure 13. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150 51-85150 *H Document Number: 38-05481 Rev. *J Page 16 of 20 CY7C1018DV33 CY7C1019DV33 Acronyms Acronym Document Conventions Description Units of Measure CE Chip Enable CMOS Complementary Metal Oxide Semiconductor °C degree Celsius I/O Input/Output MHz megahertz OE Output Enable A microampere SOJ Small Outline J-lead s microsecond SRAM Static Random Access Memory mA milliampere TSOP Thin Small Outline Package mm millimeter TTL Transistor-Transistor Logic ns nanosecond VFBGA Very Fine-Pitch Ball Grid Array  ohm WE Write Enable % percent pF picofarad V volt W watt Document Number: 38-05481 Rev. *J Symbol Unit of Measure Page 17 of 20 CY7C1018DV33 CY7C1019DV33 Document History Page Document Title: CY7C1018DV33/CY7C1019DV33, 1-Mbit (128 K × 8) Static RAM Document Number: 38-05481 Rev. ECN No. Issue Date Orig. of Change ** 201560 See ECN SWI Advance Information data sheet for C9 IPP *A 233750 See ECN RKF Updated Electrical Characteristics: DC parameters modified as per EROS (Spec # 01-02165 Rev *A) Updated Ordering Information: Added Pb-free offering. *B 262950 See ECN RKF Added Data Retention Characteristics. Updated Switching Characteristics: Added Tpower parameter and its details. Updated Ordering Information: Shaded all Pb-free MPNs. *C 307598 See ECN RKF Removed 12 ns speed bin and 15 ns speed bin related information in all instances across the document. *D 520652 See ECN VKN Changed status from Preliminary to Final. Removed Commercial Temperature Range related information in all instances across the document. Removed 8 ns speed bin related information in all instances across the document. Added 48-ball VFBGA package related information in all instances across the document. Updated Electrical Characteristics: Added values of ICC parameter (for frequencies 83 MHz, 66 MHz and 40 MHz). Updated Note 2 (Replaced “VIH(max) = VCC + 2 V” with “VIH(max) = VCC + 1 V”). Updated Thermal Resistance. Updated Ordering Information. Updated Package Diagrams: Added Figure 13 (spec 51-85150). *E 3110052 12/14/2010 AJU Added Ordering Code Definitions. Updated Package Diagrams. *F 3416342 10/20/2011 TAVA Updated Functional Description (Removed the Note “For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com link.” and its reference in Functional Description). Updated Electrical Characteristics. Updated Switching Waveforms. Updated Package Diagrams. Added Acronyms and Units of Measure. Updated to new template. *G 4324792 03/28/2014 VINI Added CY7C1018DV33 related information across the document. Updated Ordering Information (Updated part numbers). Updated Package Diagrams: spec 51-85033 – Changed revision from *D to *E. spec 51-85150 – Changed revision from *G to *H. Updated to new template. *H 4531367 10/10/2014 NILE Updated Ordering Information: Replaced “51-85033” with “51-85041” in “Package Diagram” column for CY7C1018DV33-10VXI. Updated Package Diagrams: Added Figure 11 (spec 51-85041). Document Number: 38-05481 Rev. *J Description of Change Page 18 of 20 CY7C1018DV33 CY7C1019DV33 Document History Page (continued) Document Title: CY7C1018DV33/CY7C1019DV33, 1-Mbit (128 K × 8) Static RAM Document Number: 38-05481 Rev. ECN No. Issue Date Orig. of Change *I 4574311 11/19/2014 NILE Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. Updated Package Diagrams: spec 51-85041 – Changed revision from *C to *D. *J 4777177 05/26/2015 NILE Updated Package Diagrams: spec 51-85095 – Changed revision from *B to *D. Updated to new template. Document Number: 38-05481 Rev. *J Description of Change Page 19 of 20 CY7C1018DV33 CY7C1019DV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive cypress.com/go/automotive Clocks & Buffers Interface Lighting & Power Control Memory cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2004-2015. The information contained herein is subject to change without notice. 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Document Number: 38-05481 Rev. *J Revised May 26, 2015 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 20 of 20