CY7C1021DV33-10VXIT

CY7C1021DV33 1-Mbit (64 K × 16) Static RAM 1-Mbit (64 K × 16) Static RAM Features Functional Description ■ Temperature ranges ❐ Industrial: –40 °C to 85 °C ❐ Automotive-A: –40 °C to 85 °C ■ Pin-and function-compatible with CY7C1021CV33 The CY7C1021DV33 is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. ■ High speed ❐ tAA = 10 ns ■ Low active power ❐ ICC = 60 mA @ 10 ns ■ Low CMOS standby power ❐ ISB2 = 3 mA Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the end of this data sheet for a complete description of Read and Write modes. ■ 2.0 V data retention ■ Automatic power-down when deselected ■ CMOS for optimum speed/power ■ Independent control of upper and lower bits ■ Available in Pb-free 44-pin 400-Mil wide molded SOJ, 44-pin TSOP II and 48-ball VFBGA packages The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a Write operation (CE LOW, and WE LOW). The CY7C1021DV33 is available in Pb-free 44-pin 400-Mil wide Molded SOJ, 44-pin TSOP II and 48-ball VFBGA packages. For a complete list of related resources, click here. Logic Block Diagram 64K x 16 RAM Array SENSE AMPS A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS I/O0–I/O7 I/O8–I/O15 COLUMN DECODER A8 A9 A10 A11 A12 A13 A14 A15 BHE WE CE OE BLE Cypress Semiconductor Corporation Document Number: 38-05460 Rev. *H • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 24, 2014 CY7C1021DV33 Contents Selection Guide ................................................................ 3 Pin Configurations ........................................................... 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 DC Electrical Characteristics ....................................... 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 11 Document Number: 38-05460 Rev. *H Ordering Information ...................................................... 12 Ordering Code Definitions ......................................... 12 Package Diagrams .......................................................... 13 Acronyms ........................................................................ 15 Document Conventions ................................................. 15 Units of Measure ....................................................... 15 Document History Page ................................................. 16 Sales, Solutions, and Legal Information ...................... 18 Worldwide Sales and Design Support ....................... 18 Products .................................................................... 18 PSoC® Solutions ...................................................... 18 Cypress Developer Community ................................. 18 Technical Support ..................................................... 18 Page 2 of 18 CY7C1021DV33 Selection Guide -10 (Industrial / Automotive-A) Description Unit Maximum access time 10 ns Maximum operating current 60 mA Maximum CMOS standby current 3 mA Pin Configurations SOJ, TSOP II and VFBGA pinouts are as follows. [1] SOJ/TSOP II Top View A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 48-ball VFBGA Top View A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC 1 2 3 4 5 6 BLE OE A0 A1 A2 NC A I/O8 BHE A3 A4 CE I/O0 B I/O9 I/O10 A5 A6 I/O2 I/O1 C VSS I/O11 NC A7 I/O3 VCC D VCC I/O12 NC NC I/O4 VSS E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 NC A12 A13 WE I/O7 G NC A8 A9 A10 A11 NC H Note 1. NC pins are not connected on the die. Document Number: 38-05460 Rev. *H Page 3 of 18 CY7C1021DV33 Maximum Ratings Current into outputs (LOW) ........................................ 20 mA Static discharge voltage (per MIL-STD-883, method 3015) .......................... > 2001 V Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –65 C to +150 C Latch-up current .................................................... > 200 mA Ambient temperature with power applied .......................................... –55 C to +125 C Operating Range Supply voltage on VCC to Relative GND [2] ...............................–0.3 V to +4.6 V Range Ambient Temperature VCC Speed DC Voltage applied to outputs in high Z State [2] ................................ –0.3 V to VCC + 0.3 V Industrial –40 °C to +85 °C 3.3 V  0.3 V 10 ns Automotive-A –40 °C to +85 °C 10 ns DC input voltage [2] ............................. –0.3 V to VCC + 0.3 V Electrical Characteristics Over the Operating Range DC Electrical Characteristics Over the Operating Range Parameter Description -10 (Industrial / Automotive-A) Test Conditions Min VOH Output HIGH voltage VCC = Min, IOH = –4.0 mA VOL Output LOW voltage VCC = Min, IOL = 8.0 mA VIH Input HIGH voltage [2] Unit Max 2.4 – V – 0.4 V 2.0 VCC + 0.3 V 0.3 0.8 V VIL Input LOW voltage IIX Input leakage current GND < VI < VCC 1 +1 A IOZ Output leakage current GND < VI < VCC, Output Disabled 1 +1 A ICC VCC operating supply current VCC = Max, IOUT = 0 mA, f = fMAX = 1/tRC 100 MHz – 60 mA 83 MHz – 55 mA 66 MHz – 45 mA 40 MHz – 30 mA ISB1 Automatic CE Power-Down Current – TTL Inputs Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX – 10 mA ISB2 Automatic CE Power-Down Current – CMOS Inputs Max VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V, f = 0 – 3 mA Note 2. VIL(min) = –2.0 V and VIH(max) = VCC + 1 V for pulse durations of less than 5 ns. Document Number: 38-05460 Rev. *H Page 4 of 18 CY7C1021DV33 Capacitance Parameter [3] Description CIN Input capacitance COUT Output capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 3.3 V Max Unit 8 pF 8 pF Thermal Resistance Parameter [3] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions SOJ TSOP II VFBGA Unit Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 59.52 53.91 36 C/W 36.75 21.24 9 C/W AC Test Loads and Waveforms Figure 1. AC Test Loads and Waveforms [4] 90% OUTPUT 50  * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT ALL INPUT PULSES 3.0 V Z = 50 30 pF* GND 90% 10% 10% 1.5 V Rise Time: 1 V/ns (a) (b) Fall Time: 1 V/ns High-Z characteristics: R 317 3.3 V OUTPUT R2 351 5 pF (c) Notes 3. Tested initially and after any design or process changes that may affect these parameters. 4. AC characteristics (except High Z) are tested using the load conditions shown in Figure 1 (a). High Z characteristics are tested for all speeds using the test load shown in Figure 1 (c). Document Number: 38-05460 Rev. *H Page 5 of 18 CY7C1021DV33 Data Retention Characteristics Over the Operating Range Parameter Description Conditions VDR VCC for data retention ICCDR Data retention current tCDR[5] Chip deselect to data retention time tR[6] Operation recovery time VCC = VDR = 2.0 V, CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V Industrial Min Max Unit 2 – V – 3 mA 0 – ns tRC – ns Data Retention Waveform Figure 2. Data Retention Waveform DATA RETENTION MODE VCC 3.0 V VDR > 2 V tCDR 3.0 V tR CE Notes 5. Tested initially and after any design or process changes that may affect these parameters. 6. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s. Document Number: 38-05460 Rev. *H Page 6 of 18 CY7C1021DV33 Switching Characteristics Over the Operating Range Parameter [7] Description -10 (Industrial / Automotive-A) Min Max Unit Read Cycle tpower[8] VCC(typical) to the first access 100 – s tRC Read cycle time 10 – ns tAA Address to data valid – 10 ns tOHA Data hold from address change 3 – ns tACE CE LOW to data valid – 10 ns tDOE OE LOW to data valid – 5 ns 0 – ns – 5 ns tLZOE tHZOE OE LOW to low Z [9] OE HIGH to high Z [9, 10] [9] tLZCE CE LOW to low Z 3 – ns tHZCE CE HIGH to high Z [9, 10] – 5 ns tPU[11] tPD[11] CE LOW to power-up 0 – ns CE HIGH to power-down – 10 ns tDBE Byte Enable to data valid – 5 ns tLZBE Byte Enable to low Z 0 – ns Byte Disable to high Z – 6 ns tHZBE Write Cycle [12, 13] tWC Write cycle time 10 – ns tSCE CE LOW to write end 8 – ns tAW Address set-up to write end 8 – ns tHA Address hold from write end 0 – ns tSA Address set-up to write start 0 – ns tPWE WE pulse width 7 – ns tSD Data set-up to write end 5 – ns tHD Data hold from write end 0 – ns [9] tLZWE WE HIGH to low Z 3 – ns tHZWE WE LOW to high Z [9, 10] – 5 ns tBW Byte enable to end of write 7 – ns Notes 7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V. 8. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 10. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (c) of Figure 1 on page 5. Transition is measured when the outputs enter a high impedance state. 11. This parameter is guaranteed by design and is not tested. 12. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 13. The minimum write pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be equal to the sum of tSD and tHZWE. Document Number: 38-05460 Rev. *H Page 7 of 18 CY7C1021DV33 Switching Waveforms Figure 3. Read Cycle No. 1 (Address Transition Controlled) [14, 15] tRC RC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Figure 4. Read Cycle No. 2 (OE Controlled) [15, 16] ADDRESS tRC CE tACE OE tHZOE tDOE tLZOE BHE, BLE tHZCE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZBE HIGH IMPEDANCE DATA VALID tPD tPU 50% ICC 50% ISB Notes 14. Device is continuously selected. OE, CE, BHE and/or BLE = VIL. 15. WE is HIGH for Read cycle. 16. Address valid prior to or coincident with CE transition LOW. Document Number: 38-05460 Rev. *H Page 8 of 18 CY7C1021DV33 Switching Waveforms (continued) Figure 5. Write Cycle No. 1 (CE Controlled) [17, 18] tWC ADDRESS tSA tSCE CE tAW tHA tPWE WE tBW BHE, BLE tSD tHD DATA IN VALID DATA I/O Figure 6. Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS tSA tBW BHE, BLE tAW tHA tPWE WE tSCE CE tSD DATA I/O tHD DATA IN VALID Notes 17. Data I/O is high impedance if OE or BHE and/or BLE = VIH. 18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document Number: 38-05460 Rev. *H Page 9 of 18 CY7C1021DV33 Switching Waveforms (continued) Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW) [19] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE DATA I/O tSD tHD DATA IN VALID tLZWE Note 19. The minimum write pulse width should be equal to the sum of tSD and tHZWE. Document Number: 38-05460 Rev. *H Page 10 of 18 CY7C1021DV33 Truth Table CE OE WE H X X X X High-Z High-Z Power-down Standby (ISB) L L H L L Data Out Data Out Read – All bits Active (ICC) L H Data Out High-Z Read – Lower bits only Active (ICC) H L High-Z Data Out Read – Upper bits only Active (ICC) L L Data In Data In Write – All bits Active (ICC) L H Data In High-Z Write – Lower bits only Active (ICC) H L High-Z Data In Write – Upper bits only Active (ICC) L X L BLE BHE I/O0–I/O7 I/O8–I/O15 Mode Power L H H X X High-Z High-Z Selected, outputs disabled Active (ICC) L X X H H High-Z High-Z Selected, outputs disabled Active (ICC) Document Number: 38-05460 Rev. *H Page 11 of 18 CY7C1021DV33 Ordering Information Speed (ns) 10 10 Ordering Code Package Diagram Package Type CY7C1021DV33-10VXI 51-85082 44-pin (400-Mil) Molded SOJ (Pb-free) CY7C1021DV33-10ZSXI 51-85087 44-pin TSOP Type II (Pb-free) CY7C1021DV33-10BVXI 51-85150 48-ball VFBGA (Pb-free) CY7C1021DV33-10ZSXA 51-85087 44-pin TSOP Type II (Pb-free) Operating Range Industrial Automotive-A Please contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions CY 7 C 1 02 1 D V33 - XX XX X X Temperature Range: X = I or A or E I = Industrial; A = Automotive-A; E = Automotive-E Pb-free Package Type: XX = V or ZS or BV V = 44-pin Molded SOJ ZS = 44-pin TSOP Type II BV = 48-ball VFBGA Speed: XX = 10 ns or 12 ns V33 = Voltage range (3 V to 3.6 V) D = C9, 90 nm Technology 1 = Data width × 16-bits 02 = 1-Mbit density Family Code: 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 38-05460 Rev. *H Page 12 of 18 CY7C1021DV33 Package Diagrams Figure 8. 44-pin SOJ (400 Mils) V44.4 Package Outline, 51-85082 51-85082 *E Figure 9. 44-pin TSOP Z44-II Package Outline, 51-85087 51-85087 *E Document Number: 38-05460 Rev. *H Page 13 of 18 CY7C1021DV33 Package Diagrams (continued) Figure 10. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150 51-85150 *H Document Number: 38-05460 Rev. *H Page 14 of 18 CY7C1021DV33 Acronyms Acronym Document Conventions Description Units of Measure BHE Byte High Enable BLE Byte Low Enable °C degree Celsius CMOS Complementary Metal Oxide Semiconductor MHz megahertz CE Chip Enable µA microampere I/O Input/Output µs microsecond OE Output Enable mA milliampere SOJ Small-Outline J-leaded ns nanosecond SRAM Static Random Access Memory % percent TSOP Thin Small-Outline Package TTL Transistor-Transistor Logic VFBGA Very Fine-Pitch Ball Grid Array WE Write Enable Document Number: 38-05460 Rev. *H Symbol Unit of Measure pF picofarad V volt W watt Page 15 of 18 CY7C1021DV33 Document History Page Document Title: CY7C1021DV33, 1-Mbit (64 K × 16) Static RAM Document Number: 38-05460 Rev. ECN No. Issue Date Orig. of Change ** 201560 See ECN SWI Advance Information data sheet for C9 IPP. *A 233693 See ECN RKF Updated Electrical Characteristics (modified as per Eros (Spec # 01-02165)). Updated Ordering Information (included Pb-free offering). *B 263769 See ECN RKF Updated Functional Description (Changed I/O1–I/O16 to I/O0–I/O15). Updated Pin Configurations (Changed I/O1–I/O16 to I/O0–I/O15). Added Data Retention Characteristics and Data Retention Waveform. Updated Switching Characteristics (Added Tpower parameter and its details). Updated Ordering Information (Added shade, no change in part numbers). *C 307601 See ECN RKF Updated Selection Guide (Reduced Speed bins to -8 and -10 ns (Removed -12 and -15 speed bins related information)). Updated Electrical Characteristics (Reduced Speed bins to -8 and -10 ns (Removed -12 and -15 speed bins related information)). Updated Switching Characteristics (Reduced Speed bins to -8 and -10 ns (Removed -12 and -15 speed bins related information)). Updated Ordering Information (Updated part numbers). *D 520652 See ECN VKN Changed status from Preliminary to Final. Updated Features (Removed Commercial Operating range related information and included Automotive-A, Automotive-E Operating range related information). Updated Selection Guide (Removed -8 speed bin related information and incldued -12 speed bin related information). Updated Operating Range (Removed Commercial Operating range related information and included Automotive-A, Automotive-E Operating range related information). Updated Electrical Characteristics (Updated DC Electrical Characteristics (Removed -8 speed bin related information and included -12 speed bin related information, removed Commercial Operating range related information and included Automotive-A, Automotive-E Operating range related information), Updated Note 2 (Changed VIH(max) from VCC + 2 V to VCC + 1 V), added ICC parameter values for the frequencies 83 MHz, 66 MHz and 40 MHz). Updated Thermal Resistance (Replaced TBD with values for all packages). Updated Switching Characteristics (Removed -8 speed bin related information and included -12 speed bin related information, removed Commercial Operating range related information and included Automotive-A, Automotive-E Operating range related information). Updated Data Retention Characteristics (Removed Commercial Operating range related information and included Automotive-A, Automotive-E Operating range related information). Updated Ordering Information (Updated part numbers). *E 2898399 03/24/2010 AJU Updated Package Diagrams. *F 3109897 12/14/2010 AJU Added Ordering Code Definitions. Updated Package Diagrams. Document Number: 38-05460 Rev. *H Description of Change Page 16 of 18 CY7C1021DV33 Document History Page (continued) Document Title: CY7C1021DV33, 1-Mbit (64 K × 16) Static RAM Document Number: 38-05460 Rev. ECN No. Issue Date Orig. of Change Description of Change *G 3421856 10/25/2011 TAVA Updated Features (Removed Automotive-E Operating range related information). Updated Selection Guide (Removed Automotive-E Operating range related information, removed -12 speed bin related information). Updated Operating Range (Removed Automotive-E Operating range related information, removed -12 speed bin related information). Updated Electrical Characteristics (Updated DC Electrical Characteristics (Removed Automotive-E Operating range related information, removed -12 speed bin related information)). Updated Switching Characteristics (Removed Automotive-E Operating range related information, removed -12 speed bin related information). Updated Data Retention Characteristics (Removed Automotive-E Operating range related information). Updated Switching Waveforms. Updated Ordering Information (Updated part numbers). Updated Package Diagrams. Updated to new template. *H 4578364 11/24/2014 MEMJ Updated Functional Description: Added “For a complete list of related resources, click here.” at the end. Updated Switching Characteristics: Added Note 13 and referred the same note in “Write Cycle”. Updated Switching Waveforms: Added Note 19 and referred the same note in Figure 7. Updated Ordering Information (Removed shade, no change in part numbers). Updated Package Diagrams: spec 51-85082 – Changed revision from *D to *E. spec 51-85087 – Changed revision from *D to *E. spec 51-85150 – Changed revision from *G to *H. Added Acronyms and Units of Measure. Updated to new template. Completing Sunset Review. Document Number: 38-05460 Rev. *H Page 17 of 18 CY7C1021DV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training cypress.com/go/plc Memory cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/support cypress.com/go/touch USB Controllers Wireless/RF Technical Support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2004-2014. 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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05460 Rev. *H Revised November 24, 2014 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 18 of 18