CY7C1021D
1-Mbit (64K × 16) Static RAM
1-Mbit (64K × 16) Static RAM
Features
automatic power down feature that significantly reduces power
consumption when deselected. The input and output pins (I/O0
through I/O15) are placed in a high impedance state when the
device is deselected (CE HIGH), outputs are disabled (OE
HIGH), BHE and BLE are disabled (BHE, BLE HIGH), or during
a write operation (CE LOW and WE LOW).
■
Temperature Ranges:
❐ Industrial: –40 °C to 85 °C
❐ Automotive-A: –40 °C to 85 °C
■
Pin and Function Compatible with CY7C1021B
■
High Speed
❐ tAA = 10 ns
■
Low Active Power
❐ ICC = 80 mA at 10 ns
■
Low CMOS Standby Power
❐ ISB2 = 3 mA
■
2.0 V Data Retention
■
Automatic Power Down when Deselected
■
CMOS for Optimum Speed and Power
■
Independent Control of Upper and Lower Bits
■
Available in Pb-free 44-pin 400 Mils Wide Molded SOJ and
44-pin TSOP II Packages
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7), is written into the location
specified on the address pins (A0 through A15). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A15).
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the Truth Table on page 10 for a
complete description of read and write modes.
Functional Description
The CY7C1021D is a high performance CMOS static RAM
organized as 65,536 words by 16 bits. This device has an
The CY7C1021D device is suitable for interfacing with
processors that have TTL I/P levels. It is not suitable for
processors that require CMOS I/P levels. Please see Electrical
Characteristics on page 4 for more details and suggested
alternatives.
For a complete list of related documentation, click here.
Logic Block Diagram
64K x 16
RAM Array
SENSE AMPS
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
A8
A9
A10
A11
A12
A13
A14
A15
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation
Document Number: 38-05462 Rev. *O
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 2, 2016
CY7C1021D
Contents
Pin Configurations ........................................................... 3
Selection Guide ................................................................ 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 10
Document Number: 38-05462 Rev. *O
Ordering Information ...................................................... 11
Ordering Code Definitions ......................................... 11
Package Diagrams .......................................................... 12
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC®Solutions ....................................................... 17
Cypress Developer Community ................................. 17
Technical Support ..................................................... 17
Page 2 of 17
CY7C1021D
Pin Configurations
Figure 1. 44-pin SOJ / 44-pin TSOP II pinout (Top View) [1]
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
Selection Guide
Description
-10 (Industrial /
Automotive-A)
Unit
Maximum Access Time
10
ns
Maximum Operating Current
80
mA
Maximum CMOS Standby Current
3
mA
Note
1. NC pins are not connected on the die.
Document Number: 38-05462 Rev. *O
Page 3 of 17
CY7C1021D
DC Input Voltage [2] ............................ –0.5 V to VCC + 0.5 V
Maximum Ratings
Current into Outputs (LOW) ........................................ 20 mA
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage
(per MIL-STD-883, Method 3015) .......................... > 2001 V
Storage Temperature ............................... –65 C to +150 C
Latch Up Current ................................................... > 200 mA
Ambient Temperature
with Power Applied .................................. –55 C to +125 C
Operating Range
Supply Voltage
on VCC to Relative GND[2] ...........................–0.5 V to +6.0 V
Range
DC Voltage Applied to Outputs
in High Z State [2] ................................ –0.5 V to VCC + 0.5 V
Industrial
Ambient
Temperature
VCC
Speed
–40 C to +85 C
5 V 10%
10 ns
Automotive-A
Electrical Characteristics
Over the Operating Range
Parameter
Description
-10 (Industrial /
Automotive-A)
Test Conditions
Min
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
Unit
Max
IOH = –4.0 mA
2.4
–
IOH = –0.1 mA
–
3.4 [3]
IOL = 8.0 mA
–
0.4
V
2.2
VCC + 0.5 V
V
[2]
V
VIL
Input LOW Voltage
0.5
0.8
V
IIX
Input Leakage Current
GND < VI < VCC
1
+1
A
IOZ
Output Leakage Current
GND < VI < VCC, Output Disabled
1
+1
A
ICC
VCC Operating Supply Current
VCC = Max, IOUT = 0 mA,
f = fmax = 1/tRC
100 MHz
–
80
mA
83 MHz
–
72
mA
66 MHz
–
58
mA
40 MHz
–
37
mA
ISB1
Automatic CE Power Down
Current –TTL Inputs
Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fmax
–
10
mA
ISB2
Automatic CE Power Down
Current – CMOS Inputs
Max VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V, or
VIN < 0.3 V, f = 0
–
3
mA
Note
2. VIL (min) = –2.0 V and VIH(max) = VCC + 1 V for pulse durations of less than 5 ns.
3. Please note that the maximum VOH limit does not exceed minimum CMOS VIH of 3.5 V. If you are interfacing this SRAM with 5 V legacy processors that require a
minimum VIH of 3.5 V, please refer to Application Note AN6081 for technical details and options you may consider.
Document Number: 38-05462 Rev. *O
Page 4 of 17
CY7C1021D
Capacitance
Parameter [4]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25C, f = 1 MHz, VCC = 5.0 V
Max
Unit
8
pF
8
pF
Thermal Resistance
Parameter [4]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
44-pin SOJ
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
44-pin TSOP II Unit
59.52
53.91
C/W
36.75
21.24
C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms [5]
ALL INPUT PULSES
3.0 V
Z = 50
90%
OUTPUT
50
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
30 pF*
90%
10%
10%
GND
1.5 V
Rise Time: 3 ns
(a)
(b)
Fall Time: 3 ns
High-Z characteristics:
R1 480
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
R2
255
5 pF
(c)
Notes
4. Tested initially and after any design or process changes that may affect these parameters.
5. AC characteristics (except High Z) are tested using the load conditions shown in Figure 2 (a). High Z characteristics are tested for all speeds using the test load
shown in Figure 2 (c).
Document Number: 38-05462 Rev. *O
Page 5 of 17
CY7C1021D
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR [6]
Chip Deselect to Data Retention
Time
tR [7]
Operation Recovery Time
VCC = VDR = 2.0 V, CE > VCC – 0.3 V,
VIN > VCC – 0.3 V or VIN < 0.3 V
Min
Max
Unit
2.0
–
V
–
3
mA
0
–
ns
tRC
–
ns
Data Retention Waveform
Figure 3. Data Retention Waveform
DATA RETENTION MODE
VCC
4.5 V
VDR > 2 V
tCDR
4.5 V
tR
CE
Notes
6. VIL (min) = –2.0 V and VIH(max) = VCC + 1 V for pulse durations of less than 5 ns.
7. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s.
Document Number: 38-05462 Rev. *O
Page 6 of 17
CY7C1021D
Switching Characteristics
Over the Operating Range
Parameter [8]
Description
-10 (Industrial /
Automotive-A)
Min
Unit
Max
Read Cycle
tpower [9]
VCC(typical) to the first access
100
–
s
tRC
Read Cycle Time
10
–
ns
tAA
Address to Data Valid
–
10
ns
tOHA
Data Hold from Address Change
3
–
ns
tACE
CE LOW to Data Valid
–
10
ns
tDOE
OE LOW to Data Valid
–
5
ns
[10]
0
–
ns
–
5
ns
tLZOE
tHZOE
OE LOW to Low Z
OE HIGH to High Z
[10, 11]
[10]
tLZCE
CE LOW to Low Z
3
–
ns
tHZCE
CE HIGH to High Z [10, 11]
–
5
ns
tPU
CE LOW to Power-Up
0
–
ns
tPD
CE HIGH to Power-Down
–
10
ns
tDBE
Byte Enable to Data Valid
–
5
ns
tLZBE
Byte Enable to Low Z
0
–
ns
Byte Disable to High Z
–
5
ns
tHZBE
Write Cycle
[12, 13]
tWC
Write Cycle Time
10
–
ns
tSCE
CE LOW to Write End
7
–
ns
tAW
Address Setup to Write End
7
–
ns
tHA
Address Hold from Write End
0
–
ns
tSA
Address Setup to Write Start
0
–
ns
tPWE
WE Pulse Width
7
–
ns
tSD
Data Setup to Write End
6
–
ns
tHD
Data Hold from Write End
0
–
ns
[10]
tLZWE
WE HIGH to Low Z
3
–
ns
tHZWE
WE LOW to High Z [10, 11]
–
5
ns
tBW
Byte Enable to End of Write
7
–
ns
Notes
8. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH
and 30-pF load capacitance.
9. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
11. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (c) of Figure 2 on page 5. Transition is measured when the outputs enter a high impedance
state.
12. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a write, and
a LOW to HIGH transition on any of these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal
that terminates the write.
13. The minimum write cycle pulse width for the Write Cycle No. 3 (WE Controlled, OE LOW) should be equal to the sum of tSD and tHZWE.
Document Number: 38-05462 Rev. *O
Page 7 of 17
CY7C1021D
Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled) [14, 15]
tRC
RC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2 (OE Controlled) [15, 16]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
tLZOE
BHE, BLE
tHZCE
tDBE
tLZBE
DATA OUT
HIGH IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
tHZBE
DATA VALID
HIGH
IMPEDANCE
tPD
tPU
50%
50%
ICC
ISB
Notes
14. Device is continuously selected. OE, CE, BHE and/or BLE = VIL.
15. WE is HIGH for read cycle.
16. Address valid prior to or coincident with CE transition LOW.
Document Number: 38-05462 Rev. *O
Page 8 of 17
CY7C1021D
Switching Waveforms (continued)
Figure 6. Write Cycle No. 1 (CE Controlled) [17, 18]
tWC
ADDRESS
tSA
tSCE
CE
tAW
tHA
tPWE
WE
tBW
BHE, BLE
tSD
tHD
Data Valid
DATA I/O
Figure 7. Write Cycle No. 2 (BLE or BHE Controlled)
tWC
ADDRESS
BHE, BLE
tSA
tBW
tAW
tHA
tPWE
WE
tSCE
CE
tSD
DATA I/O
tHD
Data Valid
Notes
17. Data I/O is high impedance if OE or BHE and/or BLE = VIH.
18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Document Number: 38-05462 Rev. *O
Page 9 of 17
CY7C1021D
Switching Waveforms (continued)
Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW)
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE, BLE
tHZWE
tSD
tHD
Data Valid
DATA I/O
tLZWE
Truth Table
CE
OE
WE
BLE
BHE
I/O0–I/O7
I/O8–I/O15
H
X
X
X
X
High Z
High Z
L
L
H
L
L
Data Out
Data Out
L
H
Data Out
H
L
L
L
X
L
Mode
Power
Power Down
Standby (ISB)
Read – All bits
Active (ICC)
High Z
Read – Lower bits only
Active (ICC)
High Z
Data Out
Read – Upper bits only
Active (ICC)
L
Data In
Data In
Write – All bits
Active (ICC)
L
H
Data In
High Z
Write – Lower bits only
Active (ICC)
H
L
High Z
Data In
Write – Upper bits only
Active (ICC)
L
H
H
X
X
High Z
High Z
Selected, Outputs Disabled
Active (ICC)
L
X
X
H
H
High Z
High Z
Selected, Outputs Disabled
Active (ICC)
Document Number: 38-05462 Rev. *O
Page 10 of 17
CY7C1021D
Ordering Information
Speed
(ns)
10
Package
Diagram
Ordering Code
Package Type
CY7C1021D-10VXI
51-85082 44-pin (400-Mil) Molded SOJ (Pb-free)
CY7C1021D-10ZSXI
51-85087 44-pin TSOP Type II (Pb-free)
CY7C1021D-10ZSXA
Operating
Range
Industrial
Automotive-A
Shaded areas contain advance information. Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 7 C 1 02 1
D - 10 XX
X
X
Temperature Range: X = I or A
I = Industrial; A = Automotive-A
Pb-free
Package Type: XX = V or ZS
V = 44-pin Molded SOJ
ZS = 44-pin TSOP Type II
Speed: 10 ns
D = C9, 90 nm Technology
Data Width: 1 = × 16-bits
Density: 02 = 1-Mbit density
1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-05462 Rev. *O
Page 11 of 17
CY7C1021D
Package Diagrams
Figure 9. 44-pin SOJ (400 Mils) V44.4 Package Outline, 51-85082
51-85082 *E
Document Number: 38-05462 Rev. *O
Page 12 of 17
CY7C1021D
Package Diagrams (continued)
Figure 10. 44-pin TSOP Z44-II Package Outline, 51-85087
51-85087 *E
Document Number: 38-05462 Rev. *O
Page 13 of 17
CY7C1021D
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CE
Chip Enable
CMOS
Complementary Metal Oxide Semiconductor
°C
degree Celsius
I/O
Input/Output
MHz
megahertz
OE
Output Enable
µA
microampere
SOJ
Small Outline J-lead
µs
microsecond
SRAM
Static Random Access Memory
mA
milliampere
TSOP
Thin Small Outline Package
mm
millimeter
TTL
Transistor-Transistor Logic
ms
millisecond
WE
Write Enable
ns
nanosecond
ohm
%
percent
pF
picofarad
V
volt
W
watt
Document Number: 38-05462 Rev. *O
Symbol
Unit of Measure
Page 14 of 17
CY7C1021D
Document History Page
Document Title: CY7C1021D, 1-Mbit (64K × 16) Static RAM
Document Number: 38-05462
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
201560
SWI
See ECN
Advance Information data sheet for C9 IPP
*A
233695
RKF
See ECN
DC parameters modified as per EROS (Spec # 01-02165)
Pb-free Offering in the Ordering Information
*B
263769
RKF
See ECN
Added Data Retention Characteristics Table
Added Tpower Spec in Switching Characteristics Table
Shaded Ordering Information
*C
307601
RKF
See ECN
Reduced Speed bins to –10 and –12 ns
*D
520647
VKN
See ECN
Changed status from Preliminary to Final.
Removed Commercial Operating range
Added ICC values for the frequencies 83MHz, 66MHz and 40MHz
Updated Thermal Resistance table
Added Automotive Product Information
Updated Ordering Information Table
Changed Overshoot spec from VCC+2V to VCC+1V in footnote #4
*E
802877
VKN
See ECN
Changed Commercial operating range ICC spec from 60 mA to 80 mA for
100MHz, 55 mA to 72 mA for 83MHz, 45 mA to 58 mA for 66MHz, 30 mA to
37 mA for 40MHz
Changed Automotive operating range ICC spec from 100 mA to 120 mA for
83MHz, 90 mA to 100 mA for 66MHz, 60 mA to 63 mA for 40MHz
*F
2751755
VKN /
PYRS
08/14/09
For 12 ns speed, changed ICC spec from 120 mA to 90 mA
For 12 ns speed, changed ISB1 spec from 50 mA to 10 mA and ISB2 spec from
15 mA to 10 mA
*G
2898399
AJU
03/24/2010
Description of Change
Updated Package Diagrams.
*H
3109897
AJU
12/14/2010
Added Ordering Code Definitions.
*I
3245199
PRAS
04/30/2011
Dislodged Automotive information to new datasheet (001-68372).
Removed the Note “Automotive Product Information is Preliminary.” in page 3.
Added Acronyms and Units of Measure.
Updated to new template.
*J
3086499
AJU
06/07/2011
Updated Functional Description (Removed “For best practice
recommendations, refer to the Cypress application note AN1064, SRAM
System Guidelines.”).
*K
3540685
TAVA / AJU
03/06/2012
Updated Features (Included Automotive-A Range information).
Updated Selection Guide (Included Automotive-A Range information).
Updated Operating Range (Included Automotive-A Range information).
Updated Electrical Characteristics (Included Automotive-A Range
information).
Updated Switching Characteristics (Included Automotive-A Range
information).
Updated Ordering Information (included the part number
CY7C1021D-10ZSXA).
Updated Package Diagrams.
*L
3998493
MEMJ
05/13/2013
Replaced all instances of IO with I/O across the document.
Updated Switching Characteristics:
Updated Note 12.
Updated Switching Waveforms:
Updated Figure 6, Figure 7, Figure 8.
Updated Package Diagrams:
spec 51-85082 – Changed revision from *D to *E.
spec 51-85087 – Changed revision from *D to *E.
Completing Sunset Review.
Document Number: 38-05462 Rev. *O
Page 15 of 17
CY7C1021D
Document History Page (continued)
Document Title: CY7C1021D, 1-Mbit (64K × 16) Static RAM
Document Number: 38-05462
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
*M
4033925
MEMJ
06/19/2013
Updated Functional Description.
Updated Electrical Characteristics:
Added one more Test Condition “IOH = –0.1mA” for VOH parameter and added
maximum value corresponding to that Test Condition.
Added Note 3 and referred the same note in maximum value for VOH parameter
corresponding to Test Condition “IOH = –0.1mA”.
*N
4573121
MEMJ
11/18/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*O
5293980
VINI
06/02/2016
Updated Switching Characteristics:
Added Note 13 and referred the same note in “Write Cycle”.
Updated to new template.
Completing Sunset Review.
Document Number: 38-05462 Rev. *O
Page 16 of 17
CY7C1021D
Sales, Solutions, and Legal Information
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closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2004-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 38-05462 Rev. *O
Revised June 2, 2016
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