CY7C1020CV26-15ZSXEKJ

CY7C1020CV26 512-Kbit (32 K × 16) Static RAM 512-Kbit (32 K × 16) Static RAM Features Writing to the device is accomplished by taking chip enable (CE) and write enable (WE) inputs LOW. If byte low enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A14). If byte high enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A14). ■ Temperature range ❐ Automotive: –40 °C to 125 °C ■ High speed ❐ tAA = 15 ns ■ Optimized voltage range: 2.5 V to 2.7 V ■ Automatic power down when deselected ■ Independent control of upper and lower bits ■ CMOS for optimum speed and power ■ Package offered: 44-pin TSOP II Reading from the device is accomplished by taking chip enable (CE) and Output Enable (OE) LOW while forcing the write enable (WE) HIGH. If byte low enable (BLE) is LOW, then data from the memory location specified by the address pins appears on I/O1 to I/O8. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O9 to I/O16. See the Truth Table on page 11 for a complete description of read and write modes. Functional Description The CY7C1020CV26 is a high performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power down feature that significantly reduces power consumption when deselected. The input/output pins (I/O1 through I/O16) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1020CV26 is available in a standard 44-pin TSOP Type II. For a complete list of related documentation, click here. Logic Block Diagram Cypress Semiconductor Corporation Document Number: 38-05406 Rev. *G • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 14, 2015 CY7C1020CV26 Contents Pin Configuration ............................................................. 3 Selection Guide ................................................................ 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 AC Test Loads and Waveforms ....................................... 5 AC Switching Characteristics ......................................... 6 Switching Waveforms ...................................................... 7 Truth Table ...................................................................... 11 Ordering Information ...................................................... 12 Ordering Code Definitions ......................................... 12 Document Number: 38-05406 Rev. *G Package Diagrams .......................................................... 13 Acronyms ........................................................................ 14 Document Conventions ................................................. 14 Units of Measure ....................................................... 14 Document History Page ................................................. 15 Sales, Solutions, and Legal Information ...................... 16 Worldwide Sales and Design Support ....................... 16 Products .................................................................... 16 PSoC® Solutions ...................................................... 16 Cypress Developer Community ................................. 16 Technical Support ..................................................... 16 Page 2 of 16 CY7C1020CV26 Pin Configuration Figure 1. 44-pin TSOP II pinout (Top View) Selection Guide Description CY7C1020CV26-15 Unit Maximum access time 15 ns Maximum operating current 100 mA 5 mA Maximum CMOS standby current Document Number: 38-05406 Rev. *G Page 3 of 16 CY7C1020CV26 DC input voltage[1] ................................ –0.5 V to VCC+0.5 V Maximum Ratings Current into outputs (LOW) ........................................ 20 mA Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature ................................ –65 C to +150 C Static discharge voltage (per MIL-STD-883, Method 3015) .......................... > 2001 V Latch up current ..................................................... > 200 mA Ambient temperature with power applied ................................... –55 C to +125 C Operating Range Supply voltage on VCC to relative GND[1] ............................–0.5 V to +4.6 V Range DC voltage applied to outputs in High-Z State[1] ................................... –0.5 V to VCC+0.5 V Ambient Temperature VCC –40 C to +125 C 2.5 V to 2.7 V Automotive Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VOH Output HIGH voltage VCC = Minimum, IOH = –1.0 mA VOL Output LOW voltage VCC = Minimum, IOL = 1.0 mA VIH Input HIGH voltage voltage[1] CY7C1020CV26 Min Max Unit 2.3 – V – 0.4 V 2.0 VCC + 0.3 V –0.3 0.8 V VIL Input LOW IIX Input load current GND < VI < VCC –5 +5 A IOZ Output leakage current GND < VI < VCC, Output Disabled –5 +5 A IOS[2] Output short circuit current VCC = Maximum, VOUT = GND – –300 mA ICC VCC operating supply current VCC = Maximum, IOUT = 0 mA, f = fMAX = 1/tRC – 100 mA ISB1 Automatic CE power-down Current – TTL Inputs Maximum VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX – 40 mA ISB2 Automatic CE power-down Current – CMOS Inputs Maximum VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0 – 5 mA Notes 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. Document Number: 38-05406 Rev. *G Page 4 of 16 CY7C1020CV26 Capacitance Parameter [3] Description CIN Input capacitance COUT Output capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 2.6 V Max Unit 8 pF 8 pF AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms [4] ALL INPUT PULSES R 1830  2.5V 2.6V 90% OUTPUT R2 1976  30 pF (a) GND 90% 10% 10% Fall Time:1 V/ns Rise Time: 1 V/ns (b) Notes 3. Tested initially and after any design or process changes that may affect these parameters. 4. Test conditions assume signal transition time of 1V/ns or less, timing reference levels of 1.3 V, input pulse levels of 0 to 2.5 V and transmission line loads as in (a) of Figure 2. Document Number: 38-05406 Rev. *G Page 5 of 16 CY7C1020CV26 AC Switching Characteristics Over the Operating Range Parameter Description CY7C1020CV26 Min Max Unit Read Cycle tRC Read cycle time 15 – ns tAA Address to data valid – 15 ns tOHA Data hold from address change 3 – ns tACE CE LOW to data valid – 15 ns tDOE OE LOW to data valid – 7 ns [5] 0 – ns Z[5, 6] – 7 ns tLZOE OE LOW to low Z tHZOE OE HIGH to high Z[5] tLZCE CE LOW to low 3 – ns tHZCE CE HIGH to high Z[5, 6] – 7 ns tPU[7] tPD[7] CE LOW to power-up 0 – ns CE HIGH to power-down – 15 ns tDBE Byte enable to data valid – 7 ns tLZBE Byte enable to low Z 0 – ns Byte disable to high Z – 7 ns tWC Write cycle time 15 – ns tSCE CE LOW to write end 10 – ns tAW Address setup to write end 10 – ns tHA Address hold from write end 0 – ns tSA Address setup to write start 0 – ns tPWE WE pulse width 10 – ns tSD Data setup to write end 8 – ns tHD Data hold from write end 0 – ns tHZBE Write Cycle[8, 9] [5] tLZWE WE HIGH to Low Z 3 – ns tHZWE WE LOW to High Z[5, 6] – 4 ns tBW Byte enable to end of write 10 – ns Notes 5. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 6. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (b) of Figure 2 on page 5. Transition is measured ±500 mV from steady-state voltage. 7. This parameter is guaranteed by design and is not tested. 8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write, and the transition of these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write. 9. The minimum write pulse width for WRITE Cycle No.3 (WE Controlled, OE LOW) should be sum of tHZWE and tSD. Document Number: 38-05406 Rev. *G Page 6 of 16 CY7C1020CV26 Switching Waveforms Figure 3. Read Cycle No. 1 [10, 11] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Figure 4. Read Cycle No. 2 (OE Controlled) [11, 12] ADDRESS tRC CE tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZBE HIGH IMPEDANCE DATA VALID tPD tPU 50% IICC CC 50% IISB SB Notes 10. Device is continuously selected. OE, CE, BHE and/or BHE = VIL, 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE transition LOW. Document Number: 38-05406 Rev. *G Page 7 of 16 CY7C1020CV26 Switching Waveforms (continued) Figure 5. Write Cycle No. 1 (CE Controlled) [13, 14] tWC ADDRESS CE tSA tSCE tAW tHA tPWE WE tBW BHE, BLE tSD tHD DATA I/O Figure 6. Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tHA tPWE WE tSCE CE tSD tHD DATA I/O Notes 13. Data I/O is high impedance if OE or BHE and BLE = VIH. 14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document Number: 38-05406 Rev. *G Page 8 of 16 CY7C1020CV26 Switching Waveforms (continued) Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW) [15] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD DATA I/O tLZWE Note 15. The minimum write pulse width for WRITE Cycle No.3 (WE Controlled, OE LOW) should be sum of tHZWE and tSD. Document Number: 38-05406 Rev. *G Page 9 of 16 CY7C1020CV26 Switching Waveforms (continued) Figure 8. Write Cycle No. 4 (WE Controlled) [16, 17, 18] tWC ADDRESS tSCE CE1 CE2 tAW tHA tSA tPWE WE tBW BHE/BLE OE tHD tSD DATA I/O NOTE 19 DATA IN VALID tHZOE Notes 16. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write. 17. Data I/O is high impedance if OE = VIH. 18. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state. 19. During this period the I/Os are in output state. Do not apply input signals. Document Number: 38-05406 Rev. *G Page 10 of 16 CY7C1020CV26 Truth Table CE OE WE BLE BHE H X X X X High Z High Z Power-Down Standby (ISB) L L H L L Data Out Data Out Read – All bits Active (ICC) L H Data Out High Z Read – Lower bits only Active (ICC) H L High Z Data Out Read – Upper bits only Active (ICC) L L Data In Data In Write – All bits Active (ICC) L H Data In High Z Write – Lower bits only Active (ICC) H L High Z Data In Write – Upper bits only Active (ICC) L X L I/O1–I/O8 I/O9–I/O16 Mode Power L H H X X High Z High Z Selected, Outputs Disabled Active (ICC) L X X H H High Z High Z Selected, Outputs Disabled Active (ICC) Document Number: 38-05406 Rev. *G Page 11 of 16 CY7C1020CV26 Ordering Information Speed (ns) 15 Ordering Code Package Name CY7C1020CV26-15ZSXE Z44 Package Type 44-pin TSOP Type II (Pb-free) Operating Range Automotive Ordering Code Definitions CY 7 C 1 02 0 C V26 - 15 ZS X E Temperature Range: E = Automotive Pb-free Package Type: ZS = 44-pin TSOP Type II Speed Grade= 15 ns Voltage Range: V26 = 2.5 V to 2.7 V Process Technology: C = 0.16 µm Technology Data Width: 0 = × 16-bits Density: 02 = 512-Kbit density Family Code: 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 38-05406 Rev. *G Page 12 of 16 CY7C1020CV26 Package Diagrams Figure 9. 44-pin TSOP Z44-II Package Outline, 51-85087 51-85087 *E Document Number: 38-05406 Rev. *G Page 13 of 16 CY7C1020CV26 Acronyms Acronym Document Conventions Description Units of Measure CE Chip Enable CMOS Complementary Metal Oxide Semiconductor °C degree Celsius I/O Input/Output MHz megahertz OE Output Enable µA microampere SRAM Static Random Access Memory mA milliampere TSOP Thin Small Outline Package mm millimeter TTL Transistor-Transistor Logic mV millivolt ns nanosecond Document Number: 38-05406 Rev. *G Symbol Unit of Measure  ohm % percent pF picofarad V volt Page 14 of 16 CY7C1020CV26 Document History Page Document Title: CY7C1020CV26, 512-Kbit (32 K × 16) Static RAM Document Number: 38-05406 Rev. ECN NO. Submission Date Orig. of Change ** 128060 07/30/03 EJH Customized data sheet to meet special requirements for CG5988AF Automotive temperature range: –40°C / +125°C *A 352999 See ECN SYT Updated Document Title (to include the mention of ‘512Kb’). Removed ‘CG5988AF’ from the Datasheet. Updated Features (for better structure). *B 2903127 04/01/2010 VIVG Updated Package Diagrams. Added Sales, Solutions, and Legal Information. Updated to new template. *C 3109992 12/14/2010 AJU Added Ordering Code Definitions. *D 3346414 08/16/2011 RAME Updated Ordering Code Definitions. *E 4499482 09/11/2014 MEMJ Updated AC Switching Characteristics: Updated Note 7. Added Note 9 and referred the same note in “Write Cycle”. Updated Switching Waveforms: Added Note 15 and referred the same note in Figure 7. Updated Package Diagrams: spec 51-85087 – Changed revision from *C to *E. Updated to new template. Completing Sunset Review. *F 4573200 11/18/2014 MEMJ Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. *G 4919066 09/14/2015 VINI Document Number: 38-05406 Rev. *G Description of Change Updated Switching Waveforms: Added Figure 8. Added Note 16, 17, 18, 19 and referred the same notes in Figure 8. Added Acronyms and Units of Measure. Updated to new template. Completing Sunset Review. Page 15 of 16 CY7C1020CV26 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05406 Rev. *G Revised September 14, 2015 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 16 of 16