CY7C1020CV26

CY7C1020CV26 512 Kb (32 K × 16) Static RAM Features ■ Temperature range ❐ Automotive: –40°C to 125°C High speed ❐ tAA = 15 ns Optimized voltage range: 2.5V to 2.7V Automatic power down when deselected Independent control of upper and lower bits CMOS for optimum speed and power Package offered: 44-pin TSOP II ■ Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A14). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A14). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on I/O1 to I/O8. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O9 to I/O16. See the Truth Table on page 7 for a complete description of read and write modes. The input/output pins (I/O1 through I/O16) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1020CV26 is available in a standard 44-pin TSOP Type II. ■ ■ ■ ■ ■ Functional Description The CY7C1020CV26 is a high performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power down feature that significantly reduces power consumption when deselected. Logic Block Diagram Cypress Semiconductor Corporation Document #: 38-05406 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised December 14, 2010 [+] Feedback CY7C1020CV26 Pin Configuration Figure 1. 44-Pin TSOP II (Top View) Selection Guide Description Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current CY7C1020CV26-15 15 100 5 Unit ns mA mA Document #: 38-05406 Rev. *C Page 2 of 11 [+] Feedback CY7C1020CV26 Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage Temperature ................................. –65C to +150C Ambient Temperature with Power Applied ............................................ –55C to +125C Supply Voltage on VCC to Relative GND[1] .....–0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[1] ...................................... –0.5V to VCC+0.5V DC Input Voltage[1] .................................. –0.5V to VCC+0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch Up Current .................................................... > 200 mA Operating Range Range Automotive Ambient Temperature –40C to +125C VCC 2.5V to 2.7V Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ IOS[2] ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Maximum, VOUT = GND VCC = Maximum, IOUT = 0 mA, f = fMAX = 1/tRC Maximum VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Maximum VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 Input Load Current Output Leakage Current Output Short Circuit Current VCC Operating Supply Current Automatic CE Power Down Current —TTL Inputs Automatic CE Power Down Current —CMOS Inputs Test Conditions VCC = Minimum, IOH = –1.0 mA VCC = Minimum, IOL = 1.0 mA 2.0 –0.3 –5 –5 CY7C1020CV26 Min 2.3 0.4 VCC + 0.3 0.8 +5 +5 –300 100 40 5 Max Unit V V V V A A mA mA mA mA Capacitance[3] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 2.6V Max 8 8 Unit pF pF Notes 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05406 Rev. *C Page 3 of 11 [+] Feedback CY7C1020CV26 Figure 2. AC Test Loads and Waveforms[4] R 1830  ALL INPUT PULSES 2.5V GND Rise Time: 1 V/ns 2.6V OUTPUT 30 pF 90% 10% 90% 10% R2 1976  (a) Fall Time:1 V/ns (b) AC Switching Characteristics Over the Operating Range Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU[7] tPD[7] tDBE tLZBE tHZBE WRITE CYCLE[8] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW Write Cycle Time CE LOW to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE HIGH to Low Z [5] Description CY7C1020CV26 Min 15 15 3 15 7 0 7 3 7 0 15 7 0 7 15 10 10 0 0 10 8 0 3 4 10 Max Unit Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low CE LOW to Low Z[5] Z[5] OE HIGH to High Z[5, 6] CE HIGH to High Z[5, 6] CE LOW to Power Up CE HIGH to Power Down Byte Enable to Data Valid Byte Enable to Low Z Byte Disable to High Z ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns WE LOW to High Z[5, 6] Byte Enable to End of Write Notes 4. Test conditions assume signal transition time of 1V/ns or less, timing reference levels of 1.3V, input pulse levels of 0 to 2.5V and transmission line loads as in (a) of AC Test Loads. 5. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 6. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 7. This parameter is guaranteed by design and is not tested. 8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write, and the transition of these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write. Document #: 38-05406 Rev. *C Page 4 of 11 [+] Feedback CY7C1020CV26 Switching Waveforms Figure 3. Read Cycle No. 1[9, 10] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Figure 4. Read Cycle No. 2 (OE Controlled)[10, 11] ADDRESS tRC CE tACE OE BHE, BLE tDOE tLZOE tDBE tLZBE DATA OUT VCC SUPPLY CURRENT HIGH IMPEDANCE tLZCE tPU 50% DATA VALID tPD 50% tHZCE tHZBE tHZOE HIGH IMPEDANCE IICC CC IISB SB Notes 9. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 10. WE is HIGH for read cycle. 11. Address valid prior to or coincident with CE transition LOW. Document #: 38-05406 Rev. *C Page 5 of 11 [+] Feedback CY7C1020CV26 Switching Waveforms Figure 5. Write Cycle No. 1 (CE Controlled)[12, 13] tWC ADDRESS CE tSA tSCE tAW tPWE WE tBW BHE, BLE tSD DATA I/O tHD tHA Figure 6. Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tPWE WE tSCE CE tSD DATA I/O tHD tHA Notes 12. Data I/O is high impedance if OE or BHE and BLE = VIH. 13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document #: 38-05406 Rev. *C Page 6 of 11 [+] Feedback CY7C1020CV26 Switching Waveforms Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW) tWC ADDRESS CE tSCE tAW tSA WE tBW BHE, BLE tHZWE DATA I/O tSD tHD tPWE tHA tLZWE Truth Table CE H L OE X L WE X H BLE X L L H L X L L L H L L H X H X X H BHE X L H L L H L X H I/O1–I/O8 High Z Data Out Data Out High Z Data In Data In High Z High Z High Z I/O9–I/O16 High Z Data Out High Z Data Out Data In High Z Data In High Z High Z Power Down Read – All bits Read – Lower bits only Read – Upper bits only Write – All bits Write – Lower bits only Write – Upper bits only Selected, Outputs Disabled Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Document #: 38-05406 Rev. *C Page 7 of 11 [+] Feedback CY7C1020CV26 Ordering Information Speed (ns) 15 Ordering Code CY7C1020CV26-15ZSXE Package Name Z44 Package Type 44-pin TSOP Type II (Pb-free) Operating Range Automotive Ordering Code Definitions CY 7 C 1 02 0 C V26 - 15 ZSX E Temperature Range: E = Automotive Package Type: ZSX = 44-pin TSOP Type II (Pb-free) Speed: XX = 15 ns V26 = Voltage range (2.5 V to 2.7 V) C = 0.16 µm Technology 0 = Data width × 16-bits 02 = 512-Kbit density 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS 7 = SRAM CY = Cypress Document #: 38-05406 Rev. *C Page 8 of 11 [+] Feedback CY7C1020CV26 Package Diagrams Figure 8. 44-Pin TSOP II 51-85087 *C Document #: 38-05406 Rev. *C Page 9 of 11 [+] Feedback CY7C1020CV26 Document History Page Document Title: CY7C1020CV26 512 Kb (32 K × 16) Static RAM Document Number: 38-05406 REV. ** *A ECN NO. 128060 352999 Submission Date 07/30/03 See ECN Orig. of Change EJH SYT Description of Change Customized data sheet to meet special requirements for CG5988AF Automotive temperature range: –40°C / +125°C Removed ‘CG5988AF’ from the Datasheet Edited the features section for better structure on Page 1 Edited the title to include the mention of ‘512Kb’ Updated template. Updated package diagram. Added Sales, Solutions, and Legal Information. Added Ordering Code Definitions. *B 2903127 04/01/2010 VIVG *C 3109992 12/14/2010 AJU Document #: 38-05406 Rev. *C Page 10 of 11 [+] Feedback CY7C1020CV26 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2003-2010. 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Document #: 38-05406 Rev. *C Revised December 14, 2010 Page 11 of 11 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback