CY7C1020CV33-15ZI

CY7C1020CV33 32K x 16 Static RAM Features • Pin- and function-compatible with CY7C1020V33 • High speed — tAA = 10, 12, 15 ns • CMOS for optimum speed/power • Low active power — 360 mW (max.) • Automatic power-down when deselected • Independent control of upper and lower bits • Available in 44-pin TSOP II (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A14). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A14). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O9 to I/O16. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1020CV33 is available in standard 44-pin TSOP Type II packages. Functional Description The CY7C1020CV33 is a high-performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable Logic Block Diagram DATA IN DRIVERS Pin Configuration TSOP II Top View NC A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A4 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A7 A6 A5 A4 A3 A2 A1 A0 32K × 16 RAM Array I/O1–I/O8 I/O9–I/O16 COLUMN DECODER BHE WE CE OE BLE A5 A6 A7 OE BHE BLE I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC ROW DECODER Selection Guide 1020CV33-10 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 10 90 5 1020CV33-12 12 85 5 1020CV33-15 15 80 5 Unit ns mA mA Cypress Semiconductor Corporation Document #: 38-05133 Rev. *B A8 A9 A10 A11 A12 A13 A14 • SENSE AMPS 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised August 13, 2002 CY7C1020CV33 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC to Relative GND[1] .... –0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[1] ....................................–0.5V to VCC + 0.5V DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA Operating Range Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 3.3V ± 10% 3.3V ± 10% Electrical Characteristics Over the Operating Range 1020CV33-10 Parameter VOH VOL VIH VIL IIX IOZ IOS[2] ICC Description Test Conditions Min. 2.4 0.4 2.0 −0.3 GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC −1 −1 VCC + 0.3 0.8 +1 +1 −300 90 2.0 –0.3 –1 –1 Max. Output HIGH Voltage VCC = Min., IOH = –4.0 mA Output LOW Voltage VCC = Min., IOL = 8.0 mA Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current Output Short Circuit Current VCC Operating Supply Current 1020CV33-12 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 –300 85 2.0 –0.3 –1 –1 Max. 1020CV33-15 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 –300 80 Max. Unit V V V V µA µA mA mA ISB1 Automatic CE Max. VCC, Power-down Current CE > VIH VIN > VIH or — TTL Inputs VIN < VIL, f = fMAX Automatic CE Max. VCC, Power-down Current CE > VCC – 0.3V, VIN > — CMOS Inputs VCC – 0.3V, or VIN < 0.3V, f = 0 15 15 15 mA ISB2 5 5 5 mA Capacitance[3] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max. 8 8 Unit pF pF Notes: 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05133 Rev. *B Page 2 of 8 CY7C1020CV33 AC Test Loads and Waveforms[4] R 317 Ω 3.3V OUTPUT 30 pF R2 351Ω High-Z characteristics: 3.3V OUTPUT 5 pF ALL INPUT PULSES 90% GND 10% 90% 10% R2 351Ω R 317 Ω (a) 3.0V (c) Rise Time: 1 V/ns (b) [4] Fall Time: 1 V/ns Switching Characteristics Over the Operating Range Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU[7] tPD[7] tDBE tLZBE tHZBE Write Cycle[8] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE HIGH to Low-Z [5] 1020CV33-10 Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z[5] [5] 1020CV33-12 Min. 12 Max. 1020CV33-15 Min. 15 Max. Unit ns 15 3 15 7 0 7 3 7 0 15 7 0 7 15 10 10 0 0 10 8 0 3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7 9 ns ns Min. 10 Max. 10 3 10 5 0 5 3 5 0 10 5 0 5 10 8 7 0 0 7 5 0 3 5 7 8 12 9 8 0 0 8 6 0 3 0 0 3 0 3 12 12 6 6 6 12 6 6 OE HIGH to High-Z[5, 6] CE LOW to Low-Z CE HIGH to High-Z[5, 6] CE LOW to Power-up CE HIGH to Power-down Byte Enable to Data Valid Byte Enable to Low-Z Byte Disable to High-Z WE LOW to High-Z[5, 6] Byte Enable to End of Write 6 Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 5. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 6. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage. 7. This parameter is guaranteed by design and is not tested. 8. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a Write, and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. Document #: 38-05133 Rev. *B Page 3 of 8 CY7C1020CV33 Switching Waveforms Read Cycle No. 1 [9, 10] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[10, 11] ADDRESS tRC CE tACE OE BHE, BLE tDOE tLZOE tDBE tLZBE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZCE tHZBE DATA VALID tPD 50% IISB SB IICC CC tHZOE HIGH IMPEDANCE DATA OUT Notes: 9. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 10. WE is HIGH for Read cycle. 11. Address valid prior to or coincident with CE transition LOW. Document #: 38-05133 Rev. *B Page 4 of 8 CY7C1020CV33 Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled) [12, 13] tWC ADDRESS CE tSA tSCE tAW tPWE WE t BW BHE, BLE tSD DATA I/O tHD tHA Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tPWE WE tSCE CE tSD DATA I/O tHD tHA Notes: 12. Data I/O is high impedance if OE or BHE and/or BLE = VIH. 13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05133 Rev. *B Page 5 of 8 CY7C1020CV33 Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled) tWC ADDRESS CE tSCE tAW tSA tPWE tHA WE tBW BHE, BLE tHZWE DATA I/O tLZWE tSD tHD Truth Table CE H L OE X L WE X H BLE X L L H L X L L L H L L H X H X X H BHE X L H L L H L X H I/O1–I/O8 High-Z Data Out Data Out High-Z Data In Data In High-Z High-Z High-Z I/O9–I/O16 High-Z Data Out High-Z Data Out Data In High-Z Data In High-Z High-Z Power-down Read—All bits Read—Lower bits only Read—Upper bits only Write—All bits Write—Lower bits only Write—Upper bits only Selected, Outputs Disabled Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 10 12 15 Ordering Code CY7C1020CV33-10ZC CY7C1020CV33-10ZI CY7C1020CV33-12ZC CY7C1020CV33-12ZI CY7C1020CV33-15ZC CY7C1020CV33-15ZI Package Name Z44 Z44 Z44 Z44 Z44 Z44 Package Type 44-lead TSOP Type II 44-lead TSOP Type II 44-lead TSOP Type II 44-lead TSOP Type II 44-lead TSOP Type II 44-lead TSOP Type II Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Document #: 38-05133 Rev. *B Page 6 of 8 CY7C1020CV33 Package Diagrams 44-Pin TSOP II Z44 51-85087-A All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05133 Rev. *B Page 7 of 8 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1020CV33 Document Title: CY7C1020CV33 32K x 16 Static RAM Document Number: 38-05133 REV. ** *A *B ECN NO. 109428 115045 117615 Issue Date 12/16/01 05/30/02 08/14/02 Orig. of Change HGK HGK DFP New Data Sheet ICC and ISB1 data modified Pin 1= NC Pin 18 = A4; remove SOJ package option; remove 8ns option. Description of Change Document #: 38-05133 Rev. *B Page 8 of 8