CY7C1041BNV33L-12ZXCT

THIS SPEC IS OBSOLETE Spec No: 001-06434 Spec Title: CY7C1041BNV33, 256 K X 16 STATIC RAM Replaced by: NONE CY7C1041BNV33 256 K × 16 Static RAM 256 K × 16 Static RAM Features Functional Description ■ High speed ❐ tAA = 12 ns The CY7C1041BNV33 is a high-performance CMOS Static RAM organized as 262,144 words by 16 bits. ■ Low active power ❐ 612 mW (max.) ■ Low CMOS standby power ❐ 1.8 mW (max.) ■ 2.0 V Data Retention (660 W at 2.0 V retention) Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). ■ Automatic power-down when deselected ■ TTL-compatible inputs and outputs ■ Easy memory expansion with CE and OE features Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1041BNV33 is available in a standard 44-pin TSOP II package with center power and ground (revolutionary) pinout. For a complete list of related documentation, click here. Logic Block Diagram 256K x 16 ARRAY 1024 x 4096 SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 ROW DECODER INPUT BUFFER I/O0 – I/O7 I/O8 – I/O15 A9 A10 A 11 A 12 A 13 A 14 A 15 A 16 A17 COLUMN DECODER BHE WE CE OE BLE Cypress Semiconductor Corporation Document Number: 001-06434 Rev. *I • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 11, 2018 CY7C1041BNV33 Contents Pin Configuration ............................................................. 3 Selection Guide ................................................................ 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 5 Data Retention Waveform ................................................ 5 Switching Characteristics ................................................ 6 Switching Waveforms ...................................................... 7 Truth Table ...................................................................... 10 Ordering Information ...................................................... 10 Ordering Code Definitions ......................................... 10 Document Number: 001-06434 Rev. *I Package Diagrams .......................................................... 11 Acronyms ........................................................................ 12 Document Conventions ................................................. 12 Units of Measure ....................................................... 12 Document History Page ................................................. 13 Sales, Solutions, and Legal Information ...................... 14 Worldwide Sales and Design Support ....................... 14 Products .................................................................... 14 PSoC® Solutions ...................................................... 14 Cypress Developer Community ................................. 14 Technical Support ..................................................... 14 Page 2 of 14 CY7C1041BNV33 Pin Configuration Figure 1. 44-pin TSOP II pinout (Top View) TSOP II Top View A0 A1 A2 A3 A4 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A5 A6 A7 A8 A9 1 44 2 3 43 42 4 41 40 39 38 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A14 A13 A12 A11 A10 Selection Guide Description -12 Maximum Access Time (ns) 12 Maximum Operating Current (mA) Commercial 190 Maximum CMOS Standby Current (mA) Commercial 0.5 Document Number: 001-06434 Rev. *I Page 3 of 14 CY7C1041BNV33 DC Input Voltage [1] ............................ –0.5 V to VCC + 0.5 V Maximum Ratings Current into Outputs (LOW) ........................................ 20 mA Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Static discharge voltage (MIL-STD-883, method 3015) ................................. > 2001 V Storage Temperature ............................... –65 °C to +150 °C Latch up current ..................................................... > 200 mA Ambient Temperature with Power Applied ......................................... –55 °C to +125 °C Operating Range Supply Voltage on VCC to Relative GND [1] ...............................–0.5 V to +4.6 V Range DC Voltage Applied to Outputs in High Z State [1] ................................ –0.5 V to VCC + 0.5 V Ambient Temperature [2] VCC 0 °C to +70 °C 3.3 V ± 0.3 V Commercial Electrical Characteristics Over the Operating Range Parameter Description -12 Test Conditions VOH Output HIGH Voltage VCC = Min, IOH = –4.0 mA VOL Output LOW Voltage VCC = Min, IOL = 8.0 mA VIH Input HIGH Voltage [1] Unit Min Max 2.4 – V – 0.4 V 2.2 VCC + 0.5 V VIL Input LOW Voltage –0.5 0.8 V IIX Input Leakage Current GND < VI < VCC –1 +1 µA IOZ Output Leakage Current GND < VOUT < VCC, Output Disabled –1 +1 µA ICC VCC Operating Supply Current VCC = Max., f = fMAX = 1/tRC – 190 mA ISB1 Automatic CE Power-Down Current – TTL Inputs Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX – 40 mA ISB2 Automatic CE Power-Down Current – CMOS Inputs Commercial Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3 V or VIN < 0.3V, f=0 – 0.5 mA Commercial Notes 1. VIL (min.) = –2.0 V for pulse durations of less than 20 ns. 2. TA is the “Instant On” case temperature. Document Number: 001-06434 Rev. *I Page 4 of 14 CY7C1041BNV33 Capacitance Parameter [3] Description CIN Input capacitance COUT I/O capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = 3.3 V Max Unit 8 pF 8 pF AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms R1 317  3.3 V ALL INPUT PULSES THÉVENIN EQUIVALENT 3.3 V 167 OUTPUT R2 351 30 pF INCLUDING JIG AND SCOPE 90% 1.73 V OUTPUT (b) GND 90% 10% 10% Fall time: 1 V/ns Rise time: 1 V/ns (a) Data Retention Characteristics Over the Operating Range Parameter VDR ICCDR tCDR Conditions [4] Description Min Max Unit VCC for Data Retention 2.0 – V Data Retention Current – 330 A 0 – ns tRC – ns VCC = VDR = 2.0 V, CE > VCC – 0.3 V, Chip Deselect to Data Retention VIN > VCC – 0.3 V or VIN < 0.3 V Time [3] tR[5] Operation Recovery Time Data Retention Waveform Figure 3. Data Retention Waveform DATA RETENTION MODE VCC 3.0 V VDR > 2 V tCDR 3.0 V tR CE Notes 3. Tested initially and after any design or process changes that may affect these parameters. 4. No input may exceed VCC + 0.5 V. 5. tr < 3 ns for the -12 and -15 speeds. Document Number: 001-06434 Rev. *I Page 5 of 14 CY7C1041BNV33 Switching Characteristics Over the Operating Range Parameter [6] Description -12 Min Max Unit READ CYCLE tRC Read Cycle Time 12 – ns tAA Address to Data Valid – 12 ns tOHA Data Hold from Address Change 3 – ns tACE CE LOW to Data Valid – 12 ns tDOE OE LOW to Data Valid – 6 ns tLZOE OE LOW to Low Z 0 – ns – 6 ns tHZOE OE HIGH to High Z [7, 8] [8] tLZCE CE LOW to Low Z 3 – ns tHZCE CE HIGH to High Z [7, 8] – 6 ns tPU CE LOW to Power-Up 0 – ns tPD CE HIGH to Power-Down – 12 ns tDBE Byte Enable to Data Valid – 6 ns tLZBE Byte Enable to Low Z 0 – ns tHZBE Byte Disable to High Z – 6 ns WRITE CYCLE [9, 10] tWC Write Cycle Time 12 – ns tSCE CE LOW to Write End 10 – ns tAW Address Set-Up to Write End 10 – ns tHA Address Hold from Write End 0 – ns tSA Address Set-Up to Write Start 0 – ns tPWE WE Pulse Width 10 – ns tSD Data Set-Up to Write End 7 – ns tHD Data Hold from Write End 0 – ns [8] tLZWE WE HIGH to Low Z 3 – ns tHZWE WE LOW to High Z [7, 8] – 6 ns tBW Byte Enable to End of Write 10 – ns Notes 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of Figure 2 on page 5. Transition is measured ±500 mV from steady-state voltage. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 001-06434 Rev. *I Page 6 of 14 CY7C1041BNV33 Switching Waveforms Figure 4. Read Cycle No. 1 [11, 12] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Figure 5. Read Cycle No. 2 (OE Controlled) [12, 13] ADDRESS tRC CE tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZBE HIGH IMPEDANCE DATA VALID tPD tPU 50% 50% ICC ISB Notes 11. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. Document Number: 001-06434 Rev. *I Page 7 of 14 CY7C1041BNV33 Switching Waveforms (continued) Figure 6. Write Cycle No. 1 (CE Controlled) [14, 15] tWC ADDRESS CE tSA tSCE tAW tHA tPWE WE tBW BHE, BLE tSD tHD DATAI/O Figure 7. Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tHA tPWE WE tSCE CE tSD tHD DATAI/O Notes 14. Data I/O is high-impedance if OE or BHE and/or BLE= VIH. 15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high–impedance state. Document Number: 001-06434 Rev. *I Page 8 of 14 CY7C1041BNV33 Switching Waveforms (continued) Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD DATA I/O tLZWE Document Number: 001-06434 Rev. *I Page 9 of 14 CY7C1041BNV33 Truth Table CE OE WE BLE BHE I/O0–I/O7 I/O8–I/O15 Mode Power H X X X X High Z High Z Power Down Standby (ISB) L L H L L Data Out Data Out Read All Bits Active (ICC) L L H L H Data Out High Z Read Lower Bits Only Active (ICC) L L H H L High Z Data Out Read Upper Bits Only Active (ICC) L X L L L Data In Data In Write All Bits Active (ICC) L X L L H Data In High Z Write Lower Bits Only Active (ICC) L X L H L High Z Data In Write Upper Bits Only Active (ICC) L H H X X High Z High Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 12 Ordering Code CY7C1041BNV33L-12ZXC Package Diagram Package Type 51-85087 44-pin TSOP II (Pb-free) Operating Range Commercial Please contact local sales representative regarding availability of these parts. Ordering Code Definitions CY 7 C 1 04 1 BN V33 L - 12 Z X C Temperature Range: C = Commercial Pb-free Package Type: Z = 44-pin TSOP II Speed: 12 ns L = Low Power Voltage Range: V33 = 3 V to 3.6 V BN = 0.25 µm Technology Data Width: 1 = × 16-bits Density: 04 = 4-Mbit density Family Code: 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-06434 Rev. *I Page 10 of 14 CY7C1041BNV33 Package Diagrams Figure 9. 44-pin TSOP II Package Outline, 51-85087 51-85087 *E Document Number: 001-06434 Rev. *I Page 11 of 14 CY7C1041BNV33 Acronyms Acronym Document Conventions Description Units of Measure CMOS Complementary Metal Oxide Semiconductor CE Chip Enable °C degree Celsius I/O Input/Output MHz megahertz OE Output Enable A microampere SRAM Static Random Access Memory F microfarad TTL Transistor-Transistor Logic s microsecond TSOP Thin Small-Outline Package W microwatt WE Write Enable mA milliampere ms millisecond mW milliwatt ns nanosecond  ohm % percent pF picofarad V volt W watt Document Number: 001-06434 Rev. *I Symbol Unit of Measure Page 12 of 14 CY7C1041BNV33 Document History Page Document Title: CY7C1041BNV33, 256 K × 16 Static RAM Document Number: 001-06434 Revision ECN Orig. of Change Submission Date ** 423877 NXR See ECN New data sheet. *A 2899016 VKN See ECN Removed Industrial grade temperature related information. Removed 15 ns speed bin related information. Updated Ordering Information. Updated Package Diagrams. Description of Change *B 3109184 AJU 12/13/2010 Added Ordering Code Definitions. *C 3210222 PRAS 03/30/2011 Updated Selection Guide. Added Acronyms and Units of Measure. Updated in new template. *D 3232637 PRAS 05/04/2011 Updated Electrical Characteristics: Fixed unit for Input Leakage current and Output Leakage current from mA to µA. *E 3403051 AJU 10/12/2011 Updated Ordering Information (Removed prune part number CY7C1041BNV33L-12VXC). Updated Package Diagrams. *F 4337921 VINI 04/09/2014 Updated Maximum Ratings: Added “Static discharge voltage” and “Latch up current” details. Updated Package Diagrams: spec 51-85082 – Changed revision from *D to *E. spec 51-85087 – Changed revision from *D to *E. Updated to new template. Completing Sunset Review. *G 4578500 VINI 11/25/2014 Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. *H 4736197 VINI 04/23/2015 Removed “44-pin SOJ package” details in all instances across the document. Updated Package Diagrams: Removed spec 51-85082 *E. Updated to new template. Completing Sunset Review. *I 6171990 VINI 05/11/2018 Obsolete datasheet Document Number: 001-06434 Rev. *I Page 13 of 14 CY7C1041BNV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2006-2018. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-06434 Rev. *I Revised May 11, 2018 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 14 of 14