CY7C1041BN_1105

CY7C1041BN 256 K × 16 Static RAM Features ■ Functional Description The CY7C1041BN is a high-performance CMOS static RAM organized as 262,144 words by 16 bits. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1041BN is available in a standard 44-pin 400-mil-wide body width SOJ and 44-pin TSOP II package with center power and ground (revolutionary) pinout. Temperature ranges ❐ Commercial: 0 °C to 70 °C ❐ Industrial: –40 °C to 85 °C ❐ Automotive-A: –40 °C to 85 °C High speed ❐ tAA = 15 ns Low active power ❐ 1540 mW (max.) Low CMOS standby power (L version) ❐ 2.75 mW (max.) 2.0 V data retention (400 μW at 2.0 V retention) Automatic power-down when deselected TTL-compatible inputs and outputs Easy memory expansion with CE and OE features Available in Pb-free and non Pb-free 44-pin TSOP II and molded 44-pin (400-Mil) SOJ packages ■ ■ ■ ■ ■ ■ ■ ■ Selection Guide Description Maximum access time Maximum operating current Commercial Industrial Automotive-A Maximum CMOS standby current Commercial Commercial L Industrial Automotive-A -15 15 190 210 – 3 0.5 6 – -20 20 170 190 190 3 0.5 6 6 Unit ns mA – – mA Cypress Semiconductor Corporation Document #: 001-06496 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 12, 2011 [+] Feedback CY7C1041BN Logic Block Diagram A0 A1 A2 A3 A4 A5 A6 A7 A8 Input Buffer Row Decoder 256 K x 16 Array Sense Amps I/O0–I/O7 I/O8–I/O15 Column Decoder A9 A10 A 11 A 12 A 13 A14 A15 A16 A17 BHE WE CE OE BLE Document #: 001-06496 Rev. *E Page 2 of 13 [+] Feedback CY7C1041BN Contents Pin Configuration ............................................................. 4 Maximum Ratings ............................................................. 5 Operating Range ............................................................... 5 Electrical Characteristics Over the Operating Range .. 5 Capacitance ...................................................................... 6 AC Test Loads and Waveforms ....................................... 6 Switching Characteristics[4] Over the Operating Range 6 Data Retention Characteristics Over the Operating Range (L version only) ................... 7 Data Retention Waveform ................................................ 7 Switching Waveforms ...................................................... 8 Read Cycle No. 1 ........................................................ 8 Read Cycle No. 2 (OE Controlled) .............................. 8 Write Cycle No. 1 (CE Controlled) ............................... 9 Write Cycle No. 2 (BLE or BHE Controlled) ................ 9 Write Cycle No. 3 (WE Controlled, OE LOW) ........... 10 Truth Table ...................................................................... 10 Ordering Information ...................................................... 11 Ordering Code Definition ........................................... 11 Package Diagrams .......................................................... 12 Acronyms ........................................................................ 12 Document Conventions ................................................. 12 Units of Measure ....................................................... 12 Sales, Solutions, and Legal Information ...................... 13 Worldwide Sales and Design Support ....................... 13 Products .................................................................... 13 PSoC Solutions ......................................................... 13 Document #: 001-06496 Rev. *E Page 3 of 13 [+] Feedback CY7C1041BN Pin Configuration SOJ TSOP II Top View A0 A1 A2 A3 A4 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A14 A13 A12 A11 A10 Document #: 001-06496 Rev. *E Page 4 of 13 [+] Feedback CY7C1041BN Maximum Ratings (Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.) Storage temperature ................................ –65 °C to +150 °C Ambient temperature with power applied ........................................... –55 °C to +125 °C Supply voltage on VCC to relative GND .....–0.5 V to +7.0 V DC voltage applied to outputs in High Z State[1] .................................. –0.5 V to VCC + 0.5 V DC input voltage[1] ............................... –0.5 V to VCC + 0.5 V Current into outputs (LOW) ......................................... 20 mA [1] Operating Range Range Commercial Industrial Automotive-A Ambient Temperature[2] 0 °C to +70 °C –40 °C to +85 °C –40 °C to +85 °C VCC 5 V ± 0.5 Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage[1] Input load current Output leakage current VCC operating supply current Test Conditions VCC = Min, IOH = –4.0 mA VCC = Min, IOL = 8.0 mA – – GND < VI < VCC GND < VOUT < VCC, Output Disabled VCC = Max, f = fMAX = 1/tRC Comm’l Ind’l Auto-A ISB1 Automatic CE Power-down current—TTL inputs Automatic CE power-down current —CMOS inputs Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX Max VCC, CE > VCC – 0.3 V, Comm’l VIN > VCC – 0.3 V, Comm’l L or VIN < 0.3 V, f = 0 Ind’l Auto-A –15 Min 2.4 – 2.2 –0.5 –1 –1 – – – – Max – 0.4 VCC + 0.5 0.8 +1 +1 190 210 – 40 Min 2.4 – 2.2 –0.5 –1 –1 – – – – –20 Max – 0.4 VCC + 0.5 0.8 +1 +1 170 190 190 40 Unit V V V V µA µA mA mA mA mA ISB2 – – – – 3 0.5 6 – – – – 3 0.5 6 6 mA mA mA mA Notes 1. VIL (min.) = –2.0 V for pulse durations of less than 20 ns. 2. TA is the case temperature. Document #: 001-06496 Rev. *E Page 5 of 13 [+] Feedback CY7C1041BN Capacitance Parameter[3] CIN COUT Description Input capacitance I/O capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = 5.0 V Max 8 8 Unit pF pF AC Test Loads and Waveforms 5V Output 30 pF Including JIG and Scope R1 481 Ω R1 481Ω 5V Output R2 255 Ω Including JIG and Scope 5 pF R2 255 Ω GND ≤ 3 ns 3.0 V 90% 10% 90% 10% ≤ 3 ns All Input Pulses (a) (b) Equivalent to: Output Thé venin Equivalent 167 Ω 1.73 V Switching Characteristics[4] Over the Operating Range Parameter Read Cycle tpower tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE VCC(typical) to the First Access[5] Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z[6, 7] [7] Description –15 Min 1 15 – 3 – – 0 – 3 – 0 – – 0 – Max – – 15 – 15 7 – 7 – 7 – 15 7 – 7 0 – – 0 – 3 3 – – 0 Min 1 20 –20 Max – – 20 – 20 8 – 8 – 8 – 20 8 – 8 Unit μs ns ns ns ns ns ns ns ns ns ns ns ns ns ns CE LOW to Low Z CE HIGH to High Z[6, 7] CE LOW to Power-Up CE HIGH to Power-Down Byte Enable to Data Valid Byte Enable to Low Z Byte Disable to High Z Notes 3. Tested initially and after any design or process changes that may affect these parameters. 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. This part has a voltage regulator which steps down the voltage from 5 V to 3.3 V internally. tpower time has to be provided initially before a read/write operation is started. 6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. Document #: 001-06496 Rev. *E Page 6 of 13 [+] Feedback CY7C1041BN Switching Characteristics[4] Over the Operating Range (continued) Parameter Write Cycle[11, 12] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z[10] WE LOW to High Z[9, 10] Byte Enable to End of Write 15 12 12 0 0 12 8 0 3 – 12 – – – – – – – – – 7 – 20 13 13 0 0 13 9 0 3 – 13 – – – – – – – – – 8 – ns ns ns ns ns ns ns ns ns ns ns Description –15 Min Max Min –20 Max Unit Data Retention Characteristics Over the Operating Range (L version only) Parameter VDR ICCDR tCDR[8] tR [13] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time – Conditions[14] VCC = VDR = 2.0 V, CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V Min 2.0 – 0 tRC Max – 200 – – Unit V μA ns ns Data Retention Waveform Data Retention Mode VCC 3.0 V tCDR CE VDR > 2 V 3.0 V tR Notes 8. Tested initially and after any design or process changes that may affect these parameters. 9. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 11. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 12. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 13. tr < 3 ns for the –15 speed. tr < 5 ns for the -20 and slower speeds. 14. No input may exceed VCC + 0.5 V. Document #: 001-06496 Rev. *E Page 7 of 13 [+] Feedback CY7C1041BN Switching Waveforms Read Cycle No. 1[15, 16] tRC Address tAA tOHA Data Out Previous Data Valid Data Valid Read Cycle No. 2 (OE Controlled)[16, 17] Address tRC CE tACE OE BHE, BLE tDOE tLZOE tDBE tLZBE High Impedance tLZCE VCC Supply Current tPU 50% tHZCE tHZBE Data Valid tPD 50% ISB ICC tHZOE High Impedance Data Out Notes 15. Device is continuously selected. OE, CE, BHE, and/or BHE = VIL. 16. WE is HIGH for read cycle. 17. Address valid prior to or coincident with CE transition LOW. Document #: 001-06496 Rev. *E Page 8 of 13 [+] Feedback CY7C1041BN Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[18, 19] tWC Address CE tSA tSCE tAW tPWE WE tBW BHE, BLE tSD Data I/O tHD tHA Write Cycle No. 2 (BLE or BHE Controlled) tWC Address BHE, BLE tSA tBW tAW tPWE WE tSCE CE tSD Data I/O tHD tHA Notes 18. Data I/O is high impedance if OE or BHE and/or BLE= VIH. 19. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 001-06496 Rev. *E Page 9 of 13 [+] Feedback CY7C1041BN Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) tWC Address CE tSCE tAW tSA tPWE tHA WE tBW BHE, BLE tHZWE Data I/O tLZWE tSD tHD Truth Table CE H L L L L L L L OE X L L L X X X H WE X H H H L L L H BLE X L L H L L H X BHE X L H L L H L X I/O0–I/O7 High Z Data out Data out High Z Data in Data in High Z High Z I/O8–I/O15 High Z Data out High Z Data out Data in High Z Data in High Z Power down Read All bits Read Lower bits only Read Upper bits only Write All bits Write Lower bits only Write Upper bits only Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Document #: 001-06496 Rev. *E Page 10 of 13 [+] Feedback CY7C1041BN Ordering Information Cypress offers other versions of this type of product in many different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at http://www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Speed (ns) 15 20 Ordering Code CY7C1041BNL-15ZXC CY7C1041BN-20ZSXA Package Name 51-85087 Package Type 44-pin TSOP Type II (Pb-free) 44-pin TSOP Type II Operating Range Commercial Automotive-A Ordering Code Definitions CY 7 C 1 04 1 BN L - XX ZX / ZSX X Temperature range: C = Commercial; A = Automotive-A ZX / ZSX = 44-pin TSOP II (Pb-free) Speed: xx = 15 ns / 20 ns Low power 180 nm technology Data width x 16-bits 4-Mbit density Fast Asynchronous SRAM family Technology code: C = CMOS SRAM Company Code: CY = Cypress Document #: 001-06496 Rev. *E Page 11 of 13 [+] Feedback CY7C1041BN Package Diagrams 44-Pin TSOP II (51-85087) 51-85087 *C 51-85087-*A Acronyms Acronym BHE BLE CE CMOS I/O OE SRAM TSOP WE Byte high enable Byte low enable Chip enable Complementary metal oxide semiconductor Input/output Output enable Static random access memory Thin small outline package Write enable Description Document Conventions Units of Measure Symbol ns V µA mA mV mW MHz pF °C W nano seconds Volts micro Amperes milli Amperes milli Volts milli Watts Mega Hertz pico Farad degree Celcius Watts Unit of Measure Document #: 001-06496 Rev. *E Page 12 of 13 [+] Feedback CY7C1041BN Document History Page Document Title: CY7C1041BN 256 K × 16 Static RAM Document Number: 001-06496 Revision ** *A *B *C *D *E ECN 424111 498575 2897061 2906679 3086674 3232637 Orig. of Change NXR NXR AJU NXR PRAS PRAS Submission Date See ECN See ECN 03/22/10 04/07/10 11/15/10 04/20/2011 New Data Sheets Added Automotive-A operating range updated Ordering Information Table Removed obsolete parts from ordering information table Updated package diagrams Removed inactive part CY7C1041BNL-20VXCT from the ordering information table. Removed inactive parts (CY7C1041BN-15ZXI, CY7C1041BN-15VXI). Added Ordering Code Definition. Fixed unit for Input Load current and Output Leakage current under Electrical Characteristics table from mA to µA. Updated template. Added Units table. Description of Change Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2006-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-06496 Rev. *E Revised May 12, 2011 Page 13 of 13 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback