CY7C1041CV33-20BAC

CY7C1041CV33 256K x 16 Static RAM Features • Pin equivalent to CY7C1041BV33 • High speed — tAA = 10 ns • Low active power — 324 mW (max.) • 2.0V data retention • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE and OE features HIGH Enable (BHE) is LOW, then data from I/O pins (I/O8–I/O15) is written into the location specified on the address pins (A0–A17). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte LOW Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 – I/O7. If Byte HIGH Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of Read and Write modes. The input/output pins (I/O0–I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a Write operation (CE LOW, and WE LOW). The CY7C1041CV33 is available in a standard 44-pin 400-mil-wide body width SOJ and 44-pin TSOP II package with center power and ground (revolutionary) pinout, as well as a 48-ball fine-pitch ball grid array (FBGA) package. Functional Description[1] The CY7C1041CV33 is a high-performance CMOS Static RAM organized as 262,144 words by 16 bits. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte LOW Enable (BLE) is LOW, then data from I/O pins (I/O0–I/O7), is written into the location specified on the address pins (A0–A17). If Byte Logic Block Diagram INPUT BUFFER Pin Configuration SOJ TSOP II Top View A0 A1 A2 A3 A4 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A0 A1 A2 A3 A4 A5 A6 A7 A8 256K × 16 ARRAY 1024 x 4096 I/O0–I/O7 I/O8–I/O15 COLUMN DECODER BHE WE CE OE BLE A17 A16 A15 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A14 A13 A12 A11 A10 ROW DECODER Selection Guide -8 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Commercial Industrial Commercial/ Industrial 8 100 110 10 -10 10 90 100 10 -12 12 85 95 10 -15 15 80 90 10 -20 20 75 85 10 Unit ns mA mA mA Shaded areas contain advance information. Note: 1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05134 Rev. *D A9 A10 A 11 A 12 A 13 A14 A15 A16 A17 SENSE AMPS • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised October 18, 2002 CY7C1041CV33 Pin Configurations 48-ball Mini FBGA 1 BLE I/O0 I/O1 VSS VCC I/O6 I/O7 NC 2 OE BHE I/O 2 I/O3 I/O4 I/O5 NC A8 (Top View) 4 3 A0 A3 A5 A17 NC A14 A12 A9 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE 6 NC I/O8 A B C D E F G H I/O10 I/O9 I/O 11 VCC I/O12 VSS I/O13 I/O14 WE A11 I/O15 NC Document #: 38-05134 Rev. *D Page 2 of 11 CY7C1041CV33 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC to Relative GND[2] .... –0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[2] .................................... –0.5V to VCC + 0.5V DC Input Voltage[2] ................................ –0.5V to VCC + 0.5V Current into Outputs (LOW) ........................................ 20 mA Operating Range Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 3.3V ± 0.3V DC Electrical Characteristics Over the Operating Range -8 Parameter VOH VOL VIH VIL[2] IIX IOZ ICC ISB1 Description Test Conditions Output HIGH Voltage VCC = Min., IOH = –4.0 mA Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-down Current — TTL Inputs Automatic CE Power-down Current — CMOS Inputs GND < VI < VCC GND < VOUT < VCC, Output Disabled VCC = Max., f = fMAX = Comm’l 1/tRC Indus. Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 Comm’l Indus. VCC = Min., IOL = 8.0 mA 2.4 0.4 -10 2.4 0.4 -12 2.4 0.4 -15 2.4 0.4 -20 2.4 0.4 V V Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit 2.0 VCC 2.0 VCC 2.0 VCC 2.0 VCC 2.0 VCC V + 0.3 + 0.3 + 0.3 + 0.3 + 0.3 –0.3 0.8 –0.3 0.8 –0.3 0.8 –0.3 0.8 –0.3 0.8 –1 –1 +1 +1 100 110 40 –1 –1 +1 +1 90 100 40 –1 –1 +1 +1 85 95 40 –1 –1 +1 +1 80 90 40 –1 –1 +1 +1 75 85 40 V µA µA mA mA mA ISB2 10 10 10 10 10 mA Shaded areas contain advance information. Capacitance[3] Parameter CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max. 8 8 Unit pF pF Notes: 2. Minimum voltage is–2.0V for pulse durations of less than 20 ns. 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05134 Rev. *D Page 3 of 11 CY7C1041CV33 AC Switching Characteristics[4] Over the Operating Range -8 Parameter Read Cycle tpower[5] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW VCC(typical) to the first access Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z OE HIGH to High-Z[6, 7] CE LOW to Low-Z[7] CE HIGH to High-Z[6, 7] 0 8 4 0 6 8 6 6 0 0 6 4 0 3 4 6 7 10 7 7 0 0 7 5 0 3 5 8 0 6 12 8 8 0 0 8 6 0 3 6 10 CE LOW to Power-Up CE HIGH to Power-Down Byte Enable to Data Valid Byte Enable to Low-Z Byte Disable to High-Z Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low-Z WE LOW to High-Z [7] [6, 7] -10 Max. -12 Min. 1 12 10 12 3 10 5 12 6 0 5 6 3 5 6 0 10 5 0 6 15 10 10 0 0 10 7 0 3 12 6 0 0 3 0 3 Max. -15 Min. 1 15 15 3 15 7 0 7 3 7 0 15 7 0 7 20 10 10 0 0 10 8 0 3 7 10 Max. -20 Min. 1 20 20 20 8 8 8 20 8 8 Max. Unit µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 8 ns ns Description Min. Max. Min. 1 8 8 3 8 4 0 4 3 4 0 3 0 3 1 10 Write Cycle[8, 9] Byte Enable to End of Write Shaded areas contain advance information. Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 5. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 9. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05134 Rev. *D Page 4 of 11 CY7C1041CV33 AC Test Loads and Waveforms[10] 8-, 10-ns Devices OUTPUT 50 Ω * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 1.5V Z = 50Ω 12-, 15-, 20-ns Devices 3.3V R 317 Ω 30 pF* OUTPUT 30 pF R2 351Ω (a) (b) High-Z Characteristics R 317 Ω 3.0V 90% GND 10% ALL INPUT PULSES 90% 10% 3.3V OUTPUT 5 pF R2 351Ω Rise Time: 1 V/ns (c) Fall Time: 1 V/ns (d) Switching Waveforms Read Cycle No. 1[11, 12] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled) [12, 13] ADDRESS tRC CE tACE OE BHE, BLE tDOE tLZOE tDBE tLZBE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZCE tHZBE DATA VALID tPD 50% IISB SB IICC CC tHZOE HIGH IMPEDANCE DATA OUT Notes: 10. AC characteristics (except High-Z) for all 8-ns and 10-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin load shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d). 11. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 12. WE is HIGH for Read cycle. 13. Address valid prior to or coincident with CE transition LOW. Document #: 38-05134 Rev. *D Page 5 of 11 CY7C1041CV33 Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[14, 15] tWC ADDRESS CE tSA tSCE tAW tPWE WE tBW BHE, BLE tSD DATAI/O tHD tHA Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tPWE WE tSCE CE tSD DATAI/O Notes: 14. Data I/O is high-impedance if OE or BHE and/or BLE = VIH. 15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. tHA tHD Document #: 38-05134 Rev. *D Page 6 of 11 CY7C1041CV33 Switching Waveforms (continued) Write Cycle No.3 (WE Controlled, OE LOW) tWC ADDRESS CE tSCE tAW tSA tPWE tHA WE tBW BHE, BLE tHZWE DATA I/O tLZWE tSD tHD Truth Table CE H L L L L L L L OE X L L L X X X H WE X H H H L L L H BLE X L L H L L H X BHE X L H L L H L X I/O0–I/O7 High-Z Data Out Data Out High-Z Data In Data In High-Z High-Z I/O8–I/O15 High-Z Data Out High-Z Data Out Data In High-Z Data In High-Z Power-down Read All Bits Read Lower Bits Only Read Upper Bits Only Write All Bits Write Lower Bits Only Write Upper Bits Only Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Document #: 38-05134 Rev. *D Page 7 of 11 CY7C1041CV33 Ordering Information CY7C1041CV33 Speed (ns) 10 Ordering Code CY7C1041CV33-10BAC CY7C1041CV33-10VC CY7C1041CV33-10ZC CY7C1041CV33-10BAI CY7C1041CV33-10VI CY7C1041CV33-10ZI 12 CY7C1041CV33-12BAC CY7C1041CV33-12VC CY7C1041CV33-12ZC CY7C1041CV33-12BAI CY7C1041CV33-12VI CY7C1041CV33-12ZI 15 CY7C1041CV33-15BAC CY7C1041CV33-15VC CY7C1041CV33-15ZC CY7C1041CV33-15BAI CY7C1041CV33-15VI CY7C1041CV33-15ZI 20 CY7C1041CV33-20BAC CY7C1041CV33-20VC CY7C1041CV33-20ZC CY7C1041CV33-20BAI CY7C1041CV33-20VI CY7C1041CV33-20ZI Package Name BA48B V34 Z44 BA48B V34 Z44 BA48B V34 Z44 BA48B V34 Z44 BA48B V34 Z44 BA48B V34 Z44 BA48B V34 Z44 BA48B V34 Z44 Package Type 48-ball Fine Pitch BGA 44-lead (400-mil) Molded SOJ 44-pin TSOP II Z44 48-ball Fine Pitch BGA 44-lead (400-mil) Molded SOJ 44-pin TSOP II Z44 48-ball Fine Pitch BGA 44-lead (400-mil) Molded SOJ 44-pin TSOP II Z44 48-ball Fine Pitch BGA 44-lead (400-mil) Molded SOJ 44-pin TSOP II Z44 48-ball Fine Pitch BGA 44-lead (400-mil) Molded SOJ 44-pin TSOP II Z44 48-ball Fine Pitch BGA 44-lead (400-mil) Molded SOJ 44-pin TSOP II Z44 48-ball Fine Pitch BGA 44-lead (400-mil) Molded SOJ 44-pin TSOP II Z44 48-ball Fine Pitch BGA 44-lead (400-mil) Molded SOJ 44-pin TSOP II Z44 Industrial Commercial Industrial Commercial Industrial Commercial Industrial Operating Range Commercial Document #: 38-05134 Rev. *D Page 8 of 11 CY7C1041CV33 Package Diagrams 48-ball (7.00 mm x 8.5 mm x 1.2 mm) FBGA BA48B 51-85106-*D 44-lead (400-mil) Molded SOJ V34 51-85082-*B Document #: 38-05134 Rev. *D Page 9 of 11 CY7C1041CV33 Package Diagrams (continued) 44-pin TSOP II Z44 51-85087-*A All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05134 Rev. *D Page 10 of 11 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1041CV33 Document History Page Document Title: CY7C1041CV33 256K x 16 Static RAM Document Number: 38-05134 REV. ** *A *B *C *D ECN NO. 109513 112440 112859 116477 119797 Issue Date 12/13/01 12/20/01 03/25/02 09/16/02 10/21/02 Orig. of Change HGK BSS DFP CEA DFP New Data Sheet Updated 51-85106 from revision *A to *C Added CY7C1042CV33 in BGA package Removed 1042 BGA option pin ACC Final Data Sheet Add applications foot note to data sheet Added 20-ns speed bin Description of Change Document #: 38-05134 Rev. *D Page 11 of 11