CY7C1049D-10VXIT

CY7C1049D 4-Mbit (512 K × 8) Static RAM 4-Mbit (512 K × 8) Static RAM provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). Features ■ Pin- and function-compatible with CY7C1049B ■ High speed ❐ tAA = 10 ns ■ Low active power ❐ ICC = 90 mA at 10 ns ■ Low CMOS Standby power ❐ ISB2 = 10 mA ■ 2.0 V data retention ■ Automatic power-down when deselected ■ TTL-compatible inputs and outputs ■ Easy memory expansion with CE and OE features ■ Available in Pb-free 36-pin (400-Mil) Molded SOJ package Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). Functional Description The CY7C1049D [1] is a high-performance CMOS static RAM organized as 512K words by 8 bits. Easy memory expansion is The CY7C1049D is available in a standard 400-mil-wide 36-pin SOJ package with center power and ground (revolutionary) pinout. The CY7C1049D is suitable for interfacing with processors that have TTL I/P levels. It is not suitable for processors that require CMOS I/P levels. Please see Electrical Characteristics on page 4 for more details and suggested alternatives. For a complete list of related documentation, click here. Logic Block Diagram I/O0 INPUT BUFFER I/O1 I/O2 512K x 8 SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 I/O3 I/O4 I/O5 COLUMN DECODER CE I/O6 POWER DOWN I/O7 A 11 A 12 A 13 A14 A15 A16 A17 A18 WE OE Note 1. For guidelines on SRAM system design, refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation Document Number: 38-05474 Rev. *H • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 24, 2014 CY7C1049D Contents Pin Configuration ............................................................. 3 Selection Guide ................................................................ 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 11 Document Number: 38-05474 Rev. *H Ordering Information ...................................................... 11 Ordering Code Definitions ......................................... 11 Package Diagram ............................................................ 12 Acronyms ........................................................................ 13 Document Conventions ................................................. 13 Units of Measure ....................................................... 13 Document History Page ................................................. 14 Sales, Solutions, and Legal Information ...................... 15 Worldwide Sales and Design Support ....................... 15 Products .................................................................... 15 PSoC® Solutions ...................................................... 15 Cypress Developer Community ................................. 15 Technical Support ..................................................... 15 Page 2 of 15 CY7C1049D Pin Configuration Figure 1. 36-pin SOJ pinout (Top View) SOJ Top View A0 A1 A2 A3 A4 CE I/O0 I/O1 VCC GND I/O2 I/O3 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A18 A17 A16 A15 OE I/O7 I/O6 GND VCC I/O5 I/O4 A14 A13 A12 A11 A10 NC Selection Guide Description -10 Unit Maximum access time 10 ns Maximum operating current 90 mA Maximum CMOS standby current 10 mA Document Number: 38-05474 Rev. *H Page 3 of 15 CY7C1049D DC Input Voltage [2] ............................ –0.5 V to VCC + 0.5 V Maximum Ratings Current into Outputs (LOW) ........................................ 20 mA Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Static Discharge Voltage (per MIL-STD-883, Method 3015) ........................... >2001 V Storage Temperature ............................... –65 qC to +150 qC Latch-Up Current .................................................... >200 mA Ambient Temperature with Power Applied ......................................... –55 qC to +125 qC Operating Range Supply Voltage on VCC to Relative GND [2] ...............................–0.5 V to +6.0 V Range DC Voltage Applied to Outputs in High Z State [2] ................................ –0.5 V to VCC + 0.5 V Ambient Temperature VCC –40 qC to +85 qC 4.5 V–5.5 V Industrial Electrical Characteristics Over the Operating Range Parameter VOH Description Output HIGH Voltage VCC = Min VCC = Max VOL Output LOW Voltage VIH[2] VIL[2] IIX Input Leakage Current IOZ ICC -10 Test Conditions IOH = –4.0 mA IOH = –0.1mA VCC = Min., IOL = 8.0 mA Min Max 2.4 – – 3.4 Unit V [3] – 0.4 V Input HIGH Voltage 2.0 VCC + 0.5 V Input LOW Voltage[2] –0.5 0.8 V GND < VI < VCC –1 +1 PA Output Leakage Current GND < VOUT < VCC, Output Disabled –1 +1 PA VCC Operating Supply Current VCC = Max., f = fMAX = 1/tRC – 90 mA 80 mA 70 mA 60 mA 100 MHz – 83 MHz – – 66 MHz – – 40 MHz – – ISB1 Automatic CE Power-Down Current – TTL Inputs Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX – 20 mA ISB2 Automatic CE Power-Down Current – CMOS Inputs Max. VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V, f = 0 – 10 mA Notes 2. Minimum voltage is –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns. 3. Please note that the maximum VOH limit does not exceed minimum CMOS VIH of 3.5 V. If you are interfacing this SRAM with 5 V legacy processors that require a minimum VIH of 3.5 V, please refer to Application Note AN6081 for technical details and options you may consider. Document Number: 38-05474 Rev. *H Page 4 of 15 CY7C1049D Capacitance Parameter [4] Description CIN Input capacitance COUT I/O capacitance Test Conditions Max Unit 8 pF 8 pF Test Conditions SOJ Package Unit Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 57.91 qC/W 36.73 qC/W TA = 25 qC, f = 1 MHz, VCC = 5.0 V Thermal Resistance Parameter [4] Description 4JA Thermal resistance (junction to ambient) 4JC Thermal resistance (junction to case) AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms [5] 10-ns device Z = 50: OUTPUT 3.0 V 50 : * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 1.5 V 30 pF* GND ALL INPUT PULSES 90% 90% 10% 10% d3 ns (a) d 3 ns (b) HIGH-Z CHARACTERISTICS R1 481: 5V OUTPUT 5 pF R2 255: THÉVENIN EQUIVALENT 167: 1.73 V OUTPUT Equivalent to: INCLUDING JIG AND SCOPE (c) Note 4. Tested initially and after any design or process changes that may affect these parameters. 5. AC characteristics (except High-Z) for 10-ns parts are tested using the load conditions shown in Figure 2 (a). High-Z characteristics are tested for all speeds using the test load shown in Figure 2 (c). Document Number: 38-05474 Rev. *H Page 5 of 15 CY7C1049D Data Retention Characteristics Over the Operating Range Parameter VDR Conditions [6] Description VCC for Data Retention ICCDR tCDR [7] tR[8] Data Retention Current VCC = VDR = 2.0 V, Chip Deselect to Data Retention CE > V – 0.3 V, CC Time Operation Recovery Time VIN > VCC – 0.3 V or VIN < 0.3 V Min Max Unit 2.0 – V – 10 mA 0 – ns tRC – ns Data Retention Waveform Figure 3. Data Retention Waveform DATA RETENTION MODE VCC 4.5 V VDR > 2 V tCDR 4.5 V tR CE Notes 6. No input may exceed VCC + 0.5 V. 7. Tested initially and after any design or process changes that may affect these parameters. 8. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 Ps or stable at VCC(min.) > 50 Ps. Document Number: 38-05474 Rev. *H Page 6 of 15 CY7C1049D Switching Characteristics Over the Operating Range Parameter [9] Description -10 Min Max Unit Read Cycle tpower VCC(typical) to the First Access [10] 100 – Ps tRC Read Cycle Time 10 – ns tAA Address to Data Valid – 10 ns tOHA Data Hold from Address Change 3 – ns tACE CE LOW to Data Valid – 10 ns tDOE OE LOW to Data Valid – 5 ns 0 – ns – 5 ns 3 – ns – 5 ns tLZOE OE LOW to Low Z [11] [11, 12] tHZOE OE HIGH to High Z tLZCE CE LOW to Low Z [11] [11, 12] tHZCE CE HIGH to High Z tPU CE LOW to Power-Up 0 – ns tPD CE HIGH to Power-Down – 10 ns Write Cycle [13, 14] tWC Write Cycle Time 10 – ns tSCE CE LOW to Write End 7 – ns tAW Address Set-Up to Write End 7 – ns tHA Address Hold from Write End 0 – ns tSA Address Set-Up to Write Start 0 – ns tPWE WE Pulse Width 7 – ns tSD Data Set-Up to Write End 6 – ns tHD Data Hold from Write End 0 – ns [11] 3 – ns [11, 12] – 5 ns tLZWE tHZWE WE HIGH to Low Z WE LOW to High Z Notes 9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 10. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 11. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 12. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of Figure 2. Transition is measured when the outputs enter a high impedance state. 13. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 14. The minimum write cycle time for Write Cycle No. 3 (WE Controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 38-05474 Rev. *H Page 7 of 15 CY7C1049D Switching Waveforms Figure 4. Read Cycle No. 1 [15, 16] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 5. Read Cycle No. 2 (OE Controlled) [16, 17] ADDRESS tRC CE tACE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZCE HIGH IMPEDANCE DATA VALID tPD tPU 50% 50% ICC ISB Notes 15. Device is continuously selected. OE, CE = VIL. 16. WE is HIGH for read cycle. 17. Address valid prior to or coincident with CE transition LOW. Document Number: 38-05474 Rev. *H Page 8 of 15 CY7C1049D Switching Waveforms(continued) Figure 6. Write Cycle No. 1 (CE Controlled) [18, 19] tWC ADDRESS tSCE CE tSA tSCE tAW tHA tPWE WE tSD DATA I/O tHD DATA VALID Figure 7. Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [18, 19] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE OE tSD DATA I/O tHD DATAIN VALID NOTE 20 tHZOE Notes 18. Data I/O is high impedance if OE = VIH. 19. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 20. During this period the I/Os are in the output state and input signals should not be applied. Document Number: 38-05474 Rev. *H Page 9 of 15 CY7C1049D Switching Waveforms(continued) Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [21, 22] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA I/O NOTE 23 tHD DATA VALID tHZWE tLZWE Note 21. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 22. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 23. During this period the I/Os are in the output state and input signals should not be applied. Document Number: 38-05474 Rev. *H Page 10 of 15 CY7C1049D Truth Table I/O0–I/O7 Mode Power CE OE WE H X X High-Z Power-down Standby (ISB) L L H Data Out Read Active (ICC) L X L Data In Write Active (ICC) L H H High-Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 10 Package Diagram Ordering Code CY7C1049D-10VXI Package Type 51-85090 36-pin SOJ (Molded) Pb-free Operating Range Industrial Please contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions CY 7 C 1 04 9 D - 10 V X I Temperature Range: I = Industrial Pb-free Package Type: V = 36-pin SOJ (Molded) Speed: 10 ns Process Technology: D = C9, 90 nm Technology Data width: 9 = × 8-bits Density: 04 = 4-Mbit density Family Code: 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 38-05474 Rev. *H Page 11 of 15 CY7C1049D Package Diagram Figure 9. 36-pin SOJ V36.4 (Molded) Package Outline, 51-85090 51-85090 *F Document Number: 38-05474 Rev. *H Page 12 of 15 CY7C1049D Acronyms Acronym Document Conventions Description Units of Measure CE Chip Enable CMOS Complementary Metal Oxide Semiconductor °C degree Celsius I/O Input/Output MHz megahertz OE Output Enable μA microampere SRAM Static Random Access Memory mA milliampere SOJ Small Outline J-Lead mV millivolt VFBGA Very Fine-Pitch Ball Grid Array mW milliwatt ns nanosecond Document Number: 38-05474 Rev. *H Symbol Unit of Measure pF picofarad V volt W watt Page 13 of 15 CY7C1049D Document History Page Document Title: CY7C1049D, 4-Mbit (512 K × 8) Static RAM Document Number: 38-05474 Revision ECN Orig. of Change Submission Date ** 201560 SWI See ECN Advance Datasheet for C9 IPP *A 233729 RKF See ECN 1.AC, DC parameters are modified as per EROS(Spec # 01-2165) 2.Pb-free offering in the ‘ordering information’ *B 351096 PCI See ECN Changed from Advance to Preliminary Removed 17, 20 ns Speed bin Added footnote # 4 Redefined ICC values for Com’l and Ind’l temperature ranges ICC (Com’l): Changed from 67 and 54 mA to 75 and 70 mA for 12 and 15 ns speed bins respectively ICC (Ind’l): Changed from 80, 67 and 54 mA to 90, 85 and 80 mA for 10, 12 and 15 ns speed bins respectively Added VIH(max) spec in Note# 2 Modified Note# 10 on tR Changed tSCE from 8 to 7 ns for 10 ns speed bin Changed reference voltage level for measurement of Hi-Z parameters from r500 mV to r200 mV Added Truth Table on page# 6 Removed L-Version Added 10 ns parts in the Ordering Information Table Added Lead-Free Product Information Shaded Ordering Information Table *C 446328 NXR See ECN Converted from Preliminary to Final Removed -12 and -15 speed bins Removed Commercial Operating Range product information Changed Maximum Rating for supply voltage from 7 V to 6 V Updated Thermal Resistance table Changed tHZWE from 6 ns to 5 ns Updated footnote #7 on High-Z parameter measurement Replaced Package Name column with Package Diagram in the Ordering Information table *D 3109184 AJU 12/13/2010 Added Ordering Code Definitions. Updated Package Diagram. *E 3235742 PRAS 04/20/2011 Added Acronyms and Units of measure. Updated template. *F 4040855 MEMJ 06/26/2013 Updated Functional Description. Updated Electrical Characteristics: Added one more Test Condition “VCC = Max, IOH = –0.1mA” for VOH parameter and added maximum value corresponding to that Test Condition. Added Note 3 and referred the same note in maximum value for VOH parameter corresponding to Test Condition “VCC = Max, IOH = –0.1mA”. Updated Package Diagram: spec 51-85090 – Changed revision from *E to *F. Updated in new template. *G 4391976 MEMJ 05/28/2014 Updated Switching Waveforms: Added Note 22 and referred the same note in Figure 8. Completing Sunset Review. *H 4578500 MEMJ 11/24/2014 Added related documentation hyperlink in page 1. Document Number: 38-05474 Rev. *H Description of Change Page 14 of 15 CY7C1049D Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2004-2014. 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Document Number: 38-05474 Rev. *H Revised November 24, 2014 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 15 of 15