CY7C199D-10VXIT

CY7C199D 256-Kbit (32K × 8) Static RAM 256-Kbit (32K × 8) Static RAM Features Functional Description ■ Temperature range ❐ –40 °C to 85 °C The CY7C199D is a high performance CMOS static RAM organized as 32,768 words by 8-bits. Easy memory expansion is provided by an active LOW chip enable (CE), an active LOW output enable (OE) and tri-state drivers. This device has an automatic power-down feature, reducing the power consumption when deselected. The input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW and WE LOW). ■ Pin and function compatible with CY7C199C ■ High speed ❐ tAA = 10 ns ■ Low active power ❐ ICC = 80 mA at 10 ns ■ Low CMOS standby power ❐ ISB2 = 3 mA ■ 2.0 V data retention ■ Automatic power-down when deselected ■ Complementary metal oxide semiconductor (CMOS) for optimum speed/power ■ Transistor-transistor logic (TTL) compatible inputs and outputs ■ Easy memory expansion with CE and OE features ■ Available in Pb-free 28-pin 300-Mil-wide molded small outline J-lead package (SOJ) and 28-pin thin small outline package (TSOP) I packages Write to the device by taking chip enable (CE) and write enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A14). Read from the device by taking chip enable (CE) and output enable (OE) LOW while forcing write enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appears on the I/O pins. The CY7C199D device is suitable for interfacing with processors that have TTL I/P levels. It is not suitable for processors that require CMOS I/P levels. Please see Electrical Characteristics on page 4 for more details and suggested alternatives. For a complete list of related documentation, click here. Logic Block Diagram I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Cypress Semiconductor Corporation Document Number: 38-05471 Rev. *M • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 4, 2017 CY7C199D Contents Pin Configurations ........................................................... 3 Selection Guide ................................................................ 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 10 Document Number: 38-05471 Rev. *M Ordering Information ...................................................... 10 Ordering Code Definitions ......................................... 10 Package Diagrams .......................................................... 11 Acronyms ........................................................................ 13 Document Conventions ................................................. 13 Units of Measure ....................................................... 13 Document History Page ................................................. 14 Sales, Solutions, and Legal Information ...................... 16 Worldwide Sales and Design Support ....................... 16 Products .................................................................... 16 PSoC® Solutions ...................................................... 16 Cypress Developer Community ................................. 16 Technical Support ..................................................... 16 Page 2 of 16 CY7C199D Pin Configurations Figure 1. 28-pin SOJ pinout (Top View) A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 Figure 2. 28-pin TSOP I pinout (Top View) OE A1 A2 A3 A4 WE VCC A5 A6 A7 A8 A9 A10 A11 22 23 24 25 26 27 28 1 2 3 4 5 6 7 TSOP I Top View (not to scale) 21 20 19 18 17 16 15 14 13 12 11 10 9 8 A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A14 A13 A12 Selection Guide -10 (Industrial) Unit Maximum access time Description 10 ns Maximum operating current 80 mA Maximum CMOS standby current 3 mA Document Number: 38-05471 Rev. *M Page 3 of 16 CY7C199D DC input voltage [1] ............................. –0.5 V to VCC + 0.5 V Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –65 C to +150 C Ambient temperature with power applied ................................... –55 C to +125 C Supply voltage on VCC to relative GND [1] ...........................–0.5 V to +6.0 V DC voltage applied to outputs in high Z State [1] ................................ –0.5 V to VCC + 0.5 V Output current into outputs (LOW) ............................. 20 mA Static discharge voltage (per MIL-STD-883, method 3015) ........................ > 2,001 V Latch-up current ................................................... > 140 mA Operating Range Range Ambient Temperature VCC Speed Industrial –40 C to +85 C 5 V  0.5 V 10 ns Electrical Characteristics Over the operating range Parameter VOH VOL Description Output HIGH voltage IOH = –4.0 mA Min Max 2.4 – IOH = –0.1mA – IOL = 8.0 mA 3.4 Unit V [2] – 0.4 V Input HIGH voltage [1] 2.2 VCC + 0.5 V VIL Input LOW voltage [1] –0.5 0.8 V IIX Input leakage current GND < VI < VCC –1 +1 µA IOZ Output leakage current GND < VO < VCC, output disabled –1 +1 µA ICC VCC operating supply current VCC = VCC(max), IOUT = 0 mA, f = fmax = 1/tRC 100 MHz – 80 mA 83 MHz – 72 mA 66 MHz – 58 mA 40 MHz – 37 mA VIH Output LOW voltage CY7C199D-10 Test Conditions ISB1 Automatic CE power-down current – TTL Inputs VCC = VCC(max), CE > VIH, VIN > VIH or VIN < VIL, f = fmax – 10 mA ISB2 Automatic CE power-down current – CMOS Inputs VCC = VCC(max), CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V, f = 0 – 3 mA Note 1. VIL(min) = –2.0 V and VIH(max) = VCC + 1 V for pulse durations of less than 5 ns. 2. Please note that the maximum VOH limit does not exceed minimum CMOS VIH of 3.5 V. If you are interfacing this SRAM with 5 V legacy processors that require a minimum VIH of 3.5 V, please refer to Application Note AN6081 for technical details and options you may consider. Document Number: 38-05471 Rev. *M Page 4 of 16 CY7C199D Capacitance Parameter [3] Description CIN Input capacitance COUT Output capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 5.0 V Max Unit 8 pF 8 pF Thermal Resistance Parameter [3] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions 28-pin SOJ 28-pin TSOP I Unit Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 59.16 54.65 C/W 40.84 21.49 C/W AC Test Loads and Waveforms Figure 3. AC Test Loads and Waveforms [4] Z = 50  ALL INPUT PULSES OUTPUT 3.0 V 50  * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 30pF* GND 10% 90% 10% 90% 1.5 V Rise Time: 3 ns (a) High Z characteristics: (b) Fall Time: 3 ns R1 480  5V OUTPUT R2 255  5 pF INCLUDING JIG AND SCOPE (c) Notes 3. Tested initially and after any design or process changes that may affect these parameters. 4. AC characteristics (except high Z) are tested using the load conditions shown in Figure 3 (a). High Z characteristics are tested for all speeds using the test load shown in Figure 3 (c). Document Number: 38-05471 Rev. *M Page 5 of 16 CY7C199D Data Retention Characteristics Over the operating range Parameter Description Conditions Min Max Unit 2.0 – V – 3 mA VDR VCC for data retention ICCDR Data retention current tCDR [5] Chip deselect to data retention time 0 – ns tR [6] Operation recovery time 15 – ns VCC = VDR = 2.0 V, CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V Data Retention Waveform Figure 4. Data Retention Waveform DATA RETENTION MODE VCC 4.5 V VDR > 2 V tCDR 4.5 V tR CE Notes 5. Tested initially and after any design or process changes that may affect these parameters. 6. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 µs or stable at VCC(min) > 50 µs. Document Number: 38-05471 Rev. *M Page 6 of 16 CY7C199D Switching Characteristics Over the operating range Parameter [7] Description CY7C199D-10 Min Max Unit Read Cycle tpower [8] VCC(typical) to the first access 100 – s tRC Read cycle time 10 – ns tAA Address to data valid – 10 ns tOHA Data hold from address change 3 – ns tACE CE LOW to data valid – 10 ns tDOE OE LOW to data valid – 5 ns tLZOE [9] OE LOW to low Z 0 – ns tHZOE [9, 10] OE HIGH to high Z – 5 ns CE LOW to low Z 3 – ns tLZCE [9] tHZCE [9, 10] CE HIGH to high Z – 5 ns tPU [11] CE LOW to power-up 0 – ns tPD [11] CE HIGH to power-down – 10 ns Write Cycle [12, 13] tWC Write cycle time 10 – ns tSCE CE LOW to write end 7 – ns tAW Address setup to write end 7 – ns tHA Address hold from write end 0 – ns tSA Address setup to write start 0 – ns tPWE WE pulse width 7 – ns tSD Data setup to write end 6 – ns tHD Data hold from write end 0 – ns tHZWE [9] WE LOW to high Z – 5 ns tLZWE [9, 10] WE HIGH to low Z 3 – ns Notes 7. Test conditions assume signal transition time of 3 ns or less for all speeds, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 8. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 10. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of Figure 3 on page 5. Transition is measured 200 mV from steady-state voltage. 11. This parameter is guaranteed by design and is not tested. 12. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write. 13. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 38-05471 Rev. *M Page 7 of 16 CY7C199D Switching Waveforms Figure 5. Read Cycle No. 1 (Address Transition Controlled) [14, 15] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 6. Read Cycle No. 2 (OE Controlled) [15, 16] tRC CE tACE OE DATA OUT tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZOE tHZCE HIGH IMPEDANCE DATA VALID tPD tPU ICC 50% 50% ISB Notes 14. Device is continuously selected. OE, CE = VIL. 15. WE is HIGH for read cycle. 16. Address valid prior to or coincident with CE transition LOW. Document Number: 38-05471 Rev. *M Page 8 of 16 CY7C199D Switching Waveforms (continued) Figure 7. Write Cycle No. 1 (CE Controlled) [17, 18, 19] tWC ADDRESS tSCE CE tSA tAW tHA WE tSD DATA I/O tHD DATA IN VALID Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [19, 20] tWC ADDRESS CE tAW tHA tSA WE tSD DATA IO NOTE 21 tHD DATAIN VALID tHZWE tLZWE Notes 17. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write. 18. Data I/O is high impedance if OE = VIH. 19. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 20. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 21. During this period the I/Os are in the output state and input signals should not be applied. Document Number: 38-05471 Rev. *M Page 9 of 16 CY7C199D Truth Table CE WE OE Inputs/Outputs Mode Power H X X High Z Deselect/power-down Standby (ISB) L H L Data out Read Active (ICC) L L X Data in Write Active (ICC) L H H High Z Deselect, output disabled Active (ICC) Ordering Information Cypress offers other versions of this type of product in many different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at http://www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Speed (ns) 10 Ordering Code Package Diagram Package Type CY7C199D-10VXI 51-85031 28-pin Molded SOJ (300 Mils) (Pb-free) CY7C199D-10ZXI 51-85071 28-pin TSOP I (Pb-free) Operating Range Industrial Please contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions CY 7 C 1 9 9 D - XX X X I Temperature Grade: I = Industrial Pb-free Package Type: V or Z V = 28 pin Molded SOJ (300 Mils) Z = 28 pin TSOP I Speed Grade: 10 ns Process Technology: D = 90 nm Bus Width: 9 = × 8 Density: 9 = 256K Family Code: 1 = Fast SRAM Family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 38-05471 Rev. *M Page 10 of 16 CY7C199D Package Diagrams Figure 9. 28-pin SOJ (300 Mils) V28.3 (Molded SOJ V21) Package Outline, 51-85031 51-85031 *F Document Number: 38-05471 Rev. *M Page 11 of 16 CY7C199D Package Diagrams (continued) Figure 10. 28-pin TSOP I (8 × 13.4 × 1.2 mm) Z28R (Standard) Package Outline, 51-85071 51-85071 *J Document Number: 38-05471 Rev. *M Page 12 of 16 CY7C199D Acronyms Acronym Document Conventions Description Units of Measure CE Chip Enable CMOS Complementary Metal Oxide Semiconductor °C degree Celsius I/O Input/Output µA microampere OE Output Enable µs microsecond SOJ Small Outline J-lead mA milliampere SRAM Static Random Access Memory mm millimeter TSOP Thin Small Outline Package ns nanosecond TTL Transistor-Transistor Logic WE Write Enable Document Number: 38-05471 Rev. *M Symbol Unit of Measure pF picofarad V volt W watt Page 13 of 16 CY7C199D Document History Page Document Title: CY7C199D, 256-Kbit (32K × 8) Static RAM Document Number: 38-05471 Revision ECN Orig. of Change Submission Date ** 201560 SWI See ECN Advance Information datasheet for C9 IPP *A 233728 RKF See ECN DC parameters modified as per EROS (Spec # 01-02165) Pb-free Offering in Ordering Information *B 262950 RKF See ECN Removed 28-LCC Pinout and Package Diagrams Added Data Retention Characteristics table Added Tpower Spec in Switching Characteristics table Shaded Ordering Information *C 307594 RKF See ECN Reduced Speed bins to -10, -12 and -15 ns *D 820660 VKN See ECN Converted from Preliminary to Final Removed 12 ns and 15 ns speed bin Removed Commercial Operating range Removed “L” part Removed 28-pin PDIP and 28-pin SOIC package Changed Overshoot spec from VCC+2V to VCC+1V in footnote #2 Changed ICC spec from 60 mA to 80 mA for 100 MHz speed bin Added ICC specs for 83 MHz, 66 MHz and 40 MHz speed bins Updated Thermal Resistance table Updated Ordering Information Table *E 2745093 VKN See ECN Included 28-Pin SOIC package Changed VIH level from 2.0V to 2.2V For Industrial grade, changed tSD from 5 ns to 6 ns, and tHZWE from 6 ns to 5 ns Included Automotive-E information *F 2897087 AJU 03/22/10 Removed obsolete parts from ordering information table Updated Package Diagrams. *G 3023234 RAME 09/06/2010 *H 3130763 PRAS 01/07/11 *I 3271782 PRAS 06/02/2011 Updated Functional Description (Removed “For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.”). Updated Package Diagrams. Updated to new template. *J 4033580 MEMJ 06/19/2013 Updated Functional Description. Updated Electrical Characteristics. Added one more Test Condition “IOH = –0.1 mA” for VOH parameter and added maximum value corresponding to that Test Condition. Added Note 2 and referred the same note in maximum value for VOH parameter corresponding to Test Condition “IOH = –0.1 mA”. Updated Package Diagrams: spec 51-85031 – Changed revision from *D to *E. *K 4347624 MEMJ 04/15/2014 Updated Package Diagrams: spec 51-85071 – Changed revision from *I to *J. Completing Sunset Review. *L 4576526 MEMJ 11/21/2014 Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. Document Number: 38-05471 Rev. *M Description of Change Added Auto-E SOIC package related info Changed TDOE spec from 10 ns to 11 ns in CY7C199D-25. Added Ordering Code Definitions. Added Acronyms and Units of Measure. Dislodged Automotive information to a new datasheet (001-65530) Page 14 of 16 CY7C199D Document History Page (continued) Document Title: CY7C199D, 256-Kbit (32K × 8) Static RAM Document Number: 38-05471 Revision ECN Orig. of Change Submission Date *M 5725425 VINI 05/04/2017 Document Number: 38-05471 Rev. *M Description of Change Updated Package Diagrams: spec 51-85031 – Changed revision from *E to *F. Updated to new template. Completing Sunset Review. Page 15 of 16 CY7C199D Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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