CY7C106D-10VXIT

CY7C106D CY7C1006D 1-Mbit (256 K × 4) Static RAM 1-Mbit (256 K × 4) Static RAM Features ■ Pin- and function-compatible with CY7C106B/CY7C1006B ■ High speed ❐ tAA = 10 ns ■ Low active power ❐ ICC = 80 mA @ 10 ns ■ Low CMOS standby power ❐ ISB2 = 3.0 mA ■ 2.0 V Data Retention ■ Automatic power-down when deselected ■ CMOS for optimum speed/power ■ TTL-compatible inputs and outputs ■ CY7C106D available in Pb-free 28-pin 400-Mil wide Molded SOJ package. CY7C1006D available in Pb-free 28-pin 300-Mil wide Molded SOJ package memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. These devices have an automatic power-down feature that reduces power consumption by more than 65% when the devices are deselected. The four input and output pins (IO0 through IO3) are placed in a high-impedance state when: ■ Deselected (CE HIGH) ■ Outputs are disabled (OE HIGH) ■ When the write operation is active (CE and WE LOW) Write to the device by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the four IO pins (IO0 through IO3) is then written into the location specified on the address pins (A0 through A17). Functional Description The CY7C106D [1] and CY7C1006D [1] are high-performance CMOS static RAMs organized as 262,144 words by 4 bits. Easy Read from the device by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appears on the four IO pins. Both CY7C106D and CY7C1006D devices are suitable for interfacing with processors that have TTL I/P levels. They are not suitable for processors that require CMOS I/P levels. Please see Electrical Characteristics on page 4 for more details and suggested alternatives. Logic Block Diagram 256K x 4 ARRAY CE COLUMN DECODER WE IO1 IO2 IO3 POWER DOWN A0 A10 A11 A12 A13 A14 A15 A16 A17 OE IO0 SENSE AMPS A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER INPUT BUFFER Note 1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation Document Number: 38-05459 Rev. *I • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 19, 2013 CY7C106D CY7C1006D Contents Pin Configurations ........................................................... 3 Selection Guide ................................................................ 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 11 Document Number: 38-05459 Rev. *I Ordering Information ...................................................... 11 Ordering Code Definitions ......................................... 11 Package Diagrams .......................................................... 12 Acronyms ........................................................................ 14 Document Conventions ................................................. 14 Units of Measure ....................................................... 14 Document History Page ................................................. 15 Sales, Solutions and Legal Information ....................... 16 Worldwide Sales and Design Support ....................... 16 Products .................................................................... 16 PSoC® Solutions ...................................................... 16 Cypress Developer Community ................................. 16 Technical Support ..................................................... 16 Page 2 of 16 CY7C106D CY7C1006D Pin Configurations Figure 1. 28-pin SOJ pinout (Top View) [2] A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 CE OE GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A17 A16 A15 A14 A13 A12 A11 NC IO3 IO2 IO1 IO0 WE Selection Guide CY7C106D-10 CY7C1006D-10 Unit Maximum Access Time 10 ns Maximum Operating Current 80 mA Maximum Standby Current 3 mA Note 2. NC pins are not connected on the die. Document Number: 38-05459 Rev. *I Page 3 of 16 CY7C106D CY7C1006D DC Input Voltage [3] ............................ –0.5 V to VCC + 0.5 V Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ............................... –65 °C to +150 °C Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage (per MIL-STD-883, Method 3015) .......................... > 2001 V Latch-up Current..................................................... > 200 mA Ambient Temperature with Power Applied ......................................... –55 °C to +125 °C Operating Range Supply Voltage on VCC Relative to GND [3] ..–0.5 V to +6.0 V DC Voltage Applied to Outputs in High Z State [3] ................................ –0.5 V to VCC + 0.5 V Range Ambient Temperature VCC Speed Industrial –40 °C to +85 °C 5 V  0.5 V 10 ns Electrical Characteristics Over the Operating Range Parameter VOH Description Output HIGH Voltage 7C106D-10 7C1006D-10 Test Conditions IOH = –4.0 mA Unit Min Max 2.4 – 3.4 V [4] IOH = –0.1 mA – IOL = 8.0 mA – 0.4 V VOL Output LOW Voltage VIH Input HIGH Voltage 2.2 VCC + 0.5 V VIL Input LOW Voltage [3] –0.5 0.8 V IIX Input Leakage Current GND < VI < VCC –1 +1 A IOZ Output Leakage Current GND < VI < VCC, Output Disabled –1 +1 A ICC VCC Operating Supply Current VCC = Max, IOUT = 0 mA, f = fmax = 1/tRC 100 MHz – 80 mA 83 MHz – 72 mA 66 MHz – 58 mA 40 MHz – 37 mA ISB1 Automatic CE Power-Down Current—TTL Inputs Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fmax – 10 mA ISB2 Automatic CE Power-Down Current—CMOS Inputs Max VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V, f = 0 – 3 mA Note 3. VIL (min) = –2.0 V and VIH(max) = VCC + 1 V for pulse durations of less than 5 ns. 4. Please note that the maximum VOH limit does not exceed minimum CMOS VIH of 3.5 V. If you are interfacing this SRAM with 5 V legacy processors that require a minimum VIH of 3.5 V, please refer to Application Note AN6081 for technical details and options you may consider. Document Number: 38-05459 Rev. *I Page 4 of 16 CY7C106D CY7C1006D Capacitance Parameter [5] CIN: Addresses Description Test Conditions Input Capacitance Max TA = 25 °C, f = 1 MHz, VCC = 5.0 V 7 pF 10 pF 10 pF CIN: Controls COUT Output Capacitance Unit Thermal Resistance Parameter [5] Test Conditions 300-Mil Wide SOJ 400-Mil Wide SOJ Unit Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 59.16 58.76 °C/W 40.84 40.54 °C/W Description JA Thermal Resistance (Junction to Ambient) JC Thermal Resistance (Junction to Case) AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms [6] ALL INPUT PULSES 3.0 V Z = 50  90% OUTPUT 50  * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 30 pF* 90% 10% 10% GND 1.5 V Rise Time: 3 ns (a) (b) Fall Time: 3 ns High Z characteristics: R1 480 5V OUTPUT INCLUDING JIG AND SCOPE R2 255 5 pF (c) Notes 5. Tested initially and after any design or process changes that may affect these parameters. 6. AC characteristics (except High Z) are tested using the load conditions shown in part (a) of Figure 2. High Z characteristics are tested for all speeds using the test load shown in part (c) of Figure 2. Document Number: 38-05459 Rev. *I Page 5 of 16 CY7C106D CY7C1006D Data Retention Characteristics Over the Operating Range Parameter Description Conditions VDR VCC for Data Retention ICCDR Data Retention Current tCDR [7] Chip Deselect to Data Retention Time tR [8, 9] Operation Recovery Time Min Max Unit 2.0 – V – 3 mA VCC = VDR = 2.0 V, CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V 0 – ns tRC – ns Data Retention Waveform Figure 3. Data Retention Waveform DATA RETENTION MODE VCC 4.5 V VDR > 2 V tCDR 4.5 V tR CE Notes 7. Tested initially and after any design or process changes that may affect these parameters. 8. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s. 9. tr < 3 ns for all speeds. Document Number: 38-05459 Rev. *I Page 6 of 16 CY7C106D CY7C1006D Switching Characteristics Over the Operating Range [10] Parameter 7C106D-10 7C1006D-10 Description Unit Min Max Read Cycle tpower [11] VCC(typical) to the first access 100 – s tRC Read Cycle Time 10 – ns tAA Address to Data Valid – 10 ns tOHA Data Hold from Address Change 3 – ns tACE CE LOW to Data Valid – 10 ns tDOE OE LOW to Data Valid – 5 ns tLZOE OE LOW to Low Z 0 – ns – 5 ns 3 – ns – 5 ns CE LOW to Power-Up 0 – ns CE HIGH to Power-Down – 10 ns tHZOE tLZCE tHZCE tPU [14] tPD [14] Write Cycle OE HIGH to High Z CE LOW to Low Z [12, 13] [13] CE HIGH to High Z [12, 13] [15, 16] tWC Write Cycle Time 10 – ns tSCE CE LOW to Write End 7 – ns tAW Address Set-Up to Write End 7 – ns tHA Address Hold from Write End 0 – ns tSA Address Set-Up to Write Start 0 – ns tPWE WE Pulse Width 7 – ns tSD Data Set-Up to Write End 6 – ns tHD Data Hold from Write End 0 – ns tLZWE WE HIGH to Low Z [13] 3 – ns tHZWE WE LOW to High Z [12, 13] – 5 ns Notes 10. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 11. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 12. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of AC Test Loads and Waveforms on page 5. Transition is measured when the outputs enter a high impedance state. 13. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 14. This parameter is guaranteed by design and is not tested. 15. The internal write time of the memory is defined by the overlap of CE and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 16. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 38-05459 Rev. *I Page 7 of 16 CY7C106D CY7C1006D Switching Waveforms Figure 4. Read Cycle No.1 (Address Transition Controlled) [17, 18] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 5. Read Cycle No. 2 (OE Controlled) [18, 19] ADDRESS tRC CE tACE OE tHZOE tDOE tLZOE HIGH IMPEDANCE DATA OUT VCC SUPPLY CURRENT tLZCE tHZCE HIGH IMPEDANCE DATA VALID tPD tPU 50% 50% ICC ISB Notes 17. Device is continuously selected, OE and CE = VIL. 18. WE is HIGH for read cycle. 19. Address valid prior to or coincident with CE transition LOW. Document Number: 38-05459 Rev. *I Page 8 of 16 CY7C106D CY7C1006D Switching Waveforms (continued) Figure 6. Write Cycle No. 1 (CE Controlled) [20, 21] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tSD DATA IO tHD DATA VALID Figure 7. Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [20, 21] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE OE tSD tHD DATA VALID DATA IO tHZOE Notes 20. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 21. Data IO is high impedance if OE = VIH. Document Number: 38-05459 Rev. *I Page 9 of 16 CY7C106D CY7C1006D Switching Waveforms (continued) Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [22, 23] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD tHD DATA VALID DATA IO tHZWE tLZWE Notes 22. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 23. Data IO is high impedance if OE = VIH. Document Number: 38-05459 Rev. *I Page 10 of 16 CY7C106D CY7C1006D Truth Table CE OE WE Input/Output Mode Power H X X High Z Power-Down Standby (ISB) L L H Data Out Read Active (ICC) L X L Data In Write Active (ICC) L H H High Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 10 Ordering Code Package Diagram Package Type CY7C106D-10VXI 51-85032 28-pin (400-Mil) Molded SOJ (Pb-free) CY7C1006D-10VXI 51-85031 28-pin (300-Mil) Molded SOJ (Pb-free) Operating Range Industrial Please contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions CY 7 C 1 xx6 D - 10 VX I Temperature Range: I = Industrial Package Type: VX = 28-pin Molded SOJ (Pb-free) Speed: 10 ns D = C9, 90 nm Technology xx6 = 06 or 006 = (400-Mil / 300-Mil) 1-Mbit density 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS 7 = SRAM CY = Cypress Document Number: 38-05459 Rev. *I Page 11 of 16 CY7C106D CY7C1006D Package Diagrams Figure 9. 28-pin SOJ (300 Mils) V28.3 (Molded SOJ V21) Package Outline, 51-85031 51-85031 *E Document Number: 38-05459 Rev. *I Page 12 of 16 CY7C106D CY7C1006D Package Diagrams (continued) Figure 10. 28-pin (400 Mils) V28.4 (Molded SOJ V28) Package Outline, 51-85032 51-85032 *E Document Number: 38-05459 Rev. *I Page 13 of 16 CY7C106D CY7C1006D Acronyms Acronym Document Conventions Description CE Chip Enable CMOS Complementary Metal-Oxide Semiconductor I/O Input/Output OE Output Enable SOJ Small Outline J-lead SRAM Static Random Access Memory TTL Transistor-Transistor Logic WE Write Enable Document Number: 38-05459 Rev. *I Units of Measure Symbol Unit of Measure °C degree Celsius MHz megahertz µA microampere µs microsecond mA milliampere ns nanosecond  ohm % percent pF picofarad V volt W watt Page 14 of 16 CY7C106D CY7C1006D Document History Page Document Title: CY7C106D/CY7C1006D, 1-Mbit (256 K × 4) Static RAM Document Number: 38-05459 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 201560 See ECN SWI Advance information data sheet for C9 IPP *A 233693 See ECN RKF ICC,ISB1,ISB2 Specs are modified as per EROS (Spec # 01-2165) Pb-free offering in the ‘ordering information’ *B 262950 See ECN RKF Added Tpower Spec in Switching Characteristics table Shaded ‘Ordering Information’ *C See ECN See ECN RKF Reduced Speed bins to -10 and -12 ns *D 560995 See ECN VKN Converted from Preliminary to Final Removed Commercial Operating range Removed 12 ns speed bin Added ICC values for the frequencies 83MHz, 66MHz and 40MHz Updated Thermal Resistance table Updated Ordering Information table Changed Overshoot spec from VCC+2V to VCC+1V in footnote #3 *E 802877 See ECN VKN Changed ICC spec from 60 mA to 80 mA for 100MHz, 55 mA to 72 mA for 83MHz, 45 mA to 58 mA for 66MHz, 30 mA to 37 mA for 40MHz *F 2898399 03/24/2010 AJU Updated Package Diagrams *G 3104943 12/08/2010 AJU Added Ordering Code Definitions. *H 3244490 04/29/2011 PRAS Updated Package Diagrams. Added Acronyms and Units of Measure. Updated in new template. *I 4033580 06/19/2013 MEMJ Updated Functional Description. Updated Electrical Characteristics: Added one more Test Condition “IOH = –0.1 mA” for VOH parameter and added maximum value corresponding to that Test Condition. Added Note 4 and referred the same note in maximum value for VOH parameter corresponding to Test Condition “IOH = –0.1 mA”. Updated Package Diagrams: spec 51-85031 – Changed revision from *D to *E. Document Number: 38-05459 Rev. *I Page 15 of 16 CY7C106D CY7C1006D Sales, Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive cypress.com/go/automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2004-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05459 Rev. *I Revised June 19, 2013 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 16 of 16