CY7C1061BV33-10ZI

CY7C1061BV33 16-Mbit (1M x 16) Static RAM Features • High speed — tAA = 10 ns • Low active power — 990 mW (max.) • Operating voltages of 3.3 ± 0.3V • 2.0V data retention • Automatic power-down when deselected • TTL-compatible inputs and outputs • Available in Pb-free and non Pb-free 54-pin TSOP II package Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). Reading from the device is accomplished by enabling the chip by taking CE LOW while forcing the Output Enable (OE) LOW and the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of Read and Write modes. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a Write operation (CE LOW and WE LOW). The CY7C1061BV33 is available in a 54-pin TSOP II package with center power and ground (revolutionary) pinout. Functional Description The CY7C1061BV33 is a high-performance CMOS Static RAM organized as 1,048,576 words by 16 bits. Writing to the device is accomplished by enabling the chip (CE LOW) while forcing the Write Enable (WE) input LOW. If Byte Logic Block Diagram Pin Configurations[1, 2] 54-pin TSOP II (Top View) INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 1M x 16 ARRAY I/O0–I/O7 I/O8–I/O15 COLUMN DECODER BHE WE CE OE BLE I/O12 VCC I/O13 I/O14 VSS I/O15 A4 A3 A2 A1 A0 BHE CE VCC WE DNU/VCC A19 A18 A17 A16 A15 I/O0 VCC I/O1 I/O2 VSS I/O3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 I/O11 VSS I/O10 I/O9 VCC I/O8 A5 A6 A7 A8 A9 NC OE VSS DNU/VSS BLE A10 A11 A12 A13 A14 I/O7 VSS I/O6 I/O5 VCC I/O4 ROW DECODER Notes: 1. DNU/VCC Pin (#16) has to be left floating or connected to VCC and DNU/VSS Pin (#40) has to be left floating or connected to VSS to ensure proper application. 2. NC – No Connect Pins are not connected to the die A10 A11 A 12 A 13 A 14 A15 A16 A17 A18 A19 SENSE AMPS Cypress Semiconductor Corporation Document #: 38-05693 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 3, 2006 [+] [+] Feedback CY7C1061BV33 Selection Guide –10 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Commercial Industrial Commercial/Industrial 10 275 275 50 –12 12 260 260 50 mA Unit ns mA Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC to Relative GND[3] –0.5V to +4.6VDC Voltage Applied to Outputs in High-Z State[3] ....................................–0.5V to VCC + 0.5V DC Input Voltage[3] ................................ –0.5V to VCC + 0.5V Current into Outputs (LOW)......................................... 20 mA Operating Range Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 3.3V ± 0.3V DC Electrical Characteristics Over the Operating Range –10 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[3] Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-down Current —TTL Inputs Automatic CE Power-down Current —CMOS Inputs GND < VI < VCC GND < VOUT < VCC, Output Disabled VCC = Max., f = fMAX = 1/tRC Commercial Industrial Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA 2.0 –0.3 –1 –1 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 275 275 70 2.0 –0.3 –1 –1 Max. Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 260 260 70 –12 Max. Unit V V V V µA µA mA mA mA Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 Commercial/ Industrial ISB2 50 50 mA Capacitance[4] Parameter CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max. 6 8 Unit pF pF Thermal Resistance[4] Parameter Description Test Conditions 54-pin TSOP-II 49.95 3.34 Unit °C/W °C/W ΘJA ΘJC Thermal Resistance (Junction to Ambient) Test conditions follow standard test methods and procedures for Thermal Resistance (Junction to Case) measuring thermal impedance, per EIA/JESD51. Notes: 3. VIL (min.) = –2.0V and VIH(max) = VCC + 0.5V for pulse durations of less than 20 ns. 4. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05693 Rev. *B Page 2 of 9 [+] [+] Feedback CY7C1061BV33 AC Test Loads and Waveforms[5] 50Ω OUTPUT Z0 = 50Ω 30 pF* VTH = 1.5V * Capacitive Load consists of all components of the test environment. ALL INPUT PULSES 3.3V 90% GND Rise time > 1V/ns 10% 90% 10% Fall time: > 1V/ns 3.3V OUTPUT 5 pF* INCLUDING JIG AND SCOPE R2 351Ω R1 317 Ω (a) (b) (c) AC Switching Characteristics Over the Operating Range[6] –10 Parameter Read Cycle tpower tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE VCC(typical) to the first access[7] Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z OE HIGH to CE HIGH to CE LOW to CE HIGH to High-Z[8] 3 5 0 10 5 1 5 1 6 0 12 6 High-Z[8] Power-Up[9] Power-Down[9] CE LOW to Low-Z[8] 1 5 3 6 3 10 5 1 6 1 10 10 3 12 6 1 12 12 ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Min. –12 Max. Unit Byte Enable to Data Valid Byte Enable to Low-Z Byte Disable to High-Z Notes: 5. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). As soon as 1ms (Tpower) after reaching the minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage. 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and specified transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise. 7. This part has a voltage regulator which steps down the voltage from 3V to 2V internally. tpower time has to be provided initially before a Read/Write operation is started. 8. tHZOE, tHZCE, tHZWE, tHZBE and tLZOE, tLZCE, t\LZWE, tLZBE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage. 9. These parameters are guaranteed by design and are not tested. 10. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Chip enables must be active and WE and byte enables must be LOW to initiate a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 11. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05693 Rev. *B Page 3 of 9 [+] [+] Feedback CY7C1061BV33 AC Switching Characteristics Over the Operating Range[6] (continued) –10 Parameter Write tWC tSCE tAW tSA tPWE tSD tHD tLZWE tHZWE tBW tHA Cycle[10, 11] Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE HIGH to Low-Z[8] WE LOW to High-Z[8] 7 0 Byte Enable to End of Write Address Hold from Write End 10 7 7 0 7 5.5 0 3 5 8 0 12 8 7 0 8 6 0 3 6 ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Min. –12 Max. Unit Data Retention Waveform DATA RETENTION MODE VCC 3.0V tCDR CE VDR > 2V 3.0V tR Switching Waveforms Read Cycle No. 1[12, 13] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Notes: 12. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 13. WE is HIGH for Read cycle. Document #: 38-05693 Rev. *B Page 4 of 9 [+] [+] Feedback CY7C1061BV33 Switching Waveforms (continued) Read Cycle No. 2 (OE Controlled)[13, 14] ADDRESS tRC CE tACE OE BHE, BLE tDOE tLZOE tDBE tLZBE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZCE tHZBE DATA VALID tPD 50% IICC CC ISB tHZOE HIGH IMPEDANCE DATA OUT Write Cycle No. 1 (CE Controlled)[15, 16] tWC ADDRESS CE tSA tSCE tAW tPWE WE tBW BHE, BLE tSD DATAI/O tHD tHA Notes: 14. Address valid prior to or coincident with CE transition LOW. 15. Data I/O is high-impedance if OE or BHE and/or BLE = VIH. 16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05693 Rev. *B Page 5 of 9 [+] [+] Feedback CY7C1061BV33 Switching Waveforms (continued) Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tPWE WE tSCE CE tSD DATAI/O tHD tHA Write Cycle No. 3 (WE Controlled, OE LOW)[15, 16] tWC ADDRESS CE tSCE tAW tSA tPWE tHA WE tBW BHE, BLE tHZWE DATA I/O tLZWE tSD tHD Document #: 38-05693 Rev. *B Page 6 of 9 [+] [+] Feedback CY7C1061BV33 Truth Table CE H L L L L L L L OE X L L L X X X H WE X H H H L L L H BLE X L L H L L H X BHE X L H L L H L X I/O0–I/O7 High-Z Data Out Data Out High-Z Data In Data In High-Z High-Z I/O8–I/O15 High-Z Data Out High-Z Data Out Data In High-Z Data In High-Z Power-down Read All Bits Read Lower Bits Only Read Upper Bits Only Write All Bits Write Lower Bits Only Write Upper Bits Only Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 10 Ordering Code CY7C1061BV33-10ZC CY7C1061BV33-10ZI CY7C1061BV33-10ZXC CY7C1061BV33-10ZXI CY7C1061BV33-12ZC CY7C1061BV33-12ZI CY7C1061BV33-12ZXC CY7C1061BV33-12ZXI Package Name 51-85160 Package Type 54-pin TSOP II 54-pin TSOP II (Pb-free) 54-pin TSOP II 54-pin TSOP II (Pb-free) Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial 12 Document #: 38-05693 Rev. *B Page 7 of 9 [+] [+] Feedback CY7C1061BV33 Package Diagram 54-pin TSOP II (51-85160) 51-85160-** All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05693 Rev. *B Page 8 of 9 [+] [+] Feedback CY7C1061BV33 Document History Page Document Title: CY7C1061BV33 16-Mbit (1M x 16) Static RAM Document Number: 38-05693 REV. ** *A *B ECN NO. 283950 309453 492137 Issue Date See ECN See ECN See ECN Orig. of Change RKF RKF NXR New data sheet Final data sheet Removed 8 ns speed bin Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Updated the Ordering Information Table Description of Change Document #: 38-05693 Rev. *B Page 9 of 9 [+] [+] Feedback