CY7C1062G
CY7C1062GE
16-Mbit (512 K words × 32 bits) Static RAM
with Error-Correcting Code (ECC)
16-Mbit (512 K words × 32 bits) Static RAM with Error-Correcting Code (ECC)
Features
Functional Description
■
High speed
❐ tAA = 10 ns/15 ns
■
Embedded error-correcting code (ECC) for single-bit error
correction
■
Low active and standby current
❐ ICC = 90 mA typical
❐ ISB2 = 20 mA typical
■
Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V
■
1.0-V data retention
■
Automatic power-down when deselected
■
Transistor-transistor logic (TTL) compatible inputs and outputs
■
ERR pin to indicate 1-bit error detection and correction
■
Available in Pb-free 119-ball plastic ball grid array (PBGA)
package
CY7C1062G and CY7C1062GE are high-performance CMOS
fast static RAM devices with embedded ECC. Both have three
chip enables, giving easy memory expansion features. The
CY7C1062GE device includes an error indication pin that signals
the host processor in the case of a single bit error-detection and
correction event.
To write to the device, take Chip Enables (CE1, CE2, and CE3
LOW) and Write Enable (WE) input LOW. If Byte Enable A (BA)
is LOW, then data from I/O pins (I/O0 through I/O7) is written into
the location specified on the address pins (A0 through A18). If
Byte Enable B (BB) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A18). Likewise, BC and BD correspond with the I/O
pins I/O16 to I/O23 and I/O24 to I/O31, respectively.
To read from the device, take Chip Enables (CE1, CE2, and CE3
LOW) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If the first BA is LOW, then data from the
memory location specified by the address pins appear on I/O0 to
I/O7. If BB is LOW, then data from memory appears on I/O8 to
I/O15. Likewise, BC and BD correspond to the third and fourth
bytes. See Truth Table – CY7C1062G/CY7C1062GE on page 15
for a complete description of read and write modes.
The input and output pins (I/O0 through I/O31) are placed in a
high-impedance state when the device is deselected (CE1, CE2,
or CE3 HIGH), the outputs are disabled (OE HIGH), the byte
selects are disabled (BA-D HIGH), or during a write operation
(CE1, CE2 and CE3 LOW and WE LOW).
On the CY7C1062GE device, the detection and correction of a
single-bit error in the accessed location is indicated by the
assertion of the ERR output (ERR = High)[1].
CY7C1062G and CY7C1062GE devices are available in Pb-free
119-ball plastic ball grid array (PBGA) package.
For a complete list of related documentation, click here.
Note
1. This device does not support automatic write-back on error detection.
Cypress Semiconductor Corporation
Document Number: 001-81609 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 30, 2017
CY7C1062G
CY7C1062GE
Logic Block Diagram – CY7C1062G
ECC ENCODER
I/O0‐I/O7
I/O8‐I/O15
I/O16‐I/O23
I/O24‐I/O32
DATAIN DRIVERS
BD
BC
BB
BA
ECC DECODER
512K x 32
RAM ARRAY
SENSE AMPLIFIERS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
ROW DECODER
WE
A10
A11
A12
A13
A14
A15
A16
A17
A18
COLUMN DECODER
WE
BD BC BB BA
OE
CE3
CE2
CE1
Logic Block Diagram – CY7C1062GE
ECC ENCODER
I/O0‐I/O7
I/O8‐I/O15
I/O16‐I/O23
I/O24‐I/O32
DATAIN DRIVERS
BD
BC
BB
BA
ECC DECODER
512K x 32
RAM ARRAY
SENSE AMPLIFIERS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
ROW DECODER
WE
ERR
A10
A11
A12
A13
A14
A15
A16
A17
A18
COLUMN DECODER
WE
BD BC BB BA
Document Number: 001-81609 Rev. *G
OE
CE3
CE2
CE1
Page 2 of 20
CY7C1062G
CY7C1062GE
Contents
Pin Configurations ........................................................... 4
Product Portfolio .............................................................. 5
Maximum Ratings ............................................................. 6
Operating Range ............................................................... 6
DC Electrical Characteristics .......................................... 6
Capacitance ...................................................................... 7
Thermal Resistance .......................................................... 7
AC Test Loads and Waveforms ....................................... 7
Data Retention Characteristics ....................................... 8
Data Retention Waveform ................................................ 8
AC Switching Characteristics ......................................... 9
Switching Waveforms .................................................... 10
Truth Table – CY7C1062G/CY7C1062GE ...................... 15
ERR Output – CY7C1062GE .......................................... 15
Document Number: 001-81609 Rev. *G
Ordering Information ...................................................... 16
Ordering Code Definitions ......................................... 16
Package Diagrams .......................................................... 17
Acronyms ........................................................................ 18
Document Conventions ................................................. 18
Units of Measure ....................................................... 18
Document History Page ................................................. 19
Sales, Solutions, and Legal Information ...................... 20
Worldwide Sales and Design Support ....................... 20
Products .................................................................... 20
PSoC® Solutions ...................................................... 20
Cypress Developer Community ................................. 20
Technical Support ..................................................... 20
Page 3 of 20
CY7C1062G
CY7C1062GE
Pin Configurations
Figure 1. 119-ball PBGA Pinout (Top View) - CY7C1062G [2]
1
2
3
4
5
6
7
A
I/O16
A4
A3
A2
A1
A0
I/O0
B
C
D
E
F
G
H
J
K
L
M
N
P
I/O17
I/O18
I/O19
A18
Bc
VDD
A17
CE2
VSS
CE1
NC
VSS
A16
CE3
VSS
A15
Ba
VDD
I/O1
I/O2
I/O3
I/O20
VSS
VDD
VSS
VDD
VSS
I/O4
I/O21
VDD
VSS
VSS
VSS
VDD
I/O5
I/O22
VSS
VDD
VSS
VDD
VSS
I/O6
I/O23
NC
VDD
VSS
VSS
VDD
VSS
VSS
VSS
VDD
VDD
VSS
I/O7
NC
I/O24
I/O25
VDD
VSS
VSS
VDD
VSS
VSS
VSS
VDD
VDD
VSS
I/O8
I/O9
VDD
VSS
VSS
VSS
VDD
I/O10
I/O27
VSS
VDD
VSS
VDD
VSS
I/O11
I/O28
VDD
VSS
VSS
VSS
VDD
I/O12
I/O29
A14
Bd
NC
Bb
A13
I/O13
I/O30
A12
A11
WE
A10
A9
I/O14
I/O31
A8
A7
OE
A6
A5
I/O15
R
T
U
I/O26
Figure 2. 119-ball PBGA Pinout (Top View) - CY7C1062GE [2]
1
2
3
4
5
6
7
A
I/O16
A4
A3
A2
A1
A0
I/O0
B
C
D
E
F
G
H
J
K
L
M
N
P
I/O17
I/O18
I/O19
A18
Bc
VDD
A17
CE2
VSS
CE1
NC
VSS
A16
CE3
VSS
A15
Ba
VDD
I/O1
I/O2
I/O3
I/O20
VSS
VDD
VSS
VDD
VSS
I/O4
I/O21
VDD
VSS
VSS
VSS
VDD
I/O5
I/O22
VSS
VDD
VSS
VDD
VSS
I/O6
I/O23
ERR
VDD
VSS
VSS
VDD
VSS
VSS
VSS
VDD
VDD
VSS
I/O7
NC
I/O24
I/O25
VDD
VSS
VSS
VDD
VSS
VSS
VSS
VDD
VDD
VSS
I/O8
I/O9
I/O10
R
T
U
I/O26
VDD
VSS
VSS
VSS
VDD
I/O27
VSS
VDD
VSS
VDD
VSS
I/O11
I/O28
VDD
VSS
VSS
VSS
VDD
I/O12
I/O29
A14
Bd
NC
Bb
A13
I/O13
I/O30
A12
A11
WE
A10
A9
I/O14
I/O31
A8
A7
OE
A6
A5
I/O15
Note
2. NC pins are not connected internally to the die.
3. ERR is an Output pin.If not used, this pin should be left floating.
Document Number: 001-81609 Rev. *G
Page 4 of 20
CY7C1062G
CY7C1062GE
Product Portfolio
Power Dissipation
Product
CY7C1062G18
CY7C1062G30
Features and Options
(see Pin Configurations
on page 4)
Embedded ECC. No ERR
output pin
CY7C1062GE18 Embedded ECC. Optional
CY7C1062GE30 ERR output pin
Range
Industrial
VCC Range (V) Speed
(ns)
Operating ICC, (mA)
f = fmax
Typ [4]
Max
1.65 V–2.2 V
15
70
80
2.2 V–3.6 V
10
90
110
1.65 V–2.2 V
15
70
80
2.2 V–3.6 V
10
90
110
Standby, ISB2 (mA)
Typ [4]
Max
20
30
Notes
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V–2.2 V), VCC = 3 V
and (for VCC range of 2.2 V–3.6 V), TA = 25 °C.
Document Number: 001-81609 Rev. *G
Page 5 of 20
CY7C1062G
CY7C1062GE
DC input voltage [5] ............................. –0.5 V to VCC + 0.5 V
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Ambient temperature with
power applied .......................................... –55 C to +125 C
Supply voltage on VCC
relative to GND ................................... –0.5 V to VCC + 0.5 V
Current into outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(MIL-STD-883, Method 3015) ................................. > 2001 V
Latch-up current .................................................... > 140 mA
Operating Range
DC voltage applied to outputs
in High Z State [5] ................................ –0.5 V to VCC + 0.5 V
Grade
Ambient Temperature
VCC
Industrial
–40 C to +85 C
1.65 V to 2.2 V,
2.2 V to 3.6 V
DC Electrical Characteristics
Over the Operating Range of –40 C to 85 C
Parameter
VOH
VOL
VIH
VIL
Description
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
Input LOW
Voltage [5]
Test Conditions
10 ns / 15 ns
Min
Typ [6]
Max
1.65 V to 2.2 V VCC = Min, IOH = –0.1 mA
2.2 V to 2.7 V VCC = Min, IOH = –1.0 mA
1.4
–
–
2.0
–
–
2.7 V to 3.0 V
VCC = Min, IOH = –4.0 mA
2.2
3.0 V to 3.6 V
VCC = Min, IOH = –4.0 mA
2.4
–
–
–
–
0.2
–
–
0.4
–
–
0.4
1.65 V to 2.2 V VCC = Min, IOL = 0.1 mA
2.2 V to 2.7 V VCC = Min, IOL = 2 mA
2.7 V to 3.6 V
VCC = Min, IOL = 8 mA
1.65 V to 2.2 V –
1.4
–
VCC + 0.2
2.2 V to 2.7 V
–
2.0
–
VCC + 0.3
2.7 V to 3.6 V
–
2.0
–
VCC + 0.3
1.65 V to 2.2 V –
–0.2
–
0.4
2.2 V to 2.7 V
–
–0.3
–
0.6
2.7 V to 3.6 V
–
–0.3
–
0.8
IIX
Input Leakage Current
GND < VIN < VCC
–1.0
–
+1.0
IOZ
Output Leakage Current
GND < VOUT < VCC, Output disabled
–1.0
–
+1.0
ICC
Operating Supply Current
VCC = Max, IOUT = 0 mA, f = 100 MHz
CMOS levels
f = 66.7 MHz
–
90.0
110.0
–
70.0
80.0
[7],
ISB1
Automatic CE Power-down
Current – TTL Inputs
Max VCC, CE > VIH
VIN > VIH or VIN < VIL, f = fMAX
–
–
40.0
ISB2
Automatic CE Power-down
Current – CMOS Inputs
Max VCC, CE > VCC – 0.2 V[7],
VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0
–
20.0
30.0
Unit
V
A
mA
Notes
5. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V–2.2 V), VCC = 3 V
(for VCC range of 2.2 V–3.6 V), and TA = 25 °C.
7. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE1 , CE2 ,and CE3 LOW. When HIGH, CE indicates the CE1, CE2, or CE3
HIGH.
Document Number: 001-81609 Rev. *G
Page 6 of 20
CY7C1062G
CY7C1062GE
Capacitance
Parameter [8]
Description
CIN
Input Capacitance
COUT
I/O Capacitance
Test Conditions
119-ball PBGA Unit
TA = 25 C, f = 1 MHz, VCC = VCC(typ)
10
pF
Thermal Resistance
Parameter [8]
Description
JA
Thermal Resistance
(junction to ambient)
JC
Thermal Resistance
(junction to case)
Test Conditions
119-ball PBGA Unit
20.92
Still air, soldered on a 3 × 4.5 inch, four layer printed circuit
board
C/W
15.84
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms [9]
High-Z Characteristics:
VCC
50
Output
VTH
Z0 = 50
Output
30 pF*
* Including
JIG and
Scope
(b)
All Input Pulses
VHIGH
GND
R2
5 pF*
(a)
* Capacitive load consists
of all components of the
test environment
R1
90%
90%
10%
10%
Rise Time:
> 1 V/ns
(c)
Fall Time:
> 1 V/ns
Parameters
1.8 V
3.0 V
R1
1667
317
R2
1538
351
VTH
0.9
1.5
VHIGH
1.8
3.0
Unit
V
Notes
8. Tested initially and after any design or process changes that may affect these parameters.
9. Full-device AC operation assumes a 100-µs ramp time from 0 to VCC (min) and 100-µs wait time after VCC stabilizes to its operational value.
Document Number: 001-81609 Rev. *G
Page 7 of 20
CY7C1062G
CY7C1062GE
Data Retention Characteristics
Over the Operating Range of –40 C to 85 C
Parameter
VDR
Description
Conditions
VCC for Data Retention
Min
Max
Unit
1.0
–
V
–
30.0
mA
0.0
–
VCC > 2.2 V
10.0
–
VCC < 2.2 V
15.0
–
–
[10],
VCC = VDR, CE > VCC – 0.2 V
VIN > VCC – 0.2 V or VIN < 0.2 V
ICCDR
Data Retention Current
tCDR[11]
Chip Deselect to Data Retention
–
Time
tR[11, 12]
Operation Recovery Time
ns
Data Retention Waveform
Figure 4. Data Retention Waveform [10]
VCC
VCC(min)
tCDR
DATA RETENTION MODE
VDR = 1.0 V
VCC(min)
tR
CE
Notes
10. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE1 , CE2 ,and CE3 LOW. When HIGH, CE indicates the CE1, CE2, or CE3
HIGH.
11. Tested initially and after any design or process changes that may affect these parameters.
12. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 s or stable at VCC(min.) > 100 s.
Document Number: 001-81609 Rev. *G
Page 8 of 20
CY7C1062G
CY7C1062GE
AC Switching Characteristics
Over the Operating Range of –40 C to 85 C
Parameter [13]
Description
10 ns
15 ns
Min
Max
Min
Max
Unit
Read Cycle
tPOWER
VCC (stable) to the first access[14, 15]
100.0
–
100.0
–
tRC
Read cycle time
10.0
–
15.0
–
tAA
Address to data / ERR valid
–
10.0
–
15.0
tOHA
Data / ERR hold from address change
3.0
–
3.0
–
tACE
CE LOW to data / ERR valid [16]
–
10.0
–
15.0
tDOE
OE LOW to data / ERR valid
–
5.0
–
8.0
0.0
–
1.0
–
tLZOE
OE LOW to low Z
[17, 18]
[17, 18]
tHZOE
OE HIGH to high Z
tLZCE
CE LOW to low Z [16, 17, 18]
tHZCE
CE HIGH to high Z [16, 17, 18]
tPU
CE LOW to power-up
[15, 16]
tPD
CE HIGH to power-down
tDBE
Byte enable to data valid
tLZBE
tHZBE
Write Cycle
tWC
[15, 16]
–
5.0
–
8.0
3.0
–
3.0
–
–
5.0
–
8.0
0.0
–
0.0
–
–
10.0
–
15.0
–
5.0
–
8.0
Byte enable to low Z
0.0
–
1.0
–
Byte disable to high Z
–
6.0
–
8.0
10.0
–
15.0
–
7.0
–
12.0
–
7.0
–
12.0
–
s
ns
[19, 20]
Write cycle time
[16]
tSCE
CE LOW to write end
tAW
Address setup to write end
tHA
Address hold from write end
0.0
–
0.0
–
tSA
Address setup to write start
0.0
–
0.0
–
tPWE
WE pulse width
7.0
–
12.0
–
tSD
Data setup to write end
5.0
–
8.0
–
tHD
Data hold from write end
0.0
–
0.0
–
tLZWE
WE HIGH to low Z [17, 18]
3.0
–
3.0
–
tHZWE
WE LOW to high Z
[17, 18]
–
5.0
–
8.0
tBW
Byte Enable to write end
7.0
–
12.0
–
ns
Notes
13. Test conditions assume signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse levels
of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3V). Test conditions for the read cycle use output loading shown in part (a) of Figure 3 on page 7, unless specified otherwise.
14. tPOWER gives minimum amount of time that the power supply is at stable Vcc until first memory access is performed.
15. These parameters are guaranteed by design and are not tested.
16. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE1 , CE2 ,and CE3 LOW. When HIGH, CE indicates the CE1, CE2, or CE3 HIGH.
17. tHZOE, tHZCE, tHZWE, tHZBE, tLZOE, tLZCE, tLZWE, and tLZBE are specified with a load capacitance of 5 pF as in (b) of Figure 3 on page 7. Transition is measured 200 mV from steady
state voltage.
18. Tested initially and after any design or process changes that may affect these parameters.
19. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any
of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
20. The minimum write pulse width for Write Cycle No. 2 (WE Controlled, OE Low) should be sum of tHZWE and tSD.
Document Number: 001-81609 Rev. *G
Page 9 of 20
CY7C1062G
CY7C1062GE
Switching Waveforms
Figure 5. Read Cycle No. 1 of CY7C1062G (Address Transition Controlled) [21, 22]
tRC
ADDRESS
tAA
tOHA
DATA I/O
PREVIOUS DATAOUT
VALID
DATAOUT VALID
Figure 6. Read Cycle No. 1 of CY7C1062GE (Address Transition Controlled) [21, 22]
tRC
ADDRESS
tAA
tOHA
DATA I/O
PREVIOUS DATAOUT
VALID
DATAOUT VALID
tAA
tOHA
ERR
PREVIOUS ERR VALID
ERR VALID
Notes
21. The device is continuously selected, OE, CE, BA, BB, BC, BD = VIL.
22. WE is HIGH for read cycle.
Document Number: 001-81609 Rev. *G
Page 10 of 20
CY7C1062G
CY7C1062GE
Switching Waveforms (continued)
Figure 7. Read Cycle No. 2 (OE Controlled) [23, 24, 25]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
tLZOE
BA-D
tDBE
tLZBE
DATA I/O
HIGH IMPEDANCE
tHZBE
DATAOUT VALID
HIGH
IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
tPU
ISB
Notes
23. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE1 , CE2 ,and CE3 LOW. When HIGH, CE indicates the CE1, CE2, or CE3
HIGH.
24. WE is HIGH for read cycle.
25. Address valid before or similar to CE transition LOW.
Document Number: 001-81609 Rev. *G
Page 11 of 20
CY7C1062G
CY7C1062GE
Switching Waveforms (continued)
Figure 8. Write Cycle No. 1 (CE Controlled) [26, 27, 28]
tWC
ADDRESS
tSA
tSCE
CE
tAW
tHA
tPWE
WE
tBW
BA-D
OE
tHZOE
DATA I/O
Note 29
tSD
tHD
DATAIN VALID
Notes
26. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE1 , CE2 ,and CE3 LOW. When HIGH, CE indicates the CE1, CE2, or CE3
HIGH.
27. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any
of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
28. Data I/O is high impedance if CE or OE or BA, BB, BC, BD = VIH.
29. During this period I/O are in output state. Do not apply input signals.
Document Number: 001-81609 Rev. *G
Page 12 of 20
CY7C1062G
CY7C1062GE
Switching Waveforms (continued)
Figure 9. Write Cycle No. 2 (WE Controlled, OE Low) [30, 31, 32, 33]
tWC
ADDRESS
tSCE
CE
tBW
BA-D
tSA
tAW
tHA
tPWE
WE
tHZWE
DATA I/O
Note 34
tSD
tLZWE
tHD
DATAIN VALID
Notes
30. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE1 , CE2 ,and CE3 LOW. When HIGH, CE indicates the CE1, CE2, or CE3
HIGH.
31. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any
of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
32. Data I/O is high impedance if OE or BA, BB, BC, BD = VIH.
33. The minimum write cycle pulse width should be equal to sum of tHZWE and tSD.
34. During this period I/O are in output state. Do not apply input signals.
Document Number: 001-81609 Rev. *G
Page 13 of 20
CY7C1062G
CY7C1062GE
Switching Waveforms (continued)
Figure 10. Write Cycle No. 3 (BA, BB, BC, BD Controlled) [35, 36, 37]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tBW
BA-D
tPWE
WE
tHZWE
DATA I/O
Note 38
tSD
tHD
tLZWE
DATAIN VALID
Notes
35. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE1 , CE2 ,and CE3 LOW. When HIGH, CE indicates the CE1, CE2, or CE3
HIGH.
36. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any
of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
37. Data I/O is high impedance if OE or BA, BB, BC, BD = VIH.
38. During this period I/O are in output state. Do not apply input signals.
Document Number: 001-81609 Rev. *G
Page 14 of 20
CY7C1062G
CY7C1062GE
Truth Table – CY7C1062G/CY7C1062GE
CE1 CE2 CE3
OE
WE
BA
BB
Bc
BD
I/O0–I/O7
X[39]
X[39]
X[39]
X[39]
X[39]
X[39]
X[39]
X[39]
Mode
Power
High Z
High Z
High Z
X[39]
H
X[39]
X[39]
X[39]
X[39]
X[39]
X[39]
X[39]
High Z
power-down
(ISB)
High Z
High Z
X[39]
X[39]
H
X[39]
X[39]
X[39]
X[39]
X[39]
X[39]
High Z
High Z
power-down
(ISB)
High Z
High Z
High Z
High Z
power-down
(ISB)
L
L
L
L
H
L
L
L
L
Data out
Data out
Data out
Data out
Read all bits
(ICC)
L
L
L
L
H
L
H
H
H
Data out
High Z
High Z
High Z
Read byte A
bits only
(ICC)
L
L
L
L
H
H
L
H
H
High Z
Data out
High Z
High Z
Read byte B
bits only
(ICC)
L
L
L
L
H
H
H
L
H
High Z
High Z
Data out
High Z
Read byte C
bits only
(ICC)
L
L
L
L
H
H
H
H
L
High Z
High Z
High Z
Data out
Read Byte D
bits only
(ICC)
L
L
L
X[39]
L
L
L
L
L
Data in
Data in
Data in
Data in
Write all bits
(ICC)
L
L
L
X[39]
L
L
H
H
H
Data in
High Z
High Z
High Z
Write byte A
bits only
(ICC)
L
L
L
X[39]
L
H
L
H
H
High Z
Data in
High Z
High Z
Write byte B
bits only
(ICC)
L
L
L
X[39]
L
H
H
L
H
High Z
High Z
Data in
High Z
Write byte C
bits only
(ICC)
L
L
L
X[39]
L
H
H
H
L
High Z
High Z
High Z
Data in
Write byte D
bits only
(ICC)
L
L
L
H
H
High Z
High Z
High Z
High Z
Selected,
outputs
disabled
(ICC)
L
L
L
High Z
High Z
High Z
High Z
Selected,
outputs
disabled
(ICC)
H
X[39] X[39]
X[39] X[39] X[39] X[39]
H
H
H
H
I/O8–I/O15 I/O16–I/O23 I/O24–I/O31
ERR Output – CY7C1062GE
Output [40]
0
1
High Z
Mode
Read Operation, no single-bit error in the stored data.
Read Operation, single bit error detected and corrected.
Device deselected or Outputs disabled or Write Operation.
Notes
39. The input voltage levels on these pins should be either at VIH or VIL.
40. ERR is an Output pin. If not used, this pin should be left floating.
Document Number: 001-81609 Rev. *G
Page 15 of 20
CY7C1062G
CY7C1062GE
Ordering Information
Speed
(ns)
10
Voltage
Range
Ordering Code
Package
Diagram
2.2 V–3.6 V CY7C1062G30-10BGXI
51-85115
Package Type (Pb-free)
ERR Ball
119-ball PBGA
No
CY7C1062G30-10BGXIT
119-ball PBGA, Tape & Reel
No
CY7C1062GE30-10BGXI
119-ball PBGA
Yes
CY7C1062GE30-10BGXIT
119-ball PBGA, Tape & Reel
Yes
Operating
Range
Industrial
Ordering Code Definitions
CY 7 C 1 06 2
G
E
30 - 10 BG
X
I
X
X: T = Tape & Reel; Blank = Bulk
Temperature Range: I = Industrial
Pb-free
Package Type: BG = 119-ball PBGA
Speed: 10 ns
Voltage Range: 30 = 2.2 V–3.6 V
ERR output Single bit error indication
Process Technology: 65 nm
Data width: 2 = × 32-bits
Density: 06 = 16-Mbit
Family Code: 1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-81609 Rev. *G
Page 16 of 20
CY7C1062G
CY7C1062GE
Package Diagrams
Figure 11. 119-pin PBGA (14 × 22 × 2.4 mm) BG119 Package Outline, 51-85115
51-85115 *D
Document Number: 001-81609 Rev. *G
Page 17 of 20
CY7C1062G
CY7C1062GE
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CE
Chip Enable
CMOS
Complementary Metal Oxide Semiconductor
°C
degree Celsius
I/O
Input/Output
MHz
megahertz
OE
Output Enable
A
microampere
PBGA
Plastic Ball Grid Array
s
microsecond
SRAM
Static Random Access Memory
mA
milliampere
TTL
Transistor-Transistor Logic
mm
millimeter
WE
Write Enable
ns
nanosecond
ohm
%
percent
pF
picofarad
V
volt
W
watt
Document Number: 001-81609 Rev. *G
Symbol
Unit of Measure
Page 18 of 20
CY7C1062G
CY7C1062GE
Document History Page
Document Title: CY7C1062G/CY7C1062GE, 16-Mbit (512 K words × 32 bits) Static RAM with Error-Correcting Code (ECC)
Document Number: 001-81609
Rev.
ECN No.
Orig. of
Change
Submission
Date
*E
4800546
NILE
07/31/2015
Changed status from Preliminary to Final.
*F
5434962
NILE
09/13/2016
Updated DC Electrical Characteristics:
Enhanced VOH for voltage range 3.0 V to 3.6 V from 2.2 V to 2.4 V.
Updated Footnote 5.
Updated part numbers in Ordering Information.
Added Tape & Reel ordering codes.
Updated copyright notice and Sales, Solutions, and Legal Information.
*G
5975045
AESATP12
11/30/2017
Updated logo and copyright.
Document Number: 001-81609 Rev. *G
Description of Change
Page 19 of 20
CY7C1062G
CY7C1062GE
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
ARM® Cortex® Microcontrollers
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cypress.com/arm
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Interface
cypress.com/clocks
cypress.com/interface
Internet of Things
Memory
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Cypress Developer Community
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
Touch Sensing
cypress.com/touch
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2012-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
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provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
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TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
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are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
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damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-81609 Rev. *G
Revised November 30, 2017
Page 20 of 20
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