CY7C1069GN
16-Mbit (2M × 8) Static RAM
16-Mbit (2M × 8) Static RAM
Features
Functional Description
■
High speed
❐ tAA = 10 ns
The CY7C1069GN is a high performance CMOS Static RAM
organized as 2,097,152 words by 8 bits.
■
Low active power
❐ ICC = 90 mA at 100 MHz
■
Low complementary metal oxide semiconductor (CMOS)
standby power
❐ ISB2 = 20 mA (typical)
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location specified
on the address pins (A0 through A20).
■
Operating voltages of 2.2 V to 3.6 V
■
1.0 V data retention
■
Automatic power-down when deselected
■
Transistor-transistor logic (TTL) compatible inputs and outputs
■
Easy memory expansion with CE1 and CE2 features
■
Available in Pb-free 54-pin thin small outline package (TSOP)
Type II and 48-ball very fine-pitch ball grid array (VFBGA)
packages.
To read from the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. Under these conditions, the contents of the
memory location specified by the address pins will appear on the
I/O pins. See Truth Table on page 10 for a complete description
of Read and Write modes.
The input and output pins (I/O0 through I/O7) are placed in a high
impedance state when the device is deselected (CE1 HIGH or
CE2 LOW), the outputs are disabled (OE HIGH), or during a write
operation (CE1 LOW, CE2 HIGH, and WE LOW).
The CY7C1069GN is available in a 54-pin TSOP II and a 48-ball
very fine-pitch ball grid array (VFBGA) package.
Logic Block Diagram
2Mx8
ARRAY
SENSE AMPS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
ROW DECODER
INPUT BUFFER
I/O0 – I/O7
WE
CE2
OE
COLUMN
DECODER
A10
A11
A 12
A 13
A 14
A15
A16
A17
A18
A19
A20
CE1
Cypress Semiconductor Corporation
Document Number: 002-00046 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 19, 2017
CY7C1069GN
Contents
Selection Guide ................................................................ 3
Pin Configurations ........................................................... 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
DC Electrical Characteristics .......................................... 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
AC Switching Characteristics ......................................... 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 10
Document Number: 002-00046 Rev. *B
Ordering Information ...................................................... 10
Ordering Code Definitions ......................................... 10
Package Diagrams .......................................................... 11
Acronyms ........................................................................ 13
Document Conventions ................................................. 13
Units of Measure ....................................................... 13
Document History Page ................................................. 14
Sales, Solutions, and Legal Information ...................... 15
Worldwide Sales and Design Support ....................... 15
Products .................................................................... 15
PSoC® Solutions ...................................................... 15
Cypress Developer Community ................................. 15
Technical Support ..................................................... 15
Page 2 of 15
CY7C1069GN
Selection Guide
Description
-10
Unit
Maximum access time
10
ns
Maximum operating current
110
mA
Maximum CMOS standby current
30
mA
Pin Configurations
Figure 1. 54-pin TSOP II pinout (Top View) [1]
NC
VCC
NC
I/O6
VSS
I/O7
A4
A3
A2
A1
A0
NC
CE1
VCC
WE
CE2
A19
A18
A17
A16
A15
I/O0
VCC
I/O1
NC
VSS
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
45
44
NC
VSS
NC
I/O5
VCC
I/O4
A5
A6
A7
A8
A9
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
NC
OE
VSS
NC
A20
A10
A11
A12
A13
A14
I/O3
VSS
I/O2
NC
VCC
NC
54
53
52
51
50
49
48
47
46
Figure 2. 48-ball VFBGA pinout (Top View) [1]
1
2
3
4
5
6
NC
OE
A0
A1
A2
CE2
A
NC
NC
A3
A4
CE1
NC
B
I/O0
NC
A5
A6
NC
I/O4
C
VSS
I/O1
A17
A7
I/O5
VCC
D
VCC
I/O2
A18
A16
I/O6
VSS
E
I/O3
NC
A14
A15
NC
I/O7
F
NC
NC
A12
A13
WE
NC
G
A19
A8
A9
A10
A11
A20
H
Note
1. NC pins are not connected on the die.
Document Number: 002-00046 Rev. *B
Page 3 of 15
CY7C1069GN
DC input voltage [2] ............................. –0.5 V to VCC + 0.5 V
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Ambient temperature
with power applied ................................... –55 C to +125 C
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(MIL-STD-883, method 3015) ................................. > 2001 V
Latch-up current .................................................... > 140 mA
Operating Range
Supply voltage
on VCC relative to GND [2] .................. –0.5 V to VCC + 0.5 V
DC voltage applied to outputs
in High Z state [2] ................................ –0.5 V to VCC + 0.5 V
Range
Ambient Temperature
VCC
Industrial
–40 C to +85 C
3.3 V 0.3 V
DC Electrical Characteristics
Over the Operating Range
Parameter
VOH
VOL
VIH
VIL
Description
Output HIGH
voltage
Output LOW
voltage
Input HIGH
voltage
Input LOW
voltage [2]
Test Conditions
-10ns
Min
Typ [3]
Max
2.2 V to 2.7 V
Min VCC, IOH = –1.0 mA
2.0
–
–
2.7 V to 3.0 V
Min VCC, IOH = –4.0 mA
2.2
–
–
3.0 V to 3.6 V
Min VCC, IOH = –4.0 mA
2.4
–
–
2.2 V to 2.7 V
Min VCC, IOL = 2.0 mA
–
–
0.4
2.7 V to 3.6 V
Min VCC, IOL = 8.0 mA
–
–
0.4
2.2 V to 2.7 V
–
2.0
–
VCC + 0.3
2.7 V to 3.6 V
–
2.0
–
VCC + 0.3
2.2 V to 2.7 V
–
–0.3
–
0.6
2.7 V to 3.6 V
–
–0.3
–
0.8
Unit
V
V
V
V
IIX
Input leakage current
GND < VIN < VCC
–1
+1
A
IOZ
Output leakage current
GND < VOUT < VCC, Output disabled
–1
+1
A
ICC
VCC operating supply current
VCC = Max, f = fMAX = 1/tRC,
IOUT = 0 mA, CMOS levels
–
90
110
mA
ISB1
Automatic CE power-down
current – TTL inputs
Max VCC, CE1 > VIH, CE2 < VIL,
VIN > VIH or VIN < VIL, f = fMAX
–
–
40
mA
ISB2
Automatic CE power-down
current – CMOS inputs
Max VCC,
CE1 > VCC – 0.3 V, CE2 < 0.3 V,
VIN > VCC – 0.3 V or VIN < 0.3 V, f = 0
–
20
30
mA
Notes
2. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3 V (for VCC range of 2.2 V–3.6 V)
Document Number: 002-00046 Rev. *B
Page 4 of 15
CY7C1069GN
Capacitance
Parameter [4]
Description
CIN
Input capacitance
COUT
IO capacitance
Test Conditions
TA = 25 C, f = 1 MHz, VCC = 3.3 V
TSOP II
VFBGA
Unit
10
10
pF
10
10
pF
TSOP II
VFBGA
Unit
93.63
31.50
C/W
21.58
15.75
C/W
Thermal Resistance
Parameter [4]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
Still air, soldered on a 3 × 4.5 inch, four
layer printed circuit board
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms [5]
High Z characteristics
3.3 V
50
VTH = 1.5 V
OUTPUT
Z0 = 50
R1 317
OUTPUT
30 pF*
5 pF*
(a)
* Capacitive load consists
of all components of the
test environment
3.0 V
GND
Rise Time > 1 V/ns
ALL INPUT PULSES
90%
90%
10%
10%
(c)
R2
351
INCLUDING
JIG AND
SCOPE
(b)
Fall Time:
> 1 V/ns
Notes
4. Tested initially and after any design or process changes that may affect these parameters.
5. Full device AC operation assumes a 100-μs ramp time from 0 to VCC(min) and 100-μs wait time after VCC stabilization.
Document Number: 002-00046 Rev. *B
Page 5 of 15
CY7C1069GN
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
Min
Max
Unit
1.0
–
V
30
mA
VDR
VCC for data retention
–
ICCDR
Data retention current
VCC = VDR, CE1 > VCC – 0.2 V, CE2 < 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
–
tCDR [6]
Chip deselect to data retention
time
–
0
–
ns
tR [7]
Operation recovery time
–
10
–
ns
Data Retention Waveform
Figure 4. Data Retention Waveform
DATA RETENTION MODE
VCC
3.0 V
VDR > 1 V
tCDR
3.0 V
tR
CE
Notes
6. Tested initially and after any design or process changes that may affect these parameters.
7. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 μs or stable at VCC(min.) > 100 μs.
Document Number: 002-00046 Rev. *B
Page 6 of 15
CY7C1069GN
AC Switching Characteristics
Over the Operating Range
Parameter [8]
Description
-10
Min
Max
Unit
Read Cycle
tpower
VCC(typical) to the first access [9, 10]
100
–
s
tRC
Read cycle time
10
–
ns
tAA
Address to data valid
–
10
ns
tOHA
Data hold from address change
3
–
ns
tACE
CE1 LOW/CE2 HIGH to data valid
–
10
ns
tDOE
OE LOW to data valid
–
5
ns
0
–
ns
–
5
ns
3
–
ns
[11, 12, 13]
–
5
ns
[10]
0
–
ns
–
10
ns
tLZOE
OE LOW to low Z
[11, 12, 13]
[11, 12, 13]
tHZOE
OE HIGH to high Z
tLZCE
CE1 LOW/CE2 HIGH to low Z [11, 12, 13]
tHZCE
tPU
tPD
CE1 HIGH/CE2 LOW to high Z
CE1 LOW/CE2 HIGH to power-up
CE1 HIGH/CE2 LOW to power-down
[10]
Write Cycle [14, 15]
tWC
Write cycle time
10
–
ns
tSCE
CE1 LOW/CE2 HIGH to write end
7
–
ns
tAW
Address setup to write end
7
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
tPWE
WE pulse width
7
–
ns
tSD
Data setup to write end
5
–
ns
tHD
Data hold from write end
0
–
ns
WE HIGH to low Z
[11, 12, 13]
3
–
ns
WE LOW to high Z
[11, 12, 13]
–
5
ns
tLZWE
tHZWE
Notes
8. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, and input pulse levels of 0 to 3.0 V. Test conditions for the read cycle use
output loading shown in (a) of Figure 3 on page 5, unless specified otherwise.
9. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed.
10. These parameters are guaranteed by design and are not tested.
11. tHZOE, tHZCE, tHZWE, tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in (b) of Figure 3 on page 5. Transition is measured 200 mV from steady state voltage.
12. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
These parameters are guaranteed by design and are not tested.
13. Tested initially and after any design or process changes that may affect these parameters.
14. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. CE1 and WE are LOW along with CE2 HIGH to initiate a write, and the
transition of any of these signals can terminate. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
15. The minimum write cycle time for Write Cycle No. 2 (WE Controlled, OE LOW) is the sum of tHZWE and tSD.
Document Number: 002-00046 Rev. *B
Page 7 of 15
CY7C1069GN
Switching Waveforms
Figure 5. Read Cycle No. 1 (Address Transition Controlled) [16, 17]
tRC
RC
ADDRESS
tOHA
DATA I/O
tAA
PREVIOUS DATA VALID
DATA OUT VALID
Figure 6. Read Cycle No. 2 (OE Controlled) [17, 18]
ADDRESS
tRC
CE1
CE2
tACE
OE
tHZOE
tDOE
tHZCE
tLZOE
DATA I/O
HIGH IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
DATA OUT VALID
tPD
tPU
50%
50%
ICC
ISB
Notes
16. The device is continuously selected. CE1 = VIL, and CE2 = VIH.
17. WE is HIGH for read cycle.
18. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH.
Document Number: 002-00046 Rev. *B
Page 8 of 15
CY7C1069GN
Switching Waveforms (continued)
Figure 7. Write Cycle No. 1 (CE Controlled) [19, 20, 21, 22]
tWC
ADDRESS
tSA
CE
tSCE
tAW
tHA
tPWE
WE
tSD
tHD
DATA IN VALID
DATA IO
Figure 8. Write Cycle No. 2 (WE Controlled, OE LOW) [19, 20, 21, 22]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tHZWE
DATA I/O
tSD
tHD
DATA IN VALID
tLZWE
Notes
19. CE is a shorthand combination of both CE1 and CE2 combined. It is active LOW.
20. Data I/O is high impedance if OE = VIH.
21. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
22. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any
of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
Document Number: 002-00046 Rev. *B
Page 9 of 15
CY7C1069GN
Truth Table
CE1 CE2
OE
WE
I/O0–I/O7
Mode
Power
H
X
X
X
High Z
Power-down
Standby (ISB)
X
L
X
X
High Z
Power-down
Standby (ISB)
L
H
L
H
Data out
Read all bits
Active (ICC)
L
H
X
L
Data in
Write all bits
Active (ICC)
L
H
H
H
High Z
Selected, outputs disabled
Active (ICC)
Ordering Information
Speed
(ns)
10
Ordering Code
Package
Diagram
Package Type
CY7C1069GN30-10ZSXI
51-85160 54-pin TSOP II (Pb-free)
CY7C1069GN30-10ZSXIT
51-85160 54-pin TSOP II (Pb-free), Tape and Reel
CY7C1069GN30-10BVXI
51-85150 48-ball VFBGA (Pb-free)
CY7C1069GN30-10BVXIT
51-85150 48-ball VFBGA (Pb-free), Tape and Reel
Operating
Range
Industrial
Ordering Code Definitions
CY 7 C 1 06 9 GN 30 - 10 XX X
I
X
X = blank or T
blank = Bulk; T = Tape and Reel
Temperature Range:
I = Industrial
Pb-free
Package Type: XX = ZS or BV
ZS = 54-pin TSOP II
BV = 48-ball VFBGA
Speed: 10 ns
Voltage Range: 30 = 2.2 V to 3.6 V
Process Technology: GN = 65 nm
Data Width: 9 = × 8-bits
Density: 06 = 16-Mbit density
Family Code: 1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 002-00046 Rev. *B
Page 10 of 15
CY7C1069GN
Package Diagrams
Figure 9. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm) Z54-II Package Outline, 51-85160
51-85160 *E
Document Number: 002-00046 Rev. *B
Page 11 of 15
CY7C1069GN
Package Diagrams (continued)
Figure 10. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150
51-85150 *H
Document Number: 002-00046 Rev. *B
Page 12 of 15
CY7C1069GN
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CE
chip enable
CMOS
complementary metal oxide semiconductor
°C
degree Celsius
I/O
input/output
MHz
megahertz
OE
output enable
A
microampere
SRAM
static random access memory
s
microsecond
VFBGA
very fine-pitch ball grid array
mA
milliampere
TSOP
thin small outline package
ns
nanosecond
TTL
transistor-transistor logic
ohm
WE
write enable
%
percent
pF
picofarad
V
volt
W
watt
Document Number: 002-00046 Rev. *B
Symbol
Unit of Measure
Page 13 of 15
CY7C1069GN
Document History Page
Document Title: CY7C1069GN, 16-Mbit (2M × 8) Static RAM
Document Number: 002-00046
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
4948206
NILE
10/13/2015
New data sheet
*A
5437942
NILE
09/15/2016
Updated DC Electrical Characteristics:
Removed Operating Range “2.7 V to 3.6 V” and all values corresponding to
VOH parameter.
Included Operating Ranges “2.7 V to 3.0 V” and “3.0 V to 3.6 V” and all values
corresponding to VOH parameter.
Updated Ordering Information:
Updated part numbers.
Updated Ordering Code Definitions.
Updated to new template.
Completing Sunset Review.
*B
5999403
AESATMP8
12/19/2017
Updated logo and Copyright.
Document Number: 002-00046 Rev. *B
Description of Change
Page 14 of 15
CY7C1069GN
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2015-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
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(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
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to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
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Document Number: 002-00046 Rev. *B
Revised December 19, 2017
Page 15 of 15
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