CY7C1089DV33

CY7C1089DV33 64-Mbit (8M x 8) Static RAM Features ■ Functional Description The CY7C1089DV33 is a high-performance CMOS static RAM organized as 8,388,608 words by 8 bits. To write to the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A22). To read from the device, take Chip Enables (CE1 LOW and CE2 HIGH) LOW and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. See Truth Table on page 9 for a complete description of Read and Write modes. The input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE1 LOW or CE2 HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH and WE LOW). High speed ❐ tAA = 12 ns Low active power ❐ ICC = 300 mA Low complementary metal oxide semiconductor (CMOS) standby power ❐ ISB2 = 100 mA Operating voltages of 3.3 ± 0.3 V 2.0-V data retention Automatic power-down when deselected Transistor-transistor logic (TTL)-compatible inputs and outputs Easy memory expansion with CE1 and CE2 features Available in Pb-free 48-ball fine ball grid array (FBGA) package ■ ■ ■ ■ ■ ■ ■ ■ Logic Block Diagram INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER SENSE AMPS 8M x 8 ARRAY I/O0 – I/O7 COLUMN DECODER WE OE CE2 CE1 Selection Guide Description Maximum access time Maximum operating current Maximum CMOS standby current –12 12 300 100 Unit ns mA mA A10 A11 A 12 A 13 A 14 A15 A16 A17 A18 A19 A20 A21 A22 Cypress Semiconductor Corporation Document Number: 001-53993 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 21, 2011 [+] Feedback CY7C1089DV33 Contents Pin Configuration.............................................................. Maximum Ratings ............................................................. Operating Range ............................................................... DC Electrical Characteristics........................................... Capacitance....................................................................... Thermal Resistance .......................................................... Data Retention Characteristics........................................ AC Switching Characteristics.......................................... Switching Waveforms....................................................... Truth Table ........................................................................ Ordering Information ........................................................ Ordering Code Definition ............................................. 3 4 4 4 4 4 5 6 7 9 9 9 Package Diagram............................................................ Acronyms ........................................................................ Document Conventions ................................................. Units of Measure ....................................................... Document History Page ................................................. Sales, Solutions, and Legal Information ...................... Worldwide Sales and Design Support ....................... Products .................................................................... PSoC Solutions ......................................................... 10 10 10 10 11 11 11 11 11 Document Number: 001-53993 Rev. *B Page 2 of 11 [+] Feedback CY7C1089DV33 Pin Configuration Figure 1. 48-Ball FBGA (Top View) [1] 1 A22 NC I/O0 VSS VCC I/O3 NC A19 2 OE NC NC I/O1 I/O2 NC A21 A8 3 A0 A3 A5 A17 A18 A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE1 NC I/O5 I/O6 NC WE A11 6 CE2 NC I/O4 VCC VSS I/O7 NC A20 A B C D E F G H Note 1. NC pins are not connected to the die. Document Number: 001-53993 Rev. *B Page 3 of 11 [+] Feedback CY7C1089DV33 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –65 °C to +150 °C Ambient temperature with power applied ........................................... –55 °C to +125 °C Supply voltage on VCC relative to GND[2] .....–0.5 V to +4.6 V DC voltage applied to outputs in high-Z state[2]................................... –0.5 V to VCC + 0.5 V DC input voltage[2] ............................... –0.5 V to VCC + 0.5 V Current into outputs (LOW) ......................................... 20 mA Static discharge voltage............................................ >2001 V (MIL-STD-883, Method 3015) Latch up current ...................................................... >140 mA Operating Range Range Industrial Ambient Temperature –40 °C to +85 °C VCC 3.3V ± 0.3V DC Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage[2] GND < VIN < VCC GND < VOUT < VCC, Output disabled Input leakage current Output leakage current Test Conditions VCC = Min, IOH = –4.0 mA VCC = Min, IOL = 8.0 mA –12 Min 2.4 – 2.0 –0.3 –1 –1 – – – Max – 0.4 VCC + 0.3 0.8 +1 +1 300 120 100 Unit V V V V μA μA mA mA mA VCC operating supply current VCC = Max, f = fMAX = 1/tRC, IOUT = 0 mA CMOS levels Automatic CE power-down Max VCC, CE1 > VIH, CE2 < VIL, VIN > VIH or VIN < VIL, f = fMAX current — TTL inputs Automatic CE power-down current —CMOS inputs Max VCC, CE1 > VCC – 0.3V, CE2 < 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter CIN COUT Description Input capacitance I/O capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = 3.3 V FBGA 32 40 Unit pF pF Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter ΘJA ΘJC Description Thermal resistance (junction to ambient) Thermal resistance (junction to case) Test Conditions Still air, soldered on a 3 × 4.5 inch, four layer printed circuit board FBGA 55 23.04 Unit °C/W °C/W Note 2. VIL (min) = –2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns. Document Number: 001-53993 Rev. *B Page 4 of 11 [+] Feedback CY7C1089DV33 Figure 2. AC Test Loads and Waveforms[3] 50Ω OUTPUT Z0 = 50Ω 30 pF* ALL INPUT PULSES 90% 10% VTH = 1.5V High-Z characteristics 3.3V OUTPUT 5 pF* R1 317Ω (a) * Capacitive load consists of all components of the test environment R2 351Ω 3.0V GND Rise Time > 1 V/ns 90% 10% INCLUDING JIG AND SCOPE (b) (c) Fall Time: > 1 V/ns Data Retention Characteristics Over the Operating Range Parameter VDR ICCDR tCDR[4] tR[ 5] Description VCC for data retention Data retention current Chip deselect to data retention time Operation recovery time Figure 3. Data Retention Waveform DATA RETENTION MODE VCC CE1 CE2 3.0V tCDR VDR > 2V 3.0V tR Conditions VCC = 2V , CE1 > VCC – 0.2V, CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V Min 2 – 0 12 Typ – – – – Max – 100 – – Unit V mA ns ns Notes 3. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). 100 μs (tpower) after reaching the minimum operating VDD, normal SRAM operation begins including reduction in VDD to the data retention (VCCDR, 2.0V) voltage. 4. Tested initially and after any design or process changes that may affect these parameters. 5. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 μs or stable at VCC(min.) > 50 μs. Document Number: 001-53993 Rev. *B Page 5 of 11 [+] Feedback CY7C1089DV33 AC Switching Characteristics Over the Operating Range [6] Parameter Read Cycle tpower tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle [10, 11] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Write cycle time CE1 LOW and CE2 HIGH to write end Address setup to write end Address hold from write end Address setup to write start WE pulse width Data setup to write end Data hold from write end WE HIGH to WE LOW to low-Z[8] high-Z[8] 12 9 9 0 0 9 7 0 3 – – – – – – – – – – 7 ns ns ns ns ns ns ns ns ns ns VCC(typical) to the first access[7] Read cycle time Address to data valid Data hold from address change CE1 LOW and CE2 HIGH to data valid OE LOW to data valid OE LOW to low-Z OE HIGH to high-Z [8] Description –12 Min 100 12 – 3 – – 1 – 3 – [9] [9] Max – – 12 – 12 7 – 7 – 7 – 12 Unit μs ns ns ns ns ns ns ns ns ns ns ns CE1 LOW and CE2 HIGH to low-Z [8] CE1 HIGH and CE2 LOW to high-Z [8] CE1 LOW and CE2 HIGH to power-up 0 – CE1 HIGH and CE2 LOW to power-down Notes 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. Test conditions for the read cycle use output loading shown in part a) of AC Test Loads and Waveforms[3], unless specified otherwise. 7. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed. 8. tHZOE, tHZCE, tHZWE, tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms[3]. 9. These parameters are guaranteed by design and are not tested. 10. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. Chip enables must be active and WE must be LOW to initiate a write, and the transition of any of these signals can terminate. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 11. The minimum write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 001-53993 Rev. *B Page 6 of 11 [+] Feedback CY7C1089DV33 Switching Waveforms Figure 4. Read Cycle No. 1 [12, 13, 14] tRC RC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Figure 5. Read Cycle No. 2 (OE Controlled) [12, 14, 15] tRC ADDRESS CE tACE OE tDOE tLZOE DATA OUT VCC SUPPLY CURRENT HIGH IMPEDANCE tLZCE tPU 50% DATA VALID tPD 50% tHZOE tHZCE HIGH IMPEDANCE ICC ISB Notes 12. CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other combinations, CE is HIGH. 13. The device is continuously selected. CE = VIL. 14. WE is HIGH for read cycle. 15. Address valid before or similar to CE transition LOW. Document Number: 001-53993 Rev. *B Page 7 of 11 [+] Feedback CY7C1089DV33 Switching Waveforms (continued) Figure 6. Write Cycle No. 1 (CE Controlled) [16, 17, 18] tWC ADDRESS CE tSA tSCE tAW tPWE WE tSD DATA I/O DATAIN VALID tHD tHA Figure 7. Write Cycle No. 2 (WE Controlled, OE LOW) [16, 17, 18] tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA tHZWE DATA I/O tSD DATAIN VALID tHD tLZWE Notes 16. CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other combinations, CE is HIGH. 17. Data I/O is high impedance if OE = VIH. 18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document Number: 001-53993 Rev. *B Page 8 of 11 [+] Feedback CY7C1089DV33 Truth Table CE1 H X L L L CE2 X L H H H OE X X L X H WE X X H L H I/O0 – I/O7 High-Z High-Z Data Out Data In High-Z Power down Power down Read all bits Write all bits Selected, Outputs disabled Mode Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 12 Ordering Code CY7C1089DV33-12BAXI Package Diagram 001-50044 Package Type 48-ball FBGA (8 × 9.5 × 1.4 mm) (Pb-free) Operating Range Industrial Ordering Code Definition CY 7 C 1 08 9 D V33 - xx xxx x Temperature Range: x = I I = Industrial Package Type: xxx = BAX BAX = 48-ball FBGA (Pb-free) Speed: xx = 12 ns V33 = Voltage range (3 V to 3.6 V) D = C9, 90 nm Technology 9 = Data width × 8 bits 08 = 64-Mbit density 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS 7 = SRAM CY = Cypress Document Number: 001-53993 Rev. *B Page 9 of 11 [+] Feedback CY7C1089DV33 Package Diagram Figure 8. 48-Ball FBGA (8 x 9.5 x 1.4 mm) (001-50044) 001-50044 *C Acronyms Acronym CMOS FBGA I/O SRAM TTL Description complementary metal oxide semiconductor fine ball grid array input/output static random access memory transistor-transistor logic Document Conventions Units of Measure Symbol °C μA mA MHz ns pF V Ω W Unit of Measure degrees Celsius microamperes milliampere megahertz nanoseconds picofarads volts ohms watts Document Number: 001-53993 Rev. *B Page 10 of 11 [+] Feedback CY7C1089DV33 Document History Page Document Title: CY7C1089DV33, 64-Mbit (8M x 8) Static RAM Document Number: 001-53993 REV. ** *A ECN NO. 2746867 3100499 Submission Date 07/31/2009 12/02/2010 Orig. of Change VKN/AESA New Data sheet PRAS Updated Note 12. Changed datasheet status from Preliminary to Final. Updated Package Diagram and Sales, Solutions, and Legal Information. Added Acronyms, Document Conventions and Ordering Code Definition. Post to external web. Description of Change *B 3178259 21/02/2011 PRAS Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-53993 Rev. *B Revised February 21, 2011 Page 11 of 11 All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback