CY7C1261V18, CY7C1276V18
CY7C1263V18, CY7C1265V18
36-Mbit QDR™-II+ SRAM 4-Word Burst
Architecture (2.5 Cycle Read Latency)
Features
■
Configurations
With Read Cycle Latency of 2.5 cycles:
Separate independent read and write data ports
❐ Supports concurrent transactions
■
300 MHz to 400 MHz clock for high bandwidth
■
4-Word Burst for reducing address bus frequency
CY7C1261V18 – 4M x 8
CY7C1276V18 – 4M x 9
CY7C1263V18 – 2M x 18
CY7C1265V18 – 1M x 36
■
Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 800 MHz) at 400 MHz
Functional Description
■
Read latency of 2.5 clock cycles
■
Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■
Single multiplexed address input bus latches address inputs
for both read and write ports
■
Separate Port Selects for depth expansion
■
Data valid pin (QVLD) to indicate valid data on the output
■
Synchronous internally self-timed writes
■
Available in x8, x9, x18, and x36 configurations
■
Full data coherency providing most current data
■
Core VDD = 1.8V ± 0.1V; IO VDDQ = 1.4V to VDD[1]
■
HSTL inputs and variable drive HSTL output buffers
■
Available in 165-ball FBGA package (15 x 17 x 1.4 mm)
The CY7C1261V18, CY7C1276V18, CY7C1263V18, and
CY7C1265V18 are 1.8V Synchronous Pipelined SRAMs,
equipped with Quad Data Rate-II+ (QDR-II+) architecture.
QDR-II+ architecture consists of two separate ports to access
the memory array. The read port has dedicated data outputs to
support read operations and the write port has dedicated data
inputs to support write operations. QDR-II+ architecture has
separate data inputs and data outputs to completely eliminate
the need to “turn around” the data bus required with common IO
devices. Each port is accessed through a common address bus.
Addresses for read and write addresses are latched on alternate
rising edges of the input (K) clock. Accesses to the QDR-II+ read
and write ports are completely independent of one another. To
maximize data throughput, both read and write ports are
equipped with Double Data Rate (DDR) interfaces. Each
address location is associated with four 8-bit words
(CY7C1261V18), 9-bit words (CY7C1276V18), 18-bit words
(CY7C1263V18), or 36-bit words (CY7C1265V18) that burst
sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input
clocks (K and K), memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds”.
■
Offered in both Pb-free and non Pb-free packages
■
JTAG 1149.1 compatible test access port
■
Delay Lock Loop (DLL) for accurate data placement
Depth expansion is accomplished with Port Selects for each port.
Port selects enable each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Selection Guide
400 MHz
375 MHz
333 MHz
300 MHz
Unit
Maximum Operating Frequency
Description
400
375
333
300
MHz
Maximum Operating Current
1330
1240
1120
1040
mA
Note
1. The QDR consortium specification for VDDQ is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting
VDDQ = 1.4V to VDD.
Cypress Semiconductor Corporation
Document Number: 001-06366 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 01, 2008
[+] Feedback
CY7C1261V18, CY7C1276V18
CY7C1263V18, CY7C1265V18
Logic Block Diagram (CY7C1261V18)
DOFF
Write
Reg
Address
Register
Read Add. Decode
CLK
Gen.
Write
Reg
1M x 8 Array
K
K
Write
Reg
1M x 8 Array
20
Write
Reg
1M x 8 Array
Address
Register
1M x 8 Array
A(19:0)
8
Write Add. Decode
D[7:0]
A(19:0)
20
RPS
Control
Logic
Read Data Reg.
32
VREF
WPS
CQ
16
Reg.
Control
Logic
NWS[1:0]
CQ
16
Reg.
Q[7:0]
Reg.
8
8
QVLD
Logic Block Diagram (CY7C1276V18)
DOFF
VREF
WPS
BWS[0]
Address
Register
Read Add. Decode
CLK
Gen.
Write
Reg
1M x 9 Array
K
K
Write
Reg
1M x 9 Array
20
Write
Reg
1M x 9 Array
Address
Register
Write
Reg
1M x 9 Array
A(19:0)
9
Write Add. Decode
D[8:0]
A(19:0)
20
RPS
Control
Logic
Read Data Reg.
36
Control
Logic
CQ
CQ
18
Reg.
18
Reg.
Q[8:0]
Reg.
9
9
Document Number: 001-06366 Rev. *E
QVLD
Page 2 of 29
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CY7C1261V18, CY7C1276V18
CY7C1263V18, CY7C1265V18
Logic Block Diagram (CY7C1263V18)
DOFF
Write
Reg
Address
Register
Read Add. Decode
CLK
Gen.
Write
Reg
512K x 18 Array
K
K
Write
Reg
512K x 18 Array
19
Write
Reg
512K x 18 Array
Address
Register
512K x 18 Array
A(18:0)
18
Write Add. Decode
D[17:0]
19
A(18:0)
RPS
Control
Logic
Read Data Reg.
72
VREF
WPS
CQ
36
Reg.
Control
Logic
BWS[1:0]
CQ
Reg.
Q[17:0]
36
Reg.
18
18
QVLD
Logic Block Diagram (CY7C1265V18)
DOFF
VREF
WPS
BWS[3:0]
Write
Reg
Address
Register
Read Add. Decode
CLK
Gen.
Write
Reg
256K x 36 Array
K
K
Write
Reg
256K x 36 Array
18
Write
Reg
256K x 36 Array
Address
Register
256K x 36 Array
A(17:0)
36
Write Add. Decode
D[35:0]
18
A(17:0)
RPS
Control
Logic
Read Data Reg.
144
Control
Logic
CQ
CQ
72
Reg.
72
Reg.
Q[35:0]
Reg.
36
36
Document Number: 001-06366 Rev. *E
QVLD
Page 3 of 29
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CY7C1261V18, CY7C1276V18
CY7C1263V18, CY7C1265V18
Pin Configurations
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1261V18 (4M x 8)
1
2
3
4
5
6
7
8
9
10
11
A
CQ
NC/72M
A
WPS
NWS1
K
NC/144M
RPS
A
A
CQ
B
C
D
E
F
G
H
J
K
L
M
N
P
NC
NC
NC
NC
NC
D4
NC
NC
NC
A
VSS
VSS
NC/288M
A
NWS0
A
VSS
A
VSS
VSS
NC
NC
VSS
K
NC
VSS
NC
NC
NC
NC
Q3
D3
NC
NC
NC
Q4
VDDQ
VSS
VSS
VSS
VDDQ
NC
D2
Q2
NC
NC
NC
NC
VDDQ
VDD
VSS
DOFF
NC
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
NC
NC
VDDQ
NC
NC
Q5
VDDQ
NC
VDD
VDD
VDD
VDD
VDDQ
D5
VREF
NC
NC
VREF
Q1
NC
NC
ZQ
D1
R
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
NC
Q6
D6
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q0
NC
NC
NC
D7
NC
NC
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
NC
NC
D0
NC
NC
NC
Q7
A
A
QVLD
A
A
NC
NC
NC
TDO
TCK
A
A
A
NC
A
A
A
TMS
TDI
CY7C1276V18 (4M x 9)
1
2
3
4
5
6
7
8
9
10
11
CQ
NC/72M
A
WPS
NC
K
NC/144M
RPS
A
A
CQ
NC
NC
NC
A
NC/288M
K
BWS0
A
NC
NC
Q4
NC
NC
NC
D5
NC
NC
VSS
VSS
A
A
VSS
VSS
VSS
NC
VSS
NC
VSS
NC
NC
D4
NC
NC
Q5
VDDQ
VSS
VSS
VSS
VDDQ
NC
D3
Q3
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
D6
VREF
NC
Q6
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
NC
VDDQ
NC
NC
VREF
Q2
NC
NC
ZQ
D2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC
NC
NC
DOFF
NC
R
NC
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
NC
Q7
D7
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q1
NC
NC
NC
D8
NC
NC
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
NC
NC
D1
NC
NC
NC
Q8
A
A
QVLD
A
A
NC
D0
Q0
TDO
TCK
A
A
A
NC
A
A
A
TMS
TDI
Document Number: 001-06366 Rev. *E
Page 4 of 29
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CY7C1261V18, CY7C1276V18
CY7C1263V18, CY7C1265V18
Pin Configurations (continued)
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1263V18 (2M x 18)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
2
3
4
5
6
7
8
9
10
11
CQ
NC
NC/144M
A
K
K
NC/72M
CQ
NC
NC
NC
D11
D10
Q10
VSS
VSS
A
VSS
NC
VSS
BWS0
A
VSS
RPS
A
A
D9
BWS1
NC
NC/288M
Q9
WPS
A
NC
NC
Q11
VDDQ
VSS
VSS
NC
NC
Q8
VSS
VSS
NC
NC
Q7
NC
D8
D7
VSS
VDDQ
NC
D6
Q6
NC
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
Q5
NC
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
NC
D5
DOFF
NC
VREF
NC
VDDQ
D14
VDDQ
VDDQ
VDD
VDD
VSS
VSS
VDD
VDD
VDDQ
VDDQ
NC
VDDQ
NC
VREF
Q4
ZQ
D4
NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
NC
D3
Q3
NC
Q15
D15
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q2
NC
NC
NC
D17
D16
Q16
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
Q1
NC
D2
D1
NC
NC
Q17
A
A
QVLD
A
A
NC
D0
Q0
TDO
TCK
A
A
A
NC
A
A
A
TMS
TDI
CY7C1265V18 (1M x 36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
3
NC/288M NC/72M
4
5
6
7
8
9
10
11
BWS2
K
BWS1
A
NC/144M
CQ
BWS3
A
VSS
K
D17
Q17
Q8
NC
VSS
BWS0
A
VSS
RPS
A
VSS
VSS
D16
Q16
Q7
D15
D8
D7
Q18
D18
WPS
A
Q28
D20
D19
Q19
VSS
VSS
Q29
D29
Q20
VDDQ
VSS
VSS
VSS
VDDQ
Q15
D6
Q6
Q30
Q21
D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
Q14
Q5
D30
D22
VREF
Q31
Q22
VDDQ
D23
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
Q13
VDDQ
D12
D13
VREF
Q4
D5
ZQ
D4
CQ
Q27
D27
D28
DOFF
D31
Q32
D32
Q23
VDDQ
VDD
VSS
VDD
VDDQ
Q12
D3
Q3
Q33
Q24
D24
VDDQ
VSS
VSS
VSS
VDDQ
D11
Q11
Q2
D33
D34
Q34
D26
D25
Q25
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
D10
Q10
Q1
D9
D2
D1
Q35
D35
Q26
A
A
QVLD
A
A
Q9
D0
Q0
TDO
TCK
A
A
A
NC
A
A
A
TMS
TDI
Document Number: 001-06366 Rev. *E
Page 5 of 29
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CY7C1261V18, CY7C1276V18
CY7C1263V18, CY7C1265V18
Pin Definitions
Pin Name
IO
Pin Description
D[x:0]
Data Input Signals. Sampled on the rising edge of K and K clocks during valid write operations.
InputSynchronous CY7C1261V18 – D[7:0]
CY7C1276V18 – D[8:0]
CY7C1263V18 – D[17:0]
CY7C1265V18 – D[35:0]
WPS
InputWrite Port Select, Active LOW. Sampled on the rising edge of the K clock. When asserted
Synchronous active, a write operation is initiated. Deasserting deselects the write port. Deselecting the write
port causes D[x:0] to be ignored.
NWS0, NWS1,
InputNibble Write Select 0, 1, Active LOW (CY7C1261V18 Only). Sampled on the rising edge of
Synchronous the K and K clocks when write operations are active. Used to select which nibble is written into
the device during the current portion of the write operations. NWS0 controls D[3:0] and NWS1
controls D[7:4].
All the Nibble Write Selects are sampled on the same edge as the data. The corresponding
nibble of data is ignored by deselecting a nibble write select and is not written into the device.
BWS0, BWS1,
BWS2, BWS3
Byte Write Select 0, 1, 2, and 3, Active LOW. Sampled on the rising edge of the K and K clocks
InputSynchronous during write operations. Used to select which byte is written into the device during the current
portion of the Write operations. Bytes not written remain unaltered.
CY7C1276V18 – BWS0 controls D[8:0]
CY7C1263V18 – BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1265V18 – BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18], and BWS3
controls D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
Select causes the corresponding byte of data to be ignored and not written into the device.
A
InputAddress Inputs. Sampled on the rising edge of the K clock during active read and write operaSynchronous tions. These address inputs are multiplexed for both read and write operations. Internally, the
device is organized as 4M x 8 (4 arrays each of 1M x 8) for CY7C1261V18, 4M x 9 (4 arrays
each of 1M x 9) for CY7C1276V18, 2M x 18 (4 arrays each of 512K x 18) for CY7C1263V18
and 1M x 36 (4 arrays each of 256K x 36) for CY7C1265V18. Therefore, only 20 address inputs
are needed to access the entire memory array of CY7C1261V18 and CY7C1276V18, 19 address
inputs for CY7C1263V18 and 18 address inputs for CY7C1265V18. These inputs are ignored
when the appropriate port is deselected.
Q[x:0]
OutputsData Output Signals. These pins drive out the requested data during a read operation. Valid
Synchronous data is driven out on the rising edge of both the K and K clocks during read operations. When
the read port is deselected, Q[x:0] are automatically tri-stated.
CY7C1261V18 – Q[7:0]
CY7C1276V18 – Q[8:0]
CY7C1263V18 – Q[17:0]
CY7C1265V18 – Q[35:0]
RPS
InputRead Port Select, Active LOW. Sampled on the rising edge of Positive Input Clock (K). When
Synchronous active, a read operation is initiated. Deasserting causes the read port to be deselected. When
deselected, the pending access is allowed to complete and the output drivers are automatically
tri-stated following the next rising edge of the K clock. Each read access consists of a burst of
four sequential transfers.
QVLD
Valid Output
Indicator
Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ
and CQ.
K
InputClock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the
device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated
on the rising edge of K.
K
InputClock
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the
device and to drive out data through Q[x:0] when in single clock mode.
Document Number: 001-06366 Rev. *E
Page 6 of 29
[+] Feedback
CY7C1261V18, CY7C1276V18
CY7C1263V18, CY7C1265V18
Pin Definitions
Pin Name
(continued)
IO
Pin Description
CQ
Echo Clock
Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the
input clock (K) of the QDR-II+. The timing for the echo clocks is shown in Switching Characteristics on page 24.
CQ
Echo Clock
Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the
input clock (K) of the QDR-II+. The timing for the echo clocks is shown in Switching Characteristics on page 24.
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system
data bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a
resistor connected between ZQ and ground. Alternatively, this pin can be connected directly to
VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to
GND or left unconnected.
DOFF
Input
DLL Turn Off, Active LOW. Connecting this pin to ground turns off the DLL inside the device.
The timing in the DLL turned off operation is different from that listed in this data sheet. For
normal operation, this pin can be connected to a pull up through a 10 Kohm or less pull up
resistor. The device behaves in QDR-I mode when the DLL is turned off. In this mode, the device
can be operated at a frequency of up to 167 MHz with QDR-I timing.
TDO
Output
TCK
Input
TCK Pin for JTAG.
TDI
Input
TDI Pin for JTAG.
TMS
Input
TMS Pin for JTAG.
NC
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/72M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/144M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/288M
N/A
Not Connected to the Die. Can be tied to any voltage level.
VREF
VDD
VSS
VDDQ
InputReference
TDO for JTAG.
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs,
and AC measurement points.
Power Supply Power Supply Inputs to the Core of the Device.
Ground
Ground for the Device.
Power Supply Power Supply Inputs for the Outputs of the Device.
Document Number: 001-06366 Rev. *E
Page 7 of 29
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CY7C1261V18, CY7C1276V18
CY7C1263V18, CY7C1265V18
Functional Overview
The CY7C1261V18, CY7C1276V18, CY7C1263V18, and
CY7C1265V18 are synchronous pipelined Burst SRAMs
equipped with a read port and a write port. The read port is
dedicated to read operations and the write port is dedicated to
write operations. Data flows into the SRAM through the write port
and out through the read port. These devices multiplex the
address inputs to minimize the number of address pins required.
By having separate read and write ports, the QDR-II+ completely
eliminates the need to “turn around” the data bus and avoids any
possible data contention, thereby simplifying system design.
Each access consists of four 8-bit data transfers in the case of
CY7C1261V18, four 9-bit data transfers in the case of
CY7C1276V18, four 18-bit data transfers in the case of
CY7C1263V18, and four 36-bit data transfers in the case of
CY7C1265V18, in two clock cycles.
Accesses for both ports are initiated on the Positive Input Clock
(K). All synchronous input and output timing refer to the rising
edge of the Input clocks (K/K).
All synchronous data inputs (D[x:0]) inputs pass through input
registers controlled by the input clocks (K and K). All
synchronous data outputs (Q[x:0]) outputs pass through output
registers controlled by the rising edge of the Input clocks (K and
K).
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass
through input registers controlled by the rising edge of the input
clocks (K/K).
CY7C1263V18 is described in the following sections. The same
basic descriptions apply to CY7C1261V18, CY7C1276V18, and
CY7C1265V18.
Read Operations
The CY7C1263V18 is organized internally as 4 arrays of 512K x
18. Accesses are completed in a burst of four sequential 18-bit
data words. Read operations are initiated by asserting RPS
active at the rising edge of the Positive Input Clock (K). The
addresses presented to address inputs are stored in the Read
address register. Following the next two K clock rising edges, the
corresponding lowest order 18-bit word of data is driven onto the
Q[17:0] using K as the output timing reference. On the subsequent rising edge of K the next 18-bit data word is driven onto
the Q[17:0]. This process continues until all four 18-bit data words
have been driven out onto Q[17:0]. The requested data is valid
0.45 ns from the rising edge of the Input clock (K or K). To
maintain the internal logic, each read access must be allowed to
complete. Each read access consists of four 18-bit data words
and takes two clock cycles to complete. Therefore, read
accesses to the device cannot be initiated on two consecutive K
clock rises. The internal logic of the device ignores the second
read request. Read accesses can be initiated on every other K
clock rise. Doing so pipelines the data flow such that data is
transferred out of the device on every rising edge of the input
clocks (K and K).
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the Positive Input Clock (K). On the following K
clock rise, the data presented to D[17:0] is latched and stored into
the lower 18-bit Write Data register, provided BWS[1:0] are both
asserted active. On the subsequent rising edge of the Negative
Input Clock (K), the information presented to D[17:0] is also stored
into the Write Data register, provided BWS[1:0] are both asserted
active. This process continues for one more cycle until four 18-bit
words (a total of 72 bits) of data are stored in the SRAM. The 72
bits of data are then written into the memory array at the specified
location. Therefore, write accesses to the device cannot be
initiated on two consecutive K clock rises. The internal logic of
the device ignores the second write request. Write accesses can
be initiated on every other rising edge of the Positive Input Clock
(K). Doing so pipelines the data flow such that 18 bits of data can
be transferred into the device on every rising edge of the input
clocks (K and K). When deselected, the write port ignores all
inputs after the pending write operations have been completed.
Byte Write Operations
Byte write operations are supported by the CY7C1263V18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS0 and
BWS1, which are sampled with each set of 18-bit data words.
Asserting the appropriate Byte Write Select input during the data
portion of a write latches the data being presented and written
into the device. Deasserting the Byte Write Select input during
the data portion of a write enables the data stored in the device
for that byte to remain unaltered. This feature can be used to
simplify read/modify/write operations to a byte write operation.
Concurrent Transactions
The read and write ports on the CY7C1263V18 operate
completely independently of one another. Because each port
latches the address inputs on different clock edges, the user can
read or write to any location, regardless of the transaction on the
other port. If the ports access the same location when a read
follows a write in successive clock cycles, the SRAM delivers the
most recent information associated with the specified address
location. This includes forwarding data from a write cycle that
was initiated on the previous K clock rise.
Read accesses and write access must be scheduled such that
one transaction is initiated on any clock cycle. If both ports are
selected on the same K clock rise, the arbitration depends on the
previous state of the SRAM. If both ports are deselected, the
read port takes priority. If a read was initiated on the previous
cycle, the Write port assumes priority (because read operations
cannot be initiated on consecutive cycles). If a write was initiated
on the previous cycle, the read port assumes priority (because
write operations cannot be initiated on consecutive cycles).
Therefore, asserting both port selects active from a deselected
state results in alternating read/write operations being initiated,
with the first access being a read.
When the read port is deselected, the CY7C1263V18=
completes the pending read transactions. Synchronous internal
circuitry automatically tri-states the outputs following the next
rising edge of the negative Input Clock (K). This enables a
seamless transition between devices without the insertion of wait
states in a depth expanded memory.
Document Number: 001-06366 Rev. *E
Page 8 of 29
[+] Feedback
CY7C1261V18, CY7C1276V18
CY7C1263V18, CY7C1265V18
Depth Expansion
Valid Data Indicator (QVLD)
The CY7C1263V18 has a Port Select input for each port. This
enables easy depth expansion. Both Port Selects are sampled
on the rising edge of the Positive Input Clock only (K). Each port
select input can deselect the specified port. Deselecting a port
does not affect the other port. All pending transactions (read and
write) are completed before the device is deselected.
QVLD is provided on the QDR-II+ to simplify data capture on high
speed systems. The QVLD is generated by the QDR-II+ device
along with data output. This signal is also edge aligned with the
echo clock and follows the timing of any data pin. This signal is
asserted half a cycle before valid data arrives.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and VSS to enable the SRAM to adjust its output
driver impedance. The value of RQ must be 5X the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175Ω and 350Ω, with VDDQ = 1.5V. The
output impedance is adjusted every 1024 cycles upon power up
to account for drifts in supply voltage and temperature.
Echo Clocks
Delay Lock Loop (DLL)
These chips use a DLL that is designed to function between 120
MHz and the specified maximum clock frequency. To disable the
DLL, apply ground to the DOFF pin. When the DLL is turned off,
the device behaves in QDR-I mode (with 1.0 cycle latency and a
longer access time). For more information, refer to the application
note,
DLL
Considerations
in
QDRII/DDRII/QDRII+/DDRII+. The DLL can also be reset by
slowing or stopping the input clocks K and K for a minimum of 30
ns. However, it is not necessary for the DLL to be reset to lock to
the frequency you want. During power up, when the DOFF is tied
HIGH, the DLL is locked after 2048 cycles of stable clock.
Echo clocks are provided on the QDR-II+ to simplify data capture
on high speed systems. Two echo clocks are generated by the
QDR-II+. CQ is referenced with respect to K and CQ is referenced with respect to K. These are free running clocks and are
synchronized to the input clock of the QDR-II+. The timing for the
echo clocks is shown in Switching Characteristics on page 24.
Document Number: 001-06366 Rev. *E
Page 9 of 29
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CY7C1261V18, CY7C1276V18
CY7C1263V18, CY7C1265V18
Application Example
Figure 1 shows the use of four QDR-II+ SRAMs in an application.
Figure 1. Application Example
ZQ
CQ/CQ
SRAM #1
Q
D
A RPS WPS BWS K K
Vt
R
RQ = 250ohms
ZQ
CQ/CQ
SRAM #4
Q
RPS WPS BWS K K
D
A
DATA IN
DATA OUT
Address
R
R
BUS MASTER RPS
(CPU or ASIC) WPS
RQ = 250ohms
Vt
Vt
BWS
CLKIN/CLKIN
Source K
Source K
R = 50ohms, Vt = VDDQ /2
Truth Table
The truth table for the CY7C1261V18, CY7C1276V18, CY7C1263V18, and CY7C1265V18 follows.[2, 3, 4, 5, 6, 7]
Operation
K
RPS WPS
DQ
DQ
DQ
DQ
L-H
Write Cycle:
Load address on the
rising edge of K; input
write data on two
consecutive K and K
rising edges.
H[8]
L[9]
D(A) at K(t + 1) ↑ D(A + 1) at K(t +1) ↑ D(A + 2) at K(t + 2) ↑ D(A + 3) at K(t + 2) ↑
L-H
Read Cycle:
(2.5 cycle Latency)
Load address on the
rising edge of K; wait
two and half cycle;
read data on two
consecutive K and K
rising edges.
L[9]
X
Q(A) at K(t + 2) ↑ Q(A + 1) at K(t + 3) ↑ Q(A + 2) at K(t + 3) ↑ Q(A + 3) at K(t + 4) ↑
NOP: No Operation
L-H
H
H
D=X
Q = High-Z
D=X
Q = High-Z
D=X
Q = High-Z
D=X
Q = High-Z
Standby: Clock
Stopped
Stopped X
X
Previous State
Previous State
Previous State
Previous State
Notes
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.
3. Device powers up deselected with the outputs in a tri-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A + 3 represent the address sequence in the burst.
5. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, t + 3 and t + 4 are the first, second, third, and fourth clock cycles, respectively,
succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges.
7. Cypress recommends that K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
8. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.
9. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores
the second read or write request.
Document Number: 001-06366 Rev. *E
Page 10 of 29
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CY7C1261V18, CY7C1276V18
CY7C1263V18, CY7C1265V18
Write Cycle Descriptions
The write cycle descriptions table for CY7C1261V18 and CY7C1263V18 follows.[2, 10]
BWS0/ BWS1/
NWS0 NWS1
K
K
–
L
L
L–H
L
L
–
L
H
L–H
L
H
–
H
L
L–H
H
L
–
H
H
L–H
H
H
–
Comments
During the data portion of a write sequence:
CY7C1261V18 − both nibbles (D[7:0]) are written into the device.
CY7C1263V18 − both bytes (D[17:0]) are written into the device.
L-H During the data portion of a write sequence:
CY7C1261V18 − both nibbles (D[7:0]) are written into the device.
CY7C1263V18 − both bytes (D[17:0]) are written into the device.
–
During the data portion of a write sequence:
CY7C1261V18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1263V18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L–H During the data portion of a write sequence:
CY7C1261V18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1263V18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
–
During the data portion of a write sequence:
CY7C1261V18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1263V18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
L–H During the data portion of a write sequence:
CY7C1261V18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1263V18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
–
No data is written into the devices during this portion of a write operation.
L–H No data is written into the devices during this portion of a write operation.
Write Cycle Descriptions
The write cycle descriptions table for CY7C1276V18 follows.[2, 10]
BWS0
K
K
Comments
L
L–H
–
During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.
L
–
L–H
During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.
H
L–H
–
No data is written into the device during this portion of a write operation.
H
–
L–H
No data is written into the device during this portion of a write operation.
Note
10. Assumes a write cycle was initiated per the Write Cycle Descriptions table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on different portions
of a write cycle, as long as the setup and hold requirements are met.
Document Number: 001-06366 Rev. *E
Page 11 of 29
[+] Feedback
CY7C1261V18, CY7C1276V18
CY7C1263V18, CY7C1265V18
Write Cycle Descriptions
The write cycle descriptions table for CY7C1265V18 follows.[2, 10]
BWS0
BWS1
BWS2
BWS3
K
K
Comments
L
L
L
L
L–H
–
During the data portion of a write sequence, all four bytes (D[35:0]) are written
into the device.
L
L
L
L
–
L
H
H
H
L–H
L
H
H
H
–
H
L
H
H
L–H
H
L
H
H
–
H
H
L
H
L–H
H
H
L
H
–
H
H
H
L
L–H
H
H
H
L
–
H
H
H
H
L–H
H
H
H
H
–
Document Number: 001-06366 Rev. *E
L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written
into the device.
–
During the data portion of a write sequence, only the lower byte (D[8:0]) is
written into the device. D[35:9] remains unaltered.
L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is
written into the device. D[35:9] remains unaltered.
–
During the data portion of a write sequence, only the byte (D[17:9]) is written
into the device. D[8:0] and D[35:18] remain unaltered.
L–H During the data portion of a write sequence, only the byte (D[17:9]) is written
into the device. D[8:0] and D[35:18] remain unaltered.
–
During the data portion of a write sequence, only the byte (D[26:18]) is written
into the device. D[17:0] and D[35:27] remain unaltered.
L–H During the data portion of a write sequence, only the byte (D[26:18]) is written
into the device. D[17:0] and D[35:27] remain unaltered.
–
During the data portion of a write sequence, only the byte (D[35:27]) is written
into the device. D[26:0] remains unaltered.
L–H During the data portion of a write sequence, only the byte (D[35:27]) is written
into the device. D[26:0] remains unaltered.
–
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
Page 12 of 29
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CY7C1261V18, CY7C1276V18
CY7C1263V18, CY7C1265V18
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant with
IEEE Standard #1149.1-2001. The TAP operates using JEDEC
standard 1.8V IO logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, tie TCK LOW (VSS) to
prevent device clocking. TDI and TMS are internally pulled up
and may be unconnected. They may alternatively be connected
to VDD through a pull up resistor. TDO must be left unconnected.
Upon power up, the device comes up in a reset state, which does
not interfere with the operation of the device.
Test Access Port – Test Clock
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. You can leave this pin
unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see the TAP Controller State
Diagram on page 15. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO pins as shown in TAP Controller Block Diagram on
page 16. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
When the TAP controller is in the Capture IR state, the two least
significant bits are loaded with a binary ‘01’ pattern to enable fault
isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This shifts data through the SRAM with minimal
delay. The bypass register is set LOW (VSS) when the BYPASS
instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are also
included in the scan register to reserve pins for higher density
devices.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
be used to capture the contents of the input and output ring.
Boundary Scan Order on page 20 shows the order in which the
bits are connected. Each bit corresponds to one of the bumps on
the SRAM package. The MSB of the register is connected to TDI,
and the LSB is connected to TDO.
Test Data-Out (TDO)
Identification (ID) Register
The TDO output pin is used to serially clock data-out from the
registers. Whether the output is active depends on the current
state of the TAP state machine (see Instruction Codes on page
19). The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 19.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating. At
power up, the TAP is reset internally to ensure that TDO comes
up in a high-Z state.
TAP Instruction Set
TAP Registers
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Instruction
Codes on page 19. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in this section in detail.
Registers are connected between the TDI and TDO pins and
scans data into and out of the SRAM test circuitry. Only one
register can be selected at a time through the instruction
registers. Data is serially loaded into the TDI pin on the rising
edge of TCK. Data is output on the TDO pin on the falling edge
of TCK.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
Document Number: 001-06366 Rev. *E
Page 13 of 29
[+] Feedback
CY7C1261V18, CY7C1276V18
CY7C1263V18, CY7C1265V18
IDCODE
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO pins and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register upon
power up or whenever the TAP controller is in a Test-Logic-Reset
state.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a High-Z state until the next command is issued during the
Update-IR state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is captured in the boundary scan register.
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells before the selection
of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required — that is, while data captured
is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the Shift-DR controller state.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
Be aware that the TAP controller clock can only operate at a
frequency up to 20 MHz, although the SRAM clock operates
more than an order of magnitude faster. Because there is a large
difference in the clock frequencies, it is possible that during the
Capture-DR state, an input or output may undergo a transition.
The TAP may then try to capture a signal while in transition
(metastable state). This does not harm the device, but there is
no guarantee as to the value that is captured. Repeatable results
may not be possible.
The boundary scan register has a special bit located at bit #108.
When this scan cell, called the “extest output bus tri-state,” is
latched into the preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
High-Z condition.
To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long
enough to meet the TAP controller's capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the
output Q-bus pins. Note that this bit is preset HIGH to enable the
output when the device is powered up, and also when the TAP
controller is in the Test-Logic-Reset state.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
Reserved
Document Number: 001-06366 Rev. *E
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Page 14 of 29
[+] Feedback
CY7C1261V18, CY7C1276V18
CY7C1263V18, CY7C1265V18
TAP Controller State Diagram
The state diagram for the TAP Controller follows.[11]
1
TEST-LOGIC
RESET
0
0
TEST-LOGIC/
IDLE
1
1
1
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
0
SHIFT-IR
1
1
1
EXIT1-DR
1
EXIT1-IR
0
0
PAUSE-DR
0
0
PAUSE-IR
1
1
0
0
EXIT2-DR
EXIT2-IR
1
1
UPDATE-DR
1
0
UPDATE-IR
1
0
Note
11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK
Document Number: 001-06366 Rev. *E
Page 15 of 29
[+] Feedback
CY7C1261V18, CY7C1276V18
CY7C1263V18, CY7C1265V18
TAP Controller Block Diagram
0
Bypass Register
Selection
Circuitry
TDI
2
1
0
1
0
Instruction Register
31 30 29
.
.
2
Selection
Circuitry
TDO
Min
Unit
Identification Register
108 .
.
.
.
2
1
0
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics
Over the Operating Range[12, 13, 14]
Parameter
Description
Test Conditions
Max
VOH1
Output HIGH Voltage
IOH = −2.0 mA
1.4
V
VOH2
Output HIGH Voltage
IOH = −100 μA
1.6
V
VOL1
Output LOW Voltage
IOL = 2.0 mA
0.4
V
VOL2
Output LOW Voltage
IOL = 100 μA
0.2
V
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IX
Input and Output Load Current
0.65VDD VDD + 0.3
GND ≤ VI ≤ VDD
V
–0.3
0.35VDD
V
–5
5
μA
Notes
12. These characteristics apply to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in Electrical Characteristics on page 22.
13. Overshoot: VIH(AC) < VDDQ + 0.3V (pulse width less than tCYC/2). Undershoot: VIL(AC) > −0.3V (pulse width less than tCYC/2).
14. All voltage refer to Ground.
Document Number: 001-06366 Rev. *E
Page 16 of 29
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CY7C1261V18, CY7C1276V18
CY7C1263V18, CY7C1265V18
TAP AC Switching Characteristics
Over the Operating Range[15, 16]
Parameter
Description
Min
Max
Unit
20
MHz
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
50
ns
tTH
TCK Clock HIGH
20
ns
tTL
TCK Clock LOW
20
ns
tTMSS
TMS Setup to TCK Clock Rise
5
ns
tTDIS
TDI Setup to TCK Clock Rise
5
ns
tCS
Capture Setup to TCK Rise
5
ns
tTMSH
TMS Hold after TCK Clock Rise
5
ns
tTDIH
TDI Hold after Clock Rise
5
ns
tCH
Capture Hold after Clock Rise
5
ns
Setup Times
Hold Times
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
Document Number: 001-06366 Rev. *E
10
0
ns
ns
Page 17 of 29
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CY7C1261V18, CY7C1276V18
CY7C1263V18, CY7C1265V18
TAP Timing and Test Conditions[16]
0.9V
ALL INPUT PULSES
50Ω
1.8V
0.9V
TDO
0V
Z0 = 50Ω
(a)
CL = 20 pF
tTH
GND
tTL
Test Clock
TCK
tTCYC
tTMSH
tTMSS
Test Mode Select
TMS
tTDIS
tTDIH
Test Data In
TDI
Test Data Out
TDO
tTDOV
tTDOX
Notes
15. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
16. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Document Number: 001-06366 Rev. *E
Page 18 of 29
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CY7C1261V18, CY7C1276V18
CY7C1263V18, CY7C1265V18
Identification Register Definitions
Value
Instruction
Field
CY7C1261V18
CY7C1276V18
CY7C1263V18
CY7C1265V18
000
000
000
000
Revision
Number (31:29)
Cypress Device
ID (28:12)
Description
Version number.
11010010001000111 11010010001001111 11010010001010111 11010010001100111 Defines the type
of SRAM.
Cypress JEDEC
ID (11:1)
00000110100
00000110100
00000110100
00000110100
Enables unique
identification of
SRAM vendor.
1
1
1
1
Indicates the
presence of an
ID register.
ID Register
Presence (0)
Scan Register Sizes
Register Name
Bit Size
Instruction
3
Bypass
1
ID
32
Boundary Scan
109
Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures the input/output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between
TDI and TDO. This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the input and output contents. Places the boundary scan register
between TDI and TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures the input/output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect the SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect
SRAM operation.
Document Number: 001-06366 Rev. *E
Page 19 of 29
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CY7C1261V18, CY7C1276V18
CY7C1263V18, CY7C1265V18
Boundary Scan Order
Bit #
Bump ID
Bit #
Bump ID
Bit #
Bump ID
Bit #
Bump ID
0
6R
28
10G
56
6A
84
1J
1
6P
29
9G
57
5B
85
2J
2
6N
30
11F
58
5A
86
3K
3
7P
31
11G
59
4A
87
3J
4
7N
32
9F
60
5C
88
2K
5
7R
33
10F
61
4B
89
1K
6
8R
34
11E
62
3A
90
2L
7
8P
35
10E
63
2A
91
3L
8
9R
36
10D
64
1A
92
1M
9
11P
37
9E
65
2B
93
1L
10
10P
38
10C
66
3B
94
3N
11
10N
39
11D
67
1C
95
3M
12
9P
40
9C
68
1B
96
1N
13
10M
41
9D
69
3D
97
2M
14
11N
42
11B
70
3C
98
3P
15
9M
43
11C
71
1D
99
2N
16
9N
44
9B
72
2C
100
2P
17
11L
45
10B
73
3E
101
1P
18
11M
46
11A
74
2D
102
3R
19
9L
47
10A
75
2E
103
4R
20
10L
48
9A
76
1E
104
4P
21
11K
49
8B
77
2F
105
5P
22
10K
50
7C
78
3F
106
5N
23
9J
51
6C
79
1G
107
5R
24
9K
52
8A
80
1F
108
Internal
25
10J
53
7A
81
3G
26
11J
54
7B
82
2G
27
11H
55
6B
83
1H
Document Number: 001-06366 Rev. *E
Page 20 of 29
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CY7C1261V18, CY7C1276V18
CY7C1263V18, CY7C1265V18
Power Up Sequence in QDR-II+ SRAM
DLL Constraints
QDR-II+ SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations. During
power up, when the DOFF is tied HIGH, the DLL is locked after
2048 cycles of stable clock.
■
DLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as tKC Var.
■
The DLL functions at frequencies down to 120 MHz.
■
If the input clock is unstable and the DLL is enabled, then the
DLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide 2048 cycles stable clock
to relock to the clock frequency you want.
Power Up Sequence
■
Apply power with DOFF tied HIGH (All other inputs can be
HIGH or LOW)
❐ Apply VDD before VDDQ
❐ Apply VDDQ before VREF or at the same time as VREF
■
Provide stable power and clock (K, K) for 2048 cycles to lock
the DLL
~
~
Figure 2. Power Up Waveforms
K
~
~
K
Unstable Clock
> 2048 Stable Clock
Start Normal
Operation
Clock Start (Clock Starts after VDD/VDDQ is Stable)
VDD/VDDQ
VDD/VDDQ Stable (< + 0.1V DC per 50 ns)
DOFF
Document Number: 001-06366 Rev. *E
Fix HIGH (tie to VDDQ)
Page 21 of 29
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CY7C1261V18, CY7C1276V18
CY7C1263V18, CY7C1265V18
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Current into Outputs (LOW)......................................... 20 mA
Storage Temperature ................................ –65°C to + 150°C
Latch Up Current .................................................... >200 mA
Static Discharge Voltage (MIL-STD-883, M. 3015)... >2001V
Ambient Temperature with Power Applied. –55°C to + 125°C
Supply Voltage on VDD Relative to GND .......–0.5V to + 2.9V
Operating Range
Supply Voltage on VDDQ Relative to GND ..... –0.5V to + VDD
DC Applied to Outputs in High-Z ........ –0.5V to VDDQ + 0.3V
DC Input Voltage[13] ............................... –0.5V to VDD + 0.3V
Range
Ambient
Temperature (TA)
VDD[17]
VDDQ[17]
0°C to +70°C
1.8 ± 0.1V
1.4V to VDD
Com’l
Ind’l
–40°C to +85°C
Electrical Characteristics
Over the Operating Range[14]
DC Electrical Characteristics
Min
Typ
Max
Unit
VDD
Parameter
Power Supply Voltage
Description
Test Conditions
1.7
1.8
1.9
V
VDDQ
IO Supply Voltage
1.4
1.5
VDD
V
VOH
Output HIGH Voltage
VOL
VOH(LOW)
Note 18
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
Output LOW Voltage
Note 19
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
Output HIGH Voltage
IOH = −0.1 mA, Nominal Impedance
VDDQ – 0.2
VDDQ
V
VOL(LOW)
Output LOW Voltage
IOL = 0.1 mA, Nominal Impedance
VSS
0.2
V
VIH
Input HIGH Voltage
VREF + 0.1
VDDQ + 0.15
V
VIL
Input LOW Voltage
–0.15
VREF – 0.1
V
IX
Input Leakage Current
GND ≤ VI ≤ VDDQ
−2
2
μA
IOZ
Output Leakage Current
GND ≤ VI ≤ VDDQ, Output Disabled
−2
2
μA
0.95
V
300 MHz
1040
mA
333 MHz
1120
mA
375 MHz
1240
mA
400 MHz
1330
mA
300 MHz
280
mA
333 MHz
300
mA
375 MHz
310
mA
400 MHz
320
mA
VREF
IDD
[21]
ISB1
Input Reference
Voltage[20]
VDD Operating Supply
Automatic
Power Down
Current
Typical Value = 0.75V
VDD = Max., IOUT = 0mA,
f = fMAX = 1/tCYC
Max. VDD, Both Ports
Deselected, VIN ≥ VIH or
VIN ≤ VIL
f = fMAX = 1/tCYC,
Inputs Static
0.68
0.75
AC Electrical Characteristics
Over the Operating Range [13]
Min
Typ.
Max
Unit
VIH
Parameter
Input HIGH Voltage
Description
Test Conditions
VREF + 0.2
–
VDDQ + 0.24
V
VIL
Input LOW Voltage
–0.24
–
VREF – 0.2
V
Notes
17. Power up: assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
18. Outputs are impedance controlled. IOH = −(VDDQ/2)/(RQ/5) for values of 175Ω
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