CY7C1298A-83NC

298A CY7C1298A/ GVT7164C18 64K x 18 Synchronous Burst RAM Pipelined Output Features • • • • • • • • • • • • • • • • • • • Fast access times: 5, 6, 7, and 8 ns Fast clock speed: 100, 83, 66, and 50 MHz Provide high-performance 3-1-1-1 access rate Fast OE access times: 5 and 6 ns Optimal for performance (two cycle chip deselect, depth expansion without wait state) Single +3.3V –5 to +10% power supply 5V tolerant inputs except I/Os Clamp diodes to VSSQ at all inputs and outputs Common data inputs and data outputs Byte Write Enable and Global Write control Three chip enables for depth expansion and address pipeline Address, control, input, and output pipeline registers Internally self-timed Write Cycle Write pass-through capability Burst control pins (interleaved or linear burst sequence) Automatic power-down for portable applications High-density, high-speed packages Low capacitive bus loading High 30-pF output drive capability at rated access time The CY7C1298A/GVT7164C18 SRAM integrates 65536x18 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), depth-expansion Chip Enables (CE2 and CE2), burst control inputs (ADSC, ADSP, and ADV), Write Enables (WEL, WEH, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and Burst Mode Control (MODE). The data outputs (Q), enabled by OE, are also asynchronous. Addresses and chip enables are registered with either Address Status Processor (ADSP) or Address Status Controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the burst advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate self-timed Write cycle. Write cycles can be one to four bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. WEL controls DQ1–DQ8 and DQP1. WEH controls DQ9–DQ16 and DQP2. WEL and WEH can be active only with BWE being LOW. GW being LOW causes all bytes to be written. This device also incorporates Write pass-through capability and pipelined enable circuit for better system performance. The CY7C1298A/GVT7164C18 operates from a +3.3V power supply. All inputs and outputs are TTL-compatible. The device is ideally suited for 486, Pentium®, 680x0, and PowerPC™ systems and for systems that are benefited from a wide synchronous data bus. Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced double-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors. Selection Guide 7C1298A-100 7164C18-5 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) 5 360 2 7C1298A-83 7164C18-6 6 315 2 7C1298A-66 7164C18-7 7 270 2 7C1298A-50 7164C18-8 8 225 2 Pentium is a registered trademark of Intel Corporation. PowerPC is a trademark of International Business Machines, Inc. Cypress Semiconductor Corporation Document #: 38-05194 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised January 19, 2003 CY7C1298A/ GVT7164C18 Functional Block Diagram—64K x 18[1] WEH# * BWE# UPPER BYTE WRITE D Q WEL# * GW# CE# * CE2 * CE2# ZZ OE# ADSP# Power Down Logic LOWER BYTE WRITE D Q lo byte write hi byte write Output Buffers ENABLE D Q D Q Input Register A15-A2 ADSC# Address Register 64K x 9 x 2 SRAM Array OUTPUT REGISTER CLR ADV# A1-A0 * MODE Binary Counter & Logic D Q DQ1DQ16, DQP1, DQP2 Note: 1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information. Document #: 38-05194 Rev. *A Page 2 of 12 CY7C1298A/ GVT7164C18 Pin Configuration 100-Pin TQFP Top View A6 A7 CE CE2 NC NC WEH WEL CE2 VCC VSS CLK GW BWE OE ADSC ADSP ADV A8 A9 NC NC NC VCCQ VSSQ NC NC DQ9 DQ10 VSSQ VCCQ DQ11 DQ12 VCC VCC NC VSS DQ13 DQ14 VCCQ VSSQ DQ15 DQ16 DQP2 NC VSSQ VCCQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1298A/GVT7164C18 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A10 NC NC VCCQ VSSQ NC DQP1 DQ8 DQ7 VSSQ VCCQ DQ6 DQ5 VSS NC VCC ZZ DQ4 DQ3 VCCQ VSSQ DQ2 DQ1 NC NC VSSQ VCCQ NC NC NC Pin Descriptions QFP Pins 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 80, 48, 47, 46, 45, 44 93, 94 Pin Name A0–A15 Type Description InputAddresses: These inputs are registered and must meet the set-up and hold Synchronous times around the rising edge of CLK. The burst counter generates internal addresses associated with A0 and A1, during burst cycle and wait cycle. InputByte Write Enables: A byte write enable is LOW for a Write cycle and HIGH Synchronous for a Read cycle. WEL controls DQ1–DQ8 and DQP1. WEH controls DQ9–DQ16 and DQP2. Data I/O are high-impedance if either of these inputs are LOW, conditioned by BWE being LOW. InputWrite Enable: This active LOW input gates byte write operations and must Synchronous meet the set-up and hold times around the rising edge of CLK. InputGlobal Write: This active LOW input allows a full 18-bit Write to occur indeSynchronous pendent of the BWE and WEn lines and must meet the set-up and hold times around the rising edge of CLK. InputClock: This signal registers the addresses, data, chip enables, write control Synchronous and burst control inputs on its rising edge. All synchronous inputs must meet set-up and hold times around the clock’s rising edge. InputChip Enable: This active LOW input is used to enable the device and to gate Synchronous ADSP. InputChip Enable: This active LOW input is used to enable the device. Synchronous InputChip Enable: This active HIGH input is used to enable the device. Synchronous Page 3 of 12 WEL, WEH 87 88 BWE GW 89 CLK 98 92 97 CE CE2 CE2 Document #: 38-05194 Rev. *A MODE A5 A4 A3 A2 A1 A0 NC NC VSS VCC NC NC A15 A14 A13 A12 A11 NC NC 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CY7C1298A/ GVT7164C18 Pin Descriptions (continued) QFP Pins 86 83 84 Pin Name OE ADV ADSP Type Input Description Output Enable: This active LOW asynchronous input enables the data output drivers. InputAddress Advance: This active LOW input is used to control the internal burst Synchronous counter. A HIGH on this pin generates wait cycle (no address advance). InputAddress Status Processor: This active LOW input, along with CE being Synchronous LOW, causes a new external address to be registered and a Read cycle is initiated using the new address. InputAddress Status Controller: This active LOW input causes device to be deSynchronous selected or selected along with new external address to be registered. A Read or Write cycle is initiated depending upon write control inputs. InputStatic InputStatic Input/ Output Input/ Output Supply Ground I/O Supply I/O Ground Mode: This input selects the burst sequence. A LOW on this pin selects Linear Burst. A NC or HIGH on this pin selects Interleaved Burst. Snooze: LOW or NC for normal operation. HIGH for low-power standby. Data Inputs/Outputs: Low Byte is DQ1–DQ8. HIgh Byte is DQ9–DQ16. Input data must meet set-up and hold times around the rising edge of CLK. Parity Inputs/Outputs: DQP1 is parity bit for DQ1–DQ8 and DQP2 is parity bit for DQ9–DQ16. Power Supply: +3.3V –5% and +10%. Ground: GND. Output Buffer Supply: +3.3V –5% and +10%. Output Buffer Ground: GND. No Connect: These signals are not internally connected. 85 ADSC 31 64 MODE ZZ 58, 59, 62, 63, 68, 69, DQ1–DQ16 72, 73, 8, 9, 12, 13, 18, 19, 22, 23 74, 24 14, 15, 41, 65, 91 17, 40, 67, 90 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 21, 26, 55, 60, 71, 76 1–3, 6, 7, 16, 25, 28–30, 38, 39, 42, 43, 49–53, 56, 57, 66, 75, 78–79, 95, 96 DQP1, DQP2 VCC VSS VCCQ VSSQ NC Burst Address Table (MODE = NC/VCC) First Address (external) A...A00 A...A01 A...A10 A...A11 Second Address (internal) A...A01 A...A00 A...A11 A...A10 Third Address (internal) A...A10 A...A11 A...A00 A...A01 Fourth Address (internal) A...A11 A...A10 A...A01 A...A00 Burst Address Table (MODE = GND) First Address (external) A...A00 A...A01 A...A10 A...A11 Second Address (internal) A...A01 A...A10 A...A11 A...A00 Third Address (internal) A...A10 A...A11 A...A00 A...A01 Fourth Address (internal) A...A11 A...A00 A...A01 A...A10 Partial Truth Table for Read/Write Function READ READ WRITE one byte WRITE all bytes WRITE all bytes GW H H H H L BWE H L L L X WEH X H L L X WEL X H H L X Document #: 38-05194 Rev. *A Page 4 of 12 CY7C1298A/ GVT7164C18 Truth Table[2, 3, 4, 5, 6, 7, 8] Operation Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst WRITE Cycle, Continue Burst WRITE Cycle, Continue Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst Address Used None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current CE H L L L L L L L L L X X H H X H X X H H X H CE2 CE2 ADSP X X H X H L L L L L X X X X X X X X X X X X X L X L X H H H H H X X X X X X X X X X X X X L L H H L L H H H H H X X H X H H X X H X ADSC L X X L L X X L L L H H H H H H H H H H H H ADV X X X X X X X X X X L L L L L L H H H H H H WRITE X X X X X X X L H H H H H H L L H H H H L L OE X X X X X L H X L H L H L H X X L H L H X X CLK L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H DQ High-Z High-Z High-Z High-Z High-Z Q High-Z D Q High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z D D Pass-Through Truth Table Previous Cycle[9] Operation Initiate WRITE cycle, all bytes Address = A(n–1), data = D(n–1) Initiate WRITE cycle, all bytes Address = A(n–1), data = D(n–1) Initiate WRITE cycle, all bytes Address = A(n–1), data = D(n–1) Initiate WRITE cycle, one byte Address = A(n–1), data = D(n–1) BWn All L [10, 11] Present Cycle Operation Initiate READ cycle Register A(n), Q = D(n–1) No new cycle Q = D(n–1) No new cycle Q = High-Z No new cycle Q = D(n–1) for one byte CE L H H H BWn H H H H OE L L H L Next Cycle Operation Read D(n) No carry-over from previous cycle No carry-over from previous cycle No carry-over from previous cycle All L[10, 11] All L[10, 11] One L[10] Notes: 2. X means “don’t care.” H means logic HIGH. L means logic LOW. WRITE = L means [BWE + WEL*WEH]*GW equals LOW. WRITE = H means [BWE + WEL*WEH]*GW equals HIGH. 3. WEL enables write to DQ1–DQ8 and DQP1. WEH enables write to DQ9–DQ16 and DQP2. 4. All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK. 5. Suspending burst generates wait cycle. 6. For a write operation following a read operation, OE must be HIGH before the input data required set-up time plus High-Z time for OE and staying HIGH throughout the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP LOW along with chip being selected always initiates a READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW for the CLK L-H edge of the subsequent wait cycle. Refer to Write timing diagram for clarification. 9. Previous cycle may be any cycle (non-burst, burst, or wait). 10. BWE is LOW for individual byte WRITE. 11. GW LOW yields the same result for all-byte WRITE operation. Document #: 38-05194 Rev. *A Page 5 of 12 CY7C1298A/ GVT7164C18 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Voltage on VCC Supply Relative to VSS ......... –0.5V to +4.6V VIN ...................................................................... –0.5V to 6V Storage Temperature (plastic) .......................–55°C to +150° Junction Temperature ..................................................+150° Range Com’l Power Dissipation.......................................................... 1.6W Short Circuit Output Current...................................... 100 mA Operating Range Ambient Temperature[12] 0°C to +70°C VCC[13,14] 3.3V −5%/+10% Electrical Characteristics Over the Operating Range Parameter VIH VIl ILI ILO VOH VOL VCC Description Input High (Logic 1) Voltage Input Leakage Current Output High Voltage Supply Voltage [15] [17] [15, 16] Test Conditions Min. 2.0 –0.3 Max. VCCQ + 0.3 0.8 2 2 0.4 Unit V V µA µA V V V 50 MHz -8 225 Input Low (Logic 0) Voltage[15, 16] 0V < VIN < VCC Output(s) disabled, 0V < VOUT < VCC IOH = –4.0 mA IOL = 8.0 mA Output Leakage Current [15, 18] –2 –2 2.4 3.1 100 MHz -5 360 83 MHz -6 315 Output Low Voltage[15, 18] 3.6 66 MHz -7 270 Parameter ICC Description Power Supply Current: Operating[19, 20, 21] Power Supply Current: Idle[20, 21] Conditions Device selected; all inputs < VILor > VIH; cycle time > tKC min.; VCC = Max.; outputs open Device selected; ADSC, ADSP, ADV, GW, BWE >VIH; all other inputs < VILor > VIH; VCC = Max.; cycle time > tKC min.; outputs open Typ. 180 Unit mA ISB1 30 60 55 50 45 mA ISB2 CMOS Standby[20, 21] Device deselected; VCC = Max.; all inputs < VSS + 0.2 or >VCC – 0.2; all inputs static; CLK frequency = 0 TTL Standby[20, 21] Device deselected; all inputs < VIL or > VIH; all inputs static; VCC = Max.; CLK frequency = 0 Device deselected; all inputs < VIL or > VIH; VCC = Max.; CLK cycle time > tKC min. 0.2 2 2 2 2 mA ISB3 8 18 18 18 18 mA ISB4 Clock Running[20, 21] 30 60 55 50 45 mA Capacitance[22] Parameter CI CO Description Input Capacitance Input/Output Capacitance (DQ) Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Typ. 3 6 Max. 4 7 Unit pF pF Notes: 12. TA is the case temperature. 13. Please refer to waveform (d) 14. Power Supply ramp-up should be monotonic. 15. All voltages referenced to VSS (GND). 16. Overshoot: VIH ≤ +6.0V for t ≤ tKC /2. Undershoot:VIL ≤ –2.0V for t ≤ tKC /2 17. MODE pin has an internal pull-up and ZZ pin has an internal pull-down. These two pins exhibit an input leakage current of ±30 µA. 18. AC I/O curves are available upon request. 19. ICC is given with no output current. ICC increases with greater output loading and faster cycle times. 20. “Device Deselected” means the device is in Power-Down mode as defined in the truth table. “Device Selected” means the device is active. 21. Typical values are measured at 3.3V, 25°C, and20-ns cycle time. 22. This parameter is sampled. Document #: 38-05194 Rev. *A Page 6 of 12 CY7C1298A/ GVT7164C18 Thermal Resistance Description Test Conditions Symbol ΘJA ΘJC TQFP Typ. 20 1 Unit °C/W °C/W Thermal Resistance (Junction to Ambient) Still Air, soldered on a 4.25 x 1.125 inch, 4-layer PCB Thermal Resistance (Junction to Case) AC Test Loads and Waveforms[23] +3.3v ALL INPUT PULSES 3.0V 10% 0V ≤ 1.5 ns 90% 90% 10% ≤ 1.5 ns V c c ty p V c c m in t PU = 20 0u s DQ Z0 = 50Ω 50Ω Vt = 1.5V 30 pF DQ 351Ω 317Ω 5 pF F or prope r R E S E T bring V c c dow n t o 0 V (a) (b) (c) (d) Capacitance Derating[23] Description Clock to output valid Symbol ∆ KQ t Typ. 0.016 Max. Unit ns / pF Switching Characteristics Over the Operating Range[25] 100 MHz -5 Parameter Clock tKC tKH tKL Output Times tKQ tKQX tKQLZ tKQHZ tOEQ tOELZ tOEHZ Set-up Times tS Hold Times tH Address, Controls, and Data In[29] 0.5 0.5 0.5 0.5 ns Notes: 23. Overshoot: VIH(AC)