CY7C1325G
4-Mbit (256K x 18) Flow-Through Sync SRAM
Functional Description[1]
Features
• 256K x 18 common I/O
• 3.3V core power supply (VDD)
• 2.5V or 3.3V I/O power supply (VDDQ)
• Fast clock-to-output times
— 6.5 ns (133-MHz version)
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting Intel®
Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Available in lead-free 100-Pin TQFP package, lead-free
and non-lead-free 119-Ball BGA package
• “ZZ” Sleep Mode option
The CY7C1325G is a 256 K x 18 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE1), depth-expansion Chip Enables (CE2 and CE3), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW[A:B], and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
The CY7C1325G allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects
an interleaved burst sequence, while a LOW selects a linear
burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP) or the cache Controller
Address Strobe (ADSC) inputs.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
The CY7C1325G operates from a +3.3V core power supply
while all outputs may operate with either a +2.5 or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Logic Block Diagram
A0,A1,A
ADDRESS
REGISTER
A[1:0]
MODE
BURST Q1
COUNTER AND
LOGIC
CLR
Q0
ADV
CLK
ADSC
ADSP
BWB
BWA
DQB,DQPB
WRITE DRIVER
DQB,DQPB
WRITE REGISTER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQA,DQPA
WRITE DRIVER
DQA,DQPA
WRITE REGISTER
DQs
DQPA
DQPB
BWE
GW
CE1
CE2
CE3
INPUT
REGISTERS
ENABLE
REGISTER
OE
ZZ
SLEEP
CONTROL
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05518 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 4, 2006
[+] Feedback
CY7C1325G
Selection Guide
133 MHz
100 MHz
Unit
Maximum Access Time
6.5
8.0
ns
Maximum Operating Current
225
205
mA
Maximum Standby Current
40
40
mA
Pin Configurations
Document #: 38-05518 Rev. *D
A
45
46
47
48
49
50
A
A
A
A
A
44
NC/9M
A
A
43
41
42
40
VSS
VDD
NC/18M
37
A0
39
36
A1
38
35
A
NC/72M
NC/36M
34
A
81
82
83
84
BWE
OE
ADSC
ADSP
ADV
A
85
86
GW
89
87
CLK
91
88
VDD
VSS
93
90
BWA
CE3
94
92
NC
BWB
95
CE2
NC
96
98
97
A
CE1
99
A
31
VSS
VDDQ
NC
NC
NC
33
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CY7C1325G
A
BYTE B
DQB
DQB
VSS
VDDQ
DQB
DQB
NC
VDD
NC
32
VDDQ
VSS
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
NC
NC
NC
100
100-Pin TQFP Pinout
A
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
BYTE A
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
NC
NC
Page 2 of 16
[+] Feedback
CY7C1325G
Pin Configurations (continued)
119-Ball BGA Pinout
1
2
3
4
5
6
7
A
VDDQ
A
A
ADSP
A
A
VDDQ
B
C
NC/288M
NC/144M
CE2
A
A
A
ADSC
VDD
A
A
CE3
A
NC/576M
NC/1G
D
DQB
NC
VSS
NC
VSS
DQPA
NC
E
F
NC
VDDQ
DQB
NC
VSS
VSS
CE1
OE
VSS
VSS
NC
DQA
DQA
VDDQ
G
H
J
NC
DQB
VDDQ
DQB
NC
VDD
BWB
VSS
NC
ADV
GW
VDD
VSS
VSS
NC
NC
DQA
VDD
DQA
NC
VDDQ
K
NC
DQB
VSS
CLK
VSS
NC
DQA
L
DQB
NC
VSS
NC
BWA
DQA
NC
M
N
VDDQ
DQB
DQB
NC
VSS
VSS
BWE
A1
VSS
VSS
NC
DQA
VDDQ
NC
P
NC
DQPB
VSS
A0
VSS
NC
DQA
R
T
NC
NC/72M
A
MODE
VDD
A
NC/36M
NC
A
A
A
A
NC
ZZ
U
VDDQ
NC
NC
NC
NC
NC
VDDQ
Pin Definitions
Name
I/O
Description
A0, A1, A
InputAddress Inputs used to select one of the 256K address locations. Sampled at the rising edge
Synchronous of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0]
feed the 2-bit counter.
BWA,BWB
InputByte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Synchronous Sampled on the rising edge of CLK.
GW
InputGlobal Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a
Synchronous global write is conducted (ALL bytes are written, regardless of the values on BW[A:B] and BWE).
BWE
InputByte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
Synchronous asserted LOW to conduct a byte write.
CLK
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a burst operation.
CE1
InputChip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only
when a new external address is loaded.
CE2
InputChip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external address
is loaded.
CE3
InputChip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE1 and CE2 to select/deselect the device. CE3 is sampled only when a new external address
is loaded.
OE
InputOutput Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
Asynchronous LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act
as input data pins. OE is masked during the first clock of a read cycle when emerging from a
deselected state.
Document #: 38-05518 Rev. *D
Page 3 of 16
[+] Feedback
CY7C1325G
Pin Definitions (continued)
Name
I/O
Description
ADV
InputAdvance Input signal, sampled on the rising edge of CLK. When asserted, it automatically
Synchronous increments the address in a burst cycle.
ADSP
InputAddress Strobe from Processor, sampled on the rising edge of CLK, active LOW. When
Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A[1:0]
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC
InputAddress Strobe from Controller, sampled on the rising edge of CLK, active LOW. When
Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A[1:0]
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized.
ZZ
InputZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical
Asynchronous “sleep” condition with data integrity preserved.During normal operation, this pin has to be low or
left floating. ZZ pin has an internal pull-down.
DQs
DQPA, DQPB
I/OBidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
Synchronous by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs.
When HIGH, DQs and DQP[A:B] are placed in a tri-state condition.
VDD
Power Supply Power supply inputs to the core of the device.
VSS
Ground
Ground for the core of the device.
VDDQ
I/O Power
Supply
Power supply for the I/O circuitry.
MODE
InputStatic
NC
NC/9M,
NC/18M
NC/36M
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left
floating selects interleaved burst sequence. This is a strap pin and should remain static during
device operation. Mode Pin has an internal pull-up.
No Connects. Not Internally connected to the die.
–
No Connects. Not internally connected to the die. NC/9M, NC/18M, NC/36M, NC/72M,
NC/144M, NC/288M, NC/576M and NC/1G are address expansion pins that are not internally
connected to the die.
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (t CDV) is 6.5 ns (133-MHz device).
The CY7C1325G supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is
user-selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the Processor
Address Strobe (ADSP) or the Controller Address Strobe
(ADSC). Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[A:B]) inputs. A Global Write
Document #: 38-05518 Rev. *D
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1
is HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all
asserted active, and (2) ADSP or ADSC is asserted LOW (if
the access is initiated by ADSC, the write inputs must be
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter/control logic and presented to the memory core.
If the OE input is asserted LOW, the requested data will be
available at the data outputs a maximum to tCDV after clock
rise. ADSP is ignored if CE1 is HIGH.
Page 4 of 16
[+] Feedback
CY7C1325G
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted
active, and (2) ADSP is asserted LOW. The addresses
presented are loaded into the address register and the burst
inputs (GW, BWE, and BW[A:B]) are ignored during this first
clock cycle. If the write inputs are asserted active (see Write
Cycle Descriptions table for appropriate states that indicate a
write) on the next clock rise, the appropriate data will be
latched and written into the device. Byte writes are allowed.
During byte writes, BWA controls DQA and BWB controls DQB.
All I/Os are tri-stated during a byte write.Since this is a
common I/O device, the asynchronous OE input signal must
be deasserted and the I/Os must be tri-stated prior to the
presentation of data to DQs. As a safety precaution, the data
lines are tri-stated once a write cycle is detected, regardless
of the state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BW[A:B])
indicate a write access. ADSC is ignored if ADSP is active
LOW.
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the
memory core. The information presented to DQ[A:D] will be
written into the specified address location. Byte writes are
allowed. During byte writes, BWA controls DQA, BWB controls
DQB. All I/Os are tri-stated when a write is detected, even a
byte write. Since this is a common I/O device, the
asynchronous OE input signal must be deasserted and the
I/Os must be tri-stated prior to the presentation of data to DQs.
As a safety precaution, the data lines are tri-stated once a write
cycle is detected, regardless of the state of OE.
A[1:0], and can follow either a linear or interleaved burst order.
The burst order is determined by the state of the MODE input.
A LOW on MODE will select a linear burst sequence. A HIGH
on MODE will select an interleaved burst order. Leaving
MODE unconnected will cause the device to default to a interleaved burst sequence.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LOW.
.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
Burst Sequences
01
10
11
00
The CY7C1325G provides an on-chip two-bit wraparound
burst counter inside the SRAM. The burst counter is fed by
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
IDDZZ
Sleep mode standby current
ZZ > VDD – 0.2V
tZZS
Device operation to ZZ
ZZ > VDD – 0.2V
tZZREC
ZZ recovery time
ZZ < 0.2V
tZZI
ZZ Active to sleep current
This parameter is sampled
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
Document #: 38-05518 Rev. *D
Min.
Max.
Unit
40
mA
2tCYC
ns
2tCYC
ns
2tCYC
0
ns
ns
Page 5 of 16
[+] Feedback
CY7C1325G
Truth Table[2, 3, 4, 5, 6]
Address
Used
Cycle Description
CE1 CE2 CE3
ZZ
ADSP
ADSC
ADV WRITE
OE
CLK
DQ
Deselected Cycle,
Power-down
None
H
X
X
L
X
L
X
X
X
L-H
Tri-State
Deselected Cycle,
Power-down
None
L
L
X
L
L
X
X
X
X
L-H
Tri-State
Deselected Cycle,
Power-down
None
L
X
H
L
L
X
X
X
X
L-H
Tri-State
Deselected Cycle,
Power-down
None
L
L
X
L
H
L
X
X
X
L-H
Tri-State
Deselected Cycle,
Power-down
None
X
X
X
L
H
L
X
X
X
L-H
Tri-State
Sleep Mode, Power-down
None
X
X
X
H
X
X
X
X
X
X
Tri-State
Read Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
L
L-H
Q
Read Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
H
L-H
Tri-State
Write Cycle, Begin Burst
External
L
H
L
L
H
L
X
L
X
L-H
D
Read Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
L
L-H
Q
Read Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
H
L-H
Tri-State
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L-H
Tri-State
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L-H
Tri-State
Write Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L-H
D
Write Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L-H
D
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L-H
Tri-State
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L-H
Tri-State
Write Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L-H
D
Write Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L-H
D
Truth Table for Read/Write[2]
GW
BWE
BWB
BWA
Read
Function
H
H
X
X
Read
H
L
H
H
Write Byte A – (DQA and DQPA)
H
L
H
L
Write Byte B – (DQB and DQPB)
H
L
L
H
Write All Bytes
H
L
L
L
Write All Bytes
L
X
X
X
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals (BWA, BWB) and BWE = L or GW = L. WRITE = H when all Byte write enable signals (BWA, BWB),
BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: B]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05518 Rev. *D
Page 6 of 16
[+] Feedback
CY7C1325G
Maximum Ratings
DC Input Voltage ................................... –0.5V to VDD + 0.5V
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ................................. –65°C to +150°C
Latch-up Current.................................................... > 200 mA
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Operating Range
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
Ambient
Temperature]
Supply Voltage on VDDQ Relative to GND ...... –0.5V to +VDD
Range
DC Voltage Applied to Outputs
in tri-state ............................................ –0.5V to VDDQ + 0.5V
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
Electrical Characteristics Over the Operating Range
Parameter
Description
VDD
Power Supply Voltage
VDD
VDDQ
3.3V −5%/+10% 2.5V –5%
to VDD
[7, 8]
Test Conditions
Min.
Max.
Unit
3.135
3.6
V
2.375
VDD
VDDQ
I/O Supply Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
for 3.3V I/O
VIL
Input LOW Voltage[7]
for 2.5V I/O
IX
Input Leakage Current
except ZZ and MODE
GND ≤ VI ≤ VDDQ
Input Current of MODE
Input = VSS
–30
Input Current of ZZ
Input = VSS
for 3.3V I/O, IOH = –4.0 mA
2.4
for 2.5V I/O, IOH = –1.0 mA
2.0
for 3.3V I/O, IOL = 8.0 mA
for 2.5V I/O, IOL = 1.0 mA
V
V
V
0.4
V
0.4
V
2.0
VDD + 0.3V
V
for 2.5V I/O
1.7
VDD + 0.3V
V
for 3.3V I/O
–0.3
0.8
V
–0.3
0.7
V
−5
5
µA
Input = VDD
µA
5
Input = VDD
µA
µA
–5
30
µA
5
µA
IOZ
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
IDD
VDD Operating Supply
Current
VDD = Max., IOUT = 0 mA,
f = fMAX= 1/tCYC
7.5-ns cycle, 133 MHz
225
mA
10-ns cycle, 100 MHz
205
mA
Automatic CE
Power-Down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = fMAX,
inputs switching
7.5-ns cycle, 133 MHz
90
mA
10-ns cycle, 100 MHz
80
mA
ISB2
Automatic CE
Power-Down
Current—CMOS Inputs
Max. VDD, Device Deselected, All speeds
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
40
mA
ISB3
Automatic CE
Power-down
Current—CMOS Inputs
Max. VDD, Device Deselected,
VIN ≥ VDDQ – 0.3V or
VIN ≤ 0.3V,
f = fMAX, inputs switching
Automatic CE
Power-down
Current—TTL Inputs
Max. VDD, Device Deselected, All speeds
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
ISB1
ISB4
–5
7.5-ns cycle, 133 MHz
75
mA
10-ns cycle, 100 MHz
65
mA
45
mA
Notes:
7. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).
8. TPower-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document #: 38-05518 Rev. *D
Page 7 of 16
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CY7C1325G
Capacitance[9]
Parameter
Description
Test Conditions
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CI/O
Input/Output Capacitance
100 TQFP
Max.
119 BGA
Max.
Unit
5
5
pF
5
5
pF
5
7
pF
100 TQFP
Package
119 BGA
Package
Unit
30.32
34.1
°C/W
6.85
14.0
°C/W
TA = 25°C, f = 1 MHz,
VDD = 3.3V, VDDQ = 3.3V
Thermal Resistance[9]
Parameter
Description
Test Conditions
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test conditions follow standard test
methods and procedures for
measuring thermal impedance, per
EIA/JESD51.
AC Test Loads and Waveforms
3.3V I/O Test Load
3.3V
OUTPUT
R = 317Ω
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50Ω
Z0 = 50Ω
VT = 1.5V
(a)
5 pF
INCLUDING
JIG AND
SCOPE
2.5V I/O Test Load
2.5V
OUTPUT
10%
GND
R = 351Ω
VT = 1.25V
(a)
5 pF
INCLUDING
JIG AND
SCOPE
≤ 1 ns
≤ 1 ns
(b)
(c)
R = 1667Ω
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50Ω
Z0 = 50Ω
90%
10%
90%
10%
90%
10%
90%
GND
R = 1538Ω
(b)
≤ 1 ns
≤ 1 ns
(c)
Note:
9. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05518 Rev. *D
Page 8 of 16
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CY7C1325G
Switching Characteristics Over the Operating Range [14, 15]
–133
Parameter
tPOWER
Description
[10]
VDD(Typical) to the first Access
Min.
–100
Max.
Min.
Max.
Unit
1
1
ms
Clock
tCYC
Clock Cycle Time
7.5
10
ns
tCH
Clock HIGH
2.5
4.0
ns
tCL
Clock LOW
2.5
4.0
ns
Output Times
tCDV
Data Output Valid After CLK Rise
tDOH
Data Output Hold After CLK Rise
[11, 12, 13]
6.5
2.0
8.0
2.0
ns
tCLZ
Clock to Low-Z
tCHZ
Clock to High-Z[11, 12, 13]
3.5
3.5
ns
tOEV
OE LOW to Output Valid
3.5
3.5
ns
tOELZ
tOEHZ
OE LOW to Output
Low-Z[11, 12, 13]
OE HIGH to Output
High-Z[11, 12, 13]
0
ns
0
0
ns
0
3.5
ns
3.5
ns
Set-up Times
tAS
Address Set-up Before CLK Rise
1.5
2.0
ns
tADS
ADSP, ADSC Set-up Before CLK Rise
1.5
2.0
ns
tADVS
ADV Set-up Before CLK Rise
1.5
2.0
ns
tWES
GW, BWE, BWX Set-up Before CLK Rise
1.5
2.0
ns
tDS
Data Input Set-up Before CLK Rise
1.5
2.0
ns
tCES
Chip Enable Set-up
1.5
2.0
ns
tAH
Address Hold After CLK Rise
0.5
0.5
ns
tADH
ADSP, ADSC Hold After CLK Rise
0.5
0.5
ns
tWEH
GW, BWE, BWX Hold After CLK Rise
0.5
0.5
ns
tADVH
ADV Hold After CLK Rise
0.5
0.5
ns
tDH
Data Input Hold After CLK Rise
0.5
0.5
ns
tCEH
Chip Enable Hold After CLK Rise
0.5
0.5
ns
Hold Times
Notes:
10. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation
can be initiated.
11. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
12. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
13. This parameter is sampled and not 100% tested.
14. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
15. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05518 Rev. *D
Page 9 of 16
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CY7C1325G
Timing Diagrams
Read Cycle Timing[16]
tCYC
CLK
t
tADS
t CL
CH
tADH
ADSP
tADS
tADH
ADSC
tAS
tAH
A1
ADDRESS
A2
t
WES
t
WEH
GW, BWE,BW
[A:B]
tCES
Deselect Cycle
t CEH
CE
t
ADVS
t
ADVH
ADV
ADV suspends burst
OE
t OEV
t OEHZ
t CLZ
Data Out (Q)
High-Z
Q(A1)
t OELZ
tCDV
t CHZ
tDOH
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
t CDV
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
Note:
16. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document #: 38-05518 Rev. *D
Page 10 of 16
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CY7C1325G
Timing Diagrams (continued)
Write Cycle Timing[16, 17]
t CYC
CLK
t
tADS
t
CH
CL
tADH
ADSP
tADS
ADSC extends burst
tADH
tADS
tADH
ADSC
tAS
tAH
A1
ADDRESS
A2
A3
Byte write signals are ignored for first cycle when
ADSP initiates burst
tWES tWEH
BWE,
BW[A:B]
t
t
WES WEH
GW
tCES
tCEH
CE
tADVS tADVH
ADV
ADV suspends burst
OE
t
Data in (D)
High-Z
t
OEHZ
DS
t
DH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Note:
17. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:B] LOW.
Document #: 38-05518 Rev. *D
Page 11 of 16
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CY7C1325G
Timing Diagrams (continued)
Read/Write Timing[16, 18, 19]
tCYC
CLK
t
CH
tADS
tADH
tAS
tAH
t
CL
ADSP
ADSC
ADDRESS
A1
A2
A3
A4
A5
A6
D(A5)
D(A6)
t
t
WES WEH
BWE, BW[A:B]
tCES
tCEH
CE
ADV
OE
tDS
Data In (D)
Data Out (Q)
High-Z
t
OEHZ
Q(A1)
tDH
tOELZ
D(A3)
tCDV
Q(A2)
Back-to-Back READs
Q(A4)
Single WRITE
Q(A4+1)
Q(A4+2)
BURST READ
DON’T CARE
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Notes:
18. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
19. GW is HIGH.
Document #: 38-05518 Rev. *D
Page 12 of 16
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CY7C1325G
Timing Diagrams (continued)
ZZ Mode Timing[20, 21]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes:
20. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
21. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05518 Rev. *D
Page 13 of 16
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CY7C1325G
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz)
133
Package
Diagram
Ordering Code
CY7C1325G-133AXC
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
CY7C1325G-133BGC
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1325G-133BGXC
Commercial
119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1325G-133AXI
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
CY7C1325G-133BGI
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1325G-133BGXI
100
Operating
Range
Part and Package Type
lndustrial
119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1325G-100AXC
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
CY7C1325G-100BGC
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1325G-100BGXC
Commercial
119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1325G-100AXI
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
CY7C1325G-100BGI
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1325G-100BGXI
lndustrial
119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
Package Diagrams
100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050)
16.00±0.20
1.40±0.05
14.00±0.10
81
100
80
1
20.00±0.10
22.00±0.20
0.30±0.08
0.65
TYP.
30
12°±1°
(8X)
SEE DETAIL
A
51
31
50
0.20 MAX.
0.10
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
0.25
NOTE:
1. JEDEC STD REF MS-026
GAUGE PLANE
0°-7°
R 0.08 MIN.
0.20 MAX.
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0.60±0.15
0.20 MIN.
51-85050-*B
1.00 REF.
DETAIL
Document #: 38-05518 Rev. *D
A
Page 14 of 16
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CY7C1325G
Package Diagrams (continued)
119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.75±0.15(119X)
Ø1.00(3X) REF.
1
2
3 4
5
6
7
7
6
5
4 3 2 1
A
A
B
B
C
D
1.27
C
D
E
E
F
F
H
19.50
J
K
L
20.32
G
H
22.00±0.20
G
J
K
L
M
10.16
M
N
P
N
P
R
R
T
T
U
U
1.27
0.70 REF.
A
3.81
7.62
30° TYP.
14.00±0.20
0.15(4X)
0.15 C
2.40 MAX.
B
0.90±0.05
0.25 C
12.00
51-85115-*B
C
60±0.10
0.56
SEATING PLANE
Intel and Pentium are registered trademarks and i486 is a trademark of Intel Corporation. All product and company names
mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05518 Rev. *D
Page 15 of 16
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1325G
Document History Page
Document Title: CY7C1325G 4-Mbit (256K x 18) Flow-Through Sync SRAM
Document Number: 38-05518
REV.
Orig. of
ECN NO. Issue Date Change
Description of Change
**
224366
See ECN
RKF
New data sheet
*A
283775
See ECN
VBL
Deleted 66 MHz
Changed TQFP package to lead-free TQFP in Ordering Information section
Added BG lead-free package
*B
333626
See ECN
SYT
Removed 117 MHz speed bin
Modified Address Expansion balls in the pinouts for 100 TQFP and 119 BGA
Packages as per JEDEC standards and updated the Pin Definitions accordingly
Modified VOL, VOH test conditions
Replaced ‘Snooze’ with ‘Sleep’
Replaced TBD’s for ΘJA and ΘJC to their respective values on the Thermal Resistance table
Changed the package name for 100 TQFP from A100RA to A101
Removed comment on the availability of BG lead-free package
Updated the Ordering Information by shading and unshading MPNs as per
availability
*C
418633
See ECN
RXU
Converted From Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901
North First Street” to “198 Champion Court”
Modified test condition in Footnote from VDDQ < VDD to VDDQ < VDD
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table.
Replaced Package Name column with Package Diagram in the Ordering Information table
Replaced Package Diagram of 51-85050 from *A to *B
Updated the Ordering Information
*D
480124
See ECN
VKN
Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND.
Updated the Ordering Information table.
Document #: 38-05518 Rev. *D
Page 16 of 16
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