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CY7C1353G
4-Mbit (256K × 18) Flow-Through SRAM
with NoBL™ Architecture
4-Mbit (256K × 18) Flow-Through SRAM with NoBL™ Architecture
Features
Functional Description
■
Supports up to 100-MHz bus operations with zero wait states
❐ Data is transferred on every clock
The CY7C1353G is a 3.3 V, 256K × 18 synchronous
flow-through burst SRAM designed specifically to support
unlimited true back-to-back read/write operations without the
insertion of wait states. The CY7C1353G is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to enable
consecutive read/write operations with data being transferred on
every clock cycle. This feature dramatically improves the
throughput of data through the SRAM, especially in systems that
require frequent write-read transitions.
■
Pin compatible and functionally equivalent to ZBT™ devices
■
Internally self timed output buffer control to eliminate the need
to use OE
■
Registered inputs for flow-through operation
■
Byte write capability
■
256K × 18 common I/O architecture
■
2.5 V/3.3 V I/O power supply (VDDQ)
■
Fast clock-to-output times
❐ 8.0 ns (for 100 MHz device)
■
Clock enable (CEN) pin to suspend operation
■
Synchronous self timed writes
■
Asynchronous output enable
■
Available in Pb-free 100-pin TQFP package
■
Burst capability – linear or interleaved burst order
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
■
Low standby power
For a complete list of related documentation, click here.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
clock enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 8.0 ns (100 MHz device).
Write operations are controlled by the two byte write select
(BW[A:B]) and a write enable (WE) input. All writes are conducted
with on-chip synchronous self timed write circuitry.
Logic Block Diagram
ADDRESS
REGISTER
A0, A1, A
A1
D1
A0
D0
MODE
CLK
CEN
C
CE
ADV/LD
C
BURST
LOGIC
Q1 A1'
A0'
Q0
WRITE ADDRESS
REGISTER
ADV/LD
BWA
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BWB
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
WE
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQPA
DQPB
E
INPUT E
REGISTER
OE
CE1
CE2
CE3
ZZ
READ LOGIC
SLEEP
CONTROL
Errata: For information on silicon errata, see Errata on page 16. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 38-05515 Rev. *R
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 25, 2019
CY7C1353G
Contents
Selection Guide ................................................................ 3
Pin Configuration ............................................................. 3
Pin Definitions .................................................................. 4
Functional Overview ........................................................ 5
Single Read Accesses ................................................ 5
Burst Read Accesses .................................................. 5
Single Write Accesses ................................................. 5
Burst Write Accesses .................................................. 6
Sleep Mode ................................................................. 6
Linear Burst Address Table ......................................... 6
Interleaved Burst Address Table ................................. 6
ZZ Mode Electrical Characteristics .............................. 6
Truth Table ........................................................................ 7
Partial Truth Table for Read/Write .................................. 7
Maximum Ratings ............................................................. 8
Operating Range ............................................................... 8
Electrical Characteristics ................................................. 8
Capacitance ...................................................................... 9
Thermal Resistance .......................................................... 9
AC Test Loads and Waveforms ....................................... 9
Document Number: 38-05515 Rev. *R
Switching Characteristics .............................................. 10
Switching Waveforms .................................................... 11
Ordering Information ...................................................... 13
Ordering Code Definitions ......................................... 13
Package Diagram ............................................................ 14
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Errata ............................................................................... 16
Part Numbers Affected .............................................. 16
Product Status ........................................................... 16
Ram9 NoBL ZZ Pin Issues Errata Summary ............. 16
Document History Page ................................................. 17
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC® Solutions ...................................................... 19
Cypress Developer Community ................................. 19
Technical Support ..................................................... 19
Page 2 of 19
CY7C1353G
Selection Guide
Description
100 MHz
8.0
Unit
ns
Maximum operating current
205
mA
Maximum CMOS standby current
40
mA
Maximum access time
Pin Configuration
1
VDDQ
VSS
NC
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
4
5
6
7
8
9
WE
CEN
OE
87
86
A
CLK
88
81
VSS
89
NC/9M
VDD
90
A
CE3
91
82
BWA
92
83
BWB
94
93
ADV/LD
NC
95
NC/18M
NC
96
84
CE2
97
85
A
CE1
98
A
99
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
2
3
10
11
12
13
14
15
16
17
18
19
CY7C1353G
20
21
22
23
24
25
57
56
26
27
55
54
53
52
51
28
29
47
48
49
50
A
A
A
A
41
VDD
46
40
VSS
45
39
NC/144M
A
38
A
37
A0
NC/288M
44
36
A1
43
35
A
A
34
A
NC/36M
33
A
42
32
A
NC/72M
31
30
MODE
BYTE B
NC
NC
NC
100
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout [1]
A
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
BYTE A
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
NC
NC
Note
1. Errata: The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see Errata on page 16.
Document Number: 38-05515 Rev. *R
Page 3 of 19
CY7C1353G
Pin Definitions
Name
I/O
Description
A0, A1, A
InputAddress inputs used to select one of the 256K address locations. Sampled at the rising edge of the
synchronous CLK. A[1:0] are fed to the two-bit burst counter.
BW[A:B]
InputByte write inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising
synchronous edge of CLK.
WE
InputWrite enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal
synchronous must be asserted LOW to initiate a write sequence.
ADV/LD
InputAdvance/load input. Used to advance the on-chip address counter or load a new address. When HIGH
synchronous (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be
loaded into the device for an access. After being deselected, ADV/LD must be driven LOW to load a
new address.
CLK
Input-clock
Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
CE1
InputChip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2,
synchronous and CE3 to select/deselect the device.
CE2
InputChip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE3 to select/deselect the device.
CE3
InputChip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE2 to select/deselect the device.
OE
InputOutput enable, asynchronous input, active LOW. Combined with the synchronous logic block inside
asynchronous the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as
outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state, when
the device has been deselected.
CEN
InputClock enable input, active LOW. When asserted LOW the clock signal is recognized by the SRAM.
synchronous When deasserted HIGH the clock signal is masked. While deasserting CEN does not deselect the device,
CEN can be used to extend the previous cycle when required.
ZZ[2]
InputZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with
asynchronous data integrity preserved. During normal operation, this pin has to be low or left floating. ZZ pin has an
internal pull-down.
DQs
I/OBidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by
address during the clock rise of the read cycle. The direction of the pins is controlled by OE and the
internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQs and
DQP[A:B] are placed in a tri-state condition. The outputs are automatically tri-stated during the data
portion of a write sequence, during the first clock when emerging from a deselected state, and when the
device is deselected, regardless of the state of OE.
Note
2. Errata: The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see Errata on page 16.
Document Number: 38-05515 Rev. *R
Page 4 of 19
CY7C1353G
Pin Definitions (continued)
Name
I/O
Description
DQP[A:B]
I/OBidirectional data parity I/O lines. Functionally, these signals are identical to DQs. During write
synchronous sequences, DQP[A:B] is controlled by BWx correspondingly.
MODE
Input strap pin MODE input. Selects the burst order of the device.
When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved
burst sequence.
VDD
Power supply Power supply inputs to the core of the device.
VDDQ
VSS
NC, NC/9M,
NC/18M,
NC/36M,
NC/72M,
NC/144M,
NC/288M
I/O power
supply
Ground
–
Power supply for the I/O circuitry.
Ground for the device.
No Connects. Not internally connected to the die. NC/9M, NC/18M, NC/72M, NC/144M, NC/288M are
address expansion pins are not internally connected to the die.
Functional Overview
The CY7C1353G is a synchronous flow-through burst SRAM
designed specifically to eliminate wait states during write-read
transitions. All synchronous inputs pass through input registers
controlled by the rising edge of the clock. The clock signal is
qualified with the clock enable input signal (CEN). If CEN is
HIGH, the clock signal is not recognized and all internal states
are maintained. All synchronous operations are qualified with
CEN. Maximum access delay from the clock rise (tCDV) is 8.0 ns
(100-MHz device).
Accesses can be initiated by asserting all three chip enables
(CE1, CE2, CE3) active at the rising edge of the clock. If clock
enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device is latched. The access can
either be a read or write operation, depending on the status of
the write enable (WE). BW[A:B] can be used to conduct byte write
operations.
Write operations are qualified by the write enable (WE). All writes
are simplified with on-chip synchronous self timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipe lined. ADV/LD
must be driven LOW after the device has been deselected to
load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, (3) the write enable input signal
WE is deasserted HIGH, and 4) ADV/LD is asserted LOW. The
address presented to the address inputs is latched into the
address register and presented to the memory array and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the
output buffers. The data is available within 8.0 ns (100-MHz
device) provided OE is active LOW. After the first clock of the
read access, the output buffers are controlled by OE and the
internal control logic. OE must be driven LOW in order for the
Document Number: 38-05515 Rev. *R
device to drive out the requested data. On the subsequent clock,
another operation (read/write/deselect) can be initiated. When
the SRAM is deselected at clock rise by one of the chip enable
signals, its output is tri-stated immediately.
Burst Read Accesses
The CY7C1353G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to four
reads without reasserting the address inputs. ADV/LD must be
driven LOW to load a new address into the SRAM, as described
in the Single Read Accesses. The sequence of the burst counter
is determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved burst
sequence. Both burst counters use A0 and A1 in the burst
sequence, and wraps around when incremented sufficiently. A
HIGH input on ADV/LD increments the internal burst counter
regardless of the state of chip enable inputs or WE. WE is latched
at the beginning of a burst cycle. Therefore, the type of access
(read or write) is maintained throughout the burst sequence.
Single Write Accesses
Write access are initiated when these conditions are satisfied at
clock rise:
■
CEN is asserted LOW
■
CE1, CE2, and CE3 are all asserted active
■
The write signal WE is asserted LOW.
The address presented to the address bus is loaded into the
address register. The write signals are latched into the control
logic block. The data lines are automatically tri-stated regardless
of the state of the OE input signal. This allows the external logic
to present the data on DQs and DQP[A:B].
On the next clock rise the data presented to DQs and DQP[A:B]
(or a subset for byte write operations, see truth table for details)
inputs is latched into the device and the write is complete.
Additional accesses (read/write/deselect) can be initiated on this
cycle.
Page 5 of 19
CY7C1353G
The data written during the write operation is controlled by
BW[A:B] signals. The CY7C1353G provides byte write capability
that is described in the truth table. Asserting the write enable
input (WE) with the selected byte write select input selectively
writes to only the desired bytes. Bytes not selected during a byte
write operation remains unaltered. A synchronous self timed
write mechanism has been provided to simplify the write
operations. Byte write capability has been included to greatly
simplify read/modify/write sequences, which can be reduced to
simple byte write operations.
Because the CY7C1353G is a common I/O device, data must not
be driven into the device while the outputs are active. The output
enable (OE) can be deasserted HIGH before presenting data to
the DQs and DQP[A:B] inputs. Doing so tri-states the output
drivers. As a safety precaution, DQs and DQP[A:B].are
automatically tri-stated during the data portion of a write cycle,
regardless of the state of OE.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
Linear Burst Address Table
(MODE = GND)
Burst Write Accesses
The CY7C1353G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to four
write operations without reasserting the address inputs. ADV/LD
must be driven LOW to load the initial address, as described in
the Single Write Accesses on page 5. When ADV/LD is driven
HIGH on the subsequent clock rise, the chip enables (CE1, CE2,
and CE3) and WE inputs are ignored and the burst counter is
incremented. The correct BW[A:B] inputs must be driven in each
cycle of the burst write, to write the correct bytes of data.
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Interleaved Burst Address Table
(MODE = Floating or VDD)
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
IDDZZ
Sleep mode standby current
ZZ > VDD 0.2 V
–
40
mA
tZZS
Device operation to ZZ
ZZ > VDD 0.2 V
–
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2 V
2tCYC
–
ns
tZZI
ZZ active to sleep current
This parameter is sampled
–
2tCYC
ns
tRZZI
ZZ inactive to exit sleep current
This parameter is sampled
0
–
ns
Document Number: 38-05515 Rev. *R
Page 6 of 19
CY7C1353G
Truth Table
The truth table for CY7C1353G follows. [3, 4, 5, 6, 7, 8, 9]
Operation
Address Used CE1 CE2 CE3 ZZ ADV/LD WE BWX OE CEN CLK
DQ
Deselect cycle
None
H
X
X
L
L
X
X
X
L
L->H
Tri-state
Deselect cycle
None
X
X
H
L
L
X
X
X
L
L->H
Tri-state
Deselect cycle
None
X
L
X
L
L
X
X
X
L
L->H
Tri-state
Continue deselect cycle
None
X
X
X
L
H
X
X
X
L
L->H
Tri-state
External
L
H
L
L
L
H
X
L
L
L->H Data out (Q)
Next
X
X
X
L
H
X
X
L
L
L->H Data out (Q)
External
L
H
L
L
L
H
X
H
L
L->H
Tri-state
Next
X
X
X
L
H
X
X
H
L
L->H
Tri-state
External
L
H
L
L
L
L
L
X
L
L->H Data in (D)
WRITE cycle (continue burst)
Next
X
X
X
L
H
X
L
X
L
L->H Data in (D)
NOP/WRITE ABORT (begin burst)
None
L
H
L
L
L
L
H
X
L
L->H
Tri-state
WRITE ABORT (continue burst)
Next
X
X
X
L
H
X
H
X
L
L->H
Tri-state
Current
X
X
X
L
X
X
X
X
H
L->H
–
None
X
X
X
H
X
X
X
X
X
X
Tri-state
READ cycle (begin burst)
READ cycle (continue burst)
NOP/DUMMY READ (begin burst)
DUMMY READ (continue burst)
WRITE cycle (begin burst)
IGNORE CLOCK EDGE (stall)
SLEEP MODE
Partial Truth Table for Read/Write
The partial truth table for Read/Write for CY7C1353G follows. [3, 4, 10]
Function
WE
BWA
BWB
Read
H
X
X
Write – no bytes written
L
H
H
Write byte A – (DQA and DQPA)
L
L
H
Write byte B – (DQB and DQPB)
L
H
L
Write all bytes
L
L
L
Notes
3. X =”Don’t Care.” H = Logic HIGH, L = Logic LOW. BWx = L signifies at least one byte write select is active, BWx = valid signifies that the desired byte write selects
are asserted, see truth table for details.
4. Write is defined by BWX, and WE. See truth table for read/write.
5. When a write cycle is detected, all IOs are tri-stated, even during byte writes.
6. The DQs and DQP[A:B] pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
7. CEN = H, inserts wait states.
8. Device powers up deselected and the IOs in a tri-state condition, regardless of OE.
9. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP[A:B] = tri-state when OE is
inactive or when the device is deselected, and DQs and DQP[A:B] = data when OE is active.
10. Table only lists a partial listing of the byte write combinations. Any combination of BW[A:D] is valid. Appropriate write is based on which byte write is active.
Document Number: 38-05515 Rev. *R
Page 7 of 19
CY7C1353G
Maximum Ratings
DC input voltage ................................. –0.5 V to VDD + 0.5 V
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature with
power applied .......................................... –55 °C to +125 °C
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(MIL-STD-883, method 3015) ................................ > 2001 V
Latch-up current ................................................... > 200 mA
Operating Range
Supply voltage on VDD relative to GND .......–0.5 V to +4.6 V
Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD
Range
Ambient
Temperature (TA)
DC voltage applied to outputs
in tri-state ..........................................–0.5 V to VDDQ + 0.5 V
Commercial
0 °C to +70 °C
VDD
VDDQ
3.3 V – 5% / 2.5 V – 5% to
+ 10%
VDD
Electrical Characteristics
Over the Operating Range
Parameter [11, 12]
Description
Test Conditions
Min
Max
Unit
VDD
Power supply voltage
3.135
3.6
V
VDDQ
I/O supply voltage
2.375
VDD
V
VOH
Output HIGH voltage
VOL
VIH
VIL
IX
Output LOW voltage
for 3.3 V I/O, IOH = –4.0 mA
2.4
–
V
for 2.5 V I/O, IOH = –1.0 mA
2.0
–
V
for 3.3 V I/O, IOH = 8.0 mA
–
0.4
V
for 2.5 V I/O, IOH = 1.0 mA
–
0.4
V
Input HIGH voltage
for 3.3 V I/O
2.0
VDD + 0.3
V
Input HIGH voltage
for 2.5 V I/O
1.7
VDD + 0.3
V
[11]
for 3.3 V I/O
–0.3
0.8
V
Input LOW voltage [11]
for 2.5 V I/O
–0.3
0.7
V
Input leakage current except ZZ GND VI VDDQ
and MODE
5
5
µA
Input current of MODE
Input = VSS
–30
–
µA
Input = VDD
–
5
µA
Input = VSS
–5
–
µA
Input = VDD
–
30
µA
Input LOW voltage
Input current of ZZ
IOZ
Output leakage current
GND VI VDDQ, output disabled
–5
5
µA
IDD
VDD operating supply current
VDD = Max., IOUT = 0 mA,
f = fMAX= 1/tCYC
10-ns cycle,
100 MHz
–
205
mA
ISB1
Automatic CE power-down
current – TTL inputs
VDD = Max, device deselected, 10-ns cycle,
VIN VIH or VIN VIL, f = fMAX, 100 MHz
inputs switching
–
80
mA
ISB2
Automatic CE power-down
current – CMOS inputs
VDD = Max, device deselected, 10-ns cycle,
VIN VDD – 0.3 V or VIN 0.3 V, 100 MHz
f = 0, inputs static
–
40
mA
ISB3
Automatic CE power-down
current – CMOS inputs
VDD = Max, device deselected, 10-ns cycle,
VIN VDDQ – 0.3 V or VIN 0.3 V, 100 MHz
f = fMAX, inputs switching
–
65
mA
ISB4
Automatic CE power-down
current – TTL inputs
VDD = Max, device deselected, 10-ns cycle,
VIN VDD – 0.3 V or VIN 0.3 V, 100 MHz
f = 0, inputs static
–
45
mA
Notes
11. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).
12. TPower-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ VDD.
Document Number: 38-05515 Rev. *R
Page 8 of 19
CY7C1353G
Capacitance
Parameter [13]
Description
100-pin TQFP Unit
Max
Test Conditions
CIN
Input capacitance
5
pF
CCLOCK
Clock input capacitance
5
pF
CIO
I/O capacitance
5
pF
Test Conditions
100-pin TQFP
Package
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, according
to EIA/JESD51.
30.32
°C/W
6.85
°C/W
TA = 25 °C, f = 1 MHz, VDD = 3.3 V, VDDQ = 3.3 V
Thermal Resistance
Parameter [13]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317
3.3 V
OUTPUT
Z0 = 50
(a)
OUTPUT
RL = 50
VT = 1.5 V
2.5 V I/O Test Load
OUTPUT
Z0 = 50
(a)
GND
5 pF
INCLUDING
JIG AND
SCOPE
2.5 V
R = 351
5 pF
INCLUDING
JIG AND
SCOPE
10%
90%
10%
90%
1 ns
1 ns
(b)
(c)
R = 1667
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50
VT = 1.25 V
ALL INPUT PULSES
VDDQ
GND
R =1538
(b)
10%
90%
10%
90%
1 ns
1 ns
(c)
Note
13. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05515 Rev. *R
Page 9 of 19
CY7C1353G
Switching Characteristics
Over the Operating Range
Parameter [14, 15]
Description
-100
Unit
Min
Max
VDD(typical) to the first access [16]
1
–
ms
tCYC
Clock cycle time
10
–
ns
tCH
Clock HIGH
4.0
–
ns
tCL
Clock LOW
4.0
–
ns
tPOWER
Clock
Output Times
tCDV
Data output valid after CLK rise
–
8.0
ns
tDOH
Data output hold after CLK rise
2.0
–
ns
0
–
ns
–
3.5
ns
–
3.5
ns
0
–
ns
–
3.5
ns
[17, 18, 19]
tCLZ
Clock to low Z
tCHZ
Clock to high Z [17, 18, 19]
tOEV
OE LOW to output valid
tOELZ
tOEHZ
OE LOW to output low Z
[17, 18, 19]
OE HIGH to output high Z
[17, 18, 19]
Setup Times
tAS
Address setup before CLK rise
2.0
–
ns
tALS
ADV/LD setup before CLK rise
2.0
–
ns
tWES
WE, BWX setup before CLK rise
2.0
–
ns
tCENS
CEN setup before CLK rise
2.0
–
ns
tDS
Data input setup before CLK rise
2.0
–
ns
tCES
Chip enable setup before CLK rise
2.0
–
ns
tAH
Address hold after CLK rise
0.5
–
ns
tALH
ADV/LD hold after CLK rise
0.5
–
ns
tWEH
WE, BWX hold after CLK rise
0.5
–
ns
tCENH
CEN hold after CLK rise
0.5
–
ns
tDH
Data input hold after CLK rise
0.5
–
ns
tCEH
Chip enable hold after CLK rise
0.5
–
ns
Hold Times
Notes
14. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
15. Test conditions shown in (a) of Figure 2 on page 9, unless otherwise noted.
16. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can
be initiated.
17. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 2 on page 9. Transition is measured ± 200 mV from steady-state voltage.
18. At any voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus.
These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
tri-state prior to low Z under the same system conditions.
19. This parameter is sampled and not 100% tested.
Document Number: 38-05515 Rev. *R
Page 10 of 19
CY7C1353G
Switching Waveforms
Figure 3. Read/Write Waveforms [20, 21, 22]
1
2
3
tCYC
4
5
6
7
8
9
A5
A6
A7
10
CLK
tCENS
tCENH
tCES
tCEH
tCH
tCL
CEN
CE
ADV/LD
WE
BW[A:B]
A1
ADDRESS
tAS
A2
A4
A3
tCDV
tAH
tDOH
tCLZ
DQ
D(A1)
tDS
D(A2)
Q(A3)
D(A2+1)
tOEV
Q(A4+1)
Q(A4)
tOELZ
WRITE
D(A1)
WRITE
D(A2)
D(A5)
Q(A6)
D(A7)
WRITE
D(A7)
DESELECT
tOEHZ
tDH
OE
COMMAND
tCHZ
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
DON’T CARE
BURST
READ
Q(A4+1)
tDOH
WRITE
D(A5)
READ
Q(A6)
UNDEFINED
Notes
20. For this waveform ZZ is tied low.
21. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
22. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document Number: 38-05515 Rev. *R
Page 11 of 19
CY7C1353G
Switching Waveforms (continued)
Figure 4. NOP, STALL and DESELECT Cycles [23, 24, 25]
1
2
3
A1
A2
4
5
A3
A4
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BW[A:B]
ADDRESS
A5
tCHZ
D(A1)
DQ
Q(A2)
Q(A3)
D(A4)
Q(A5)
tDOH
COMMAND
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
DON’T CARE
Figure 5.
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
UNDEFINED
ZZ Mode Timing [26, 27]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
23. For this waveform ZZ is tied low.
24. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
25. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
26. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.
27. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 38-05515 Rev. *R
Page 12 of 19
CY7C1353G
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The following table contains only
the list of parts that are currently available.
For a complete listing of all options, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products or contact your local sales representative.
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
100
Package
Diagram
Ordering Code
CY7C1353G-100AXC
Part and Package Type
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Operating
Range
Commercial
Ordering Code Definitions
CY 7
C 1353 G - 100 A
X C
Temperature Range: C = Commercial
Pb-free
Package Type:
A = 100-pin TQFP
Speed Grade: 100 MHz
Process Technology: G 90 nm
Part Identifier: 1353 = FL, 256Kb × 18 (4Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-05515 Rev. *R
Page 13 of 19
CY7C1353G
Package Diagram
Figure 6. 100-pin TQFP (16 × 22 × 1.6 mm) Package Outline, 51-85050
ș2
ș1
ș
SYMBOL
DIMENSIONS
MIN. NOM. MAX.
A
A1
1.60
0.05
0.15
NOTE:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. BODY LENGTH DIMENSION DOES NOT
INCLUDE MOLD PROTRUSION/END FLASH.
A2
1.35 1.40 1.45
D
15.80 16.00 16.20
MOLD PROTRUSION/END FLASH SHALL
D1
13.90 14.00 14.10
E
21.80 22.00 22.20
NOT EXCEED 0.0098 in (0.25 mm) PER SIDE.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC
E1
19.90 20.00 20.10
R1
0.08
0.20
R2
0.08
0.20
ș
0°
7°
ș1
0°
ș2
11°
13°
12°
0.20
c
b
0.22 0.30 0.38
L
0.45 0.60 0.75
L1
L2
L3
e
BODY SIZE INCLUDING MOLD MISMATCH.
3. JEDEC SPECIFICATION NO. REF: MS-026.
1.00 REF
0.25 BSC
0.20
0.65 TYP
51-85050 *G
Document Number: 38-05515 Rev. *R
Page 14 of 19
CY7C1353G
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CMOS
Complementary Metal Oxide Semiconductor
CE
Chip Enable
°C
degree Celsius
CEN
Clock Enable
MHz
megahertz
EIA
Electronic Industries Alliance
µA
microampere
I/O
Input/Output
mA
milliampere
JEDEC
Joint Electron Devices Engineering Council
ms
millisecond
NoBL
No Bus Latency
mV
millivolt
OE
Output Enable
SRAM
Static Random Access Memory
TQFP
Thin Quad Flat Pack
TTL
Transistor-Transistor Logic
WE
Write Enable
Document Number: 38-05515 Rev. *R
Symbol
Unit of Measure
ns
nanosecond
ohm
%
percent
pF
picofarad
V
volt
W
watt
Page 15 of 19
CY7C1353G
Errata
This section describes the Ram9 NoBL ZZ pin issue. Details include trigger conditions, the devices affected, proposed workaround
and silicon revision applicability. Please contact your local Cypress sales representative if you have further questions.
Part Numbers Affected
Density & Revision
Package Type
Operating Range
4Mb-Ram9 NoBL™ SRAMs: CY7C135*G
100-pin TQFP
Commercial
Product Status
All of the devices in the Ram9 4Mb NoBL family are qualified and available in production quantities.
Ram9 NoBL ZZ Pin Issues Errata Summary
The following table defines the errata applicable to available Ram9 4Mb NoBL family devices.
Item
1.
Issues
ZZ Pin
Description
Device
When asserted HIGH, the ZZ pin places
device in a “sleep” condition with data integrity
preserved.The ZZ pin currently does not have
an internal pull-down resistor and hence
cannot be left floating externally by the user
during normal mode of operation.
4M-Ram9 (90 nm)
Fix Status
For the 4M Ram9 (90 nm)
devices, there is no plan to fix
this issue.
1. ZZ Pin Issue
■
Problem Definition
The problem occurs only when the device is operated in the normal mode with ZZ pin left floating. The ZZ pin on the SRAM
device does not have an internal pull-down resistor. Switching noise in the system may cause the SRAM to recognize a HIGH
on the ZZ input, which may cause the SRAM to enter sleep mode. This could result in incorrect or undesirable operation of the
SRAM.
■
Trigger Conditions
Device operated with ZZ pin left floating.
■
Scope of Impact
When the ZZ pin is left floating, the device delivers incorrect data.
■
Workaround
Tie the ZZ pin externally to ground.
■
Fix Status
For the 4M Ram9 (90 nm) devices, there is no plan to fix this issue.
Document Number: 38-05515 Rev. *R
Page 16 of 19
CY7C1353G
Document History Page
Document Title: CY7C1353G, 4-Mbit (256K × 18) Flow-Through SRAM with NoBL™ Architecture
Document Number: 38-05515
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
224363
RKF
05/17/2004
New data sheet.
*A
288431
VBL
11/10/2004
Updated Features (Removed 66 MHz frequency related information).
Updated Selection Guide (Removed 66 MHz frequency related information).
Updated Electrical Characteristics (Removed 66 MHz frequency related
information).
Updated Switching Characteristics (Removed 66 MHz frequency related
information).
Updated Ordering Information (Updated part numbers (Removed 66 MHz
frequency related information; changed TQFP package in Ordering Information
section to Pb-free TQFP)).
*B
333626
SYT
03/15/2005
Updated Features (Removed 117 MHz frequency related information).
Updated Selection Guide (Removed 117 MHz frequency related information).
Updated Pin Configuration (Modified Address Expansion balls in the pinouts
for 100-pin TQFP Packages according to JEDEC standards).
Updated Pin Definitions.
Updated Functional Overview (Updated ZZ Mode Electrical Characteristics
(Replaced “Snooze” with “Sleep”)).
Updated Truth Table (Replaced “Snooze” with “Sleep”).
Updated Electrical Characteristics (Updated Test Conditions of VOL, VOH
parameters; removed 117 MHz frequency related information).
Updated Thermal Resistance (Replaced values of JA and JC parameters
from TBD to their respective values).
Updated Switching Characteristics (Removed 117 MHz frequency related
information).
Updated Ordering Information (Updated part numbers (By shading and
unshading MPNs according to availability)).
*C
418633
RXU
01/06/2006
Changed status from Preliminary to Final.
Changed address of Cypress Semiconductor Corporation from “3901 North
First Street” to “198 Champion Court”.
Updated Electrical Characteristics (Updated Note 12 (Modified test condition
from VDDQ < VDD to VDDQ < VDD); changed “Input Load Current except ZZ and
MODE” to “Input Leakage Current except ZZ and MODE”).
Updated Ordering Information (Updated part numbers; removed Package
Name column; added Package Diagram column).
Updated Package Diagram (spec 51-85050 (changed revision from *A to *B)).
*D
480124
VKN
07/14/2006
Updated Maximum Ratings (Added the Maximum Rating for Supply Voltage
on VDDQ Relative to GND).
Updated Ordering Information (Updated part numbers).
*E
1274724
VKN /
AESA
07/17/2007
Updated Ordering Information (Updated part numbers (Corrected typo only).
*F
2896584
NJY
03/20/2010
Updated Ordering Information (Updated part numbers).
Updated Package Diagram:
spec 51-85050 – Changed revision from *B to *C.
*G
3033272
NJY
09/19/2010
Updated Ordering Information:
No change in part numbers.
Added Ordering Code Definitions.
Added Acronyms and Units of Measure
Minor edits.
Updated to new template.
Completing Sunset Review.
Document Number: 38-05515 Rev. *R
Description of Change
Page 17 of 19
CY7C1353G
Document History Page (continued)
Document Title: CY7C1353G, 4-Mbit (256K × 18) Flow-Through SRAM with NoBL™ Architecture
Document Number: 38-05515
Rev.
ECN No.
Orig. of
Change
Submission
Date
*H
3357006
PRIT
08/29/2011
Updated Package Diagram:
spec 51-85050 – Changed revision from *C to *D.
Updated to new template.
Completing Sunset Review.
*I
3619154
PRIT
05/16/2012
Updated Features (Removed 133 MHz frequency related information).
Updated Functional Description (Removed the Note “For best-practices
recommendations, please refer to the Cypress application note System Design
Guidelines on www.cypress.com.” and its reference; removed 133 MHz
frequency related information).
Updated Selection Guide (Removed 133 MHz frequency related information).
Updated Operating Range (Removed Industrial Temperature Range).
Updated Electrical Characteristics (Removed 133 MHz frequency related
information).
Updated Switching Characteristics (Removed 133 MHz frequency related
information).
Replaced all instances of IO with I/O across the document.
*J
3754982
PRIT
09/25/2012
No technical updates.
Completing Sunset Review.
*K
3980362
PRIT
04/24/2013
Added Errata.
*L
4038283
PRIT
06/24/2013
Added Errata Footnotes.
Updated to new template.
*M
4149033
PRIT
10/07/2013
Updated Errata.
*N
4539104
PRIT
10/15/2014
Updated Package Diagram:
spec 51-85050 – Changed revision from *D to *E.
Completing Sunset Review.
*O
4572829
PRIT
11/18/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*P
5512557
PRIT
11/07/2016
Updated Package Diagram:
spec 51-85050 – Changed revision from *E to *F.
Updated to new template.
Completing Sunset Review.
*Q
6041206
RMES
01/22/2018
Updated Package Diagram:
spec 51-85050 – Changed revision from *F to *G.
Updated to new template.
Completing Sunset Review.
*R
6520144
RMES
03/25/2019
Updated to new template.
Document Number: 38-05515 Rev. *R
Description of Change
Page 18 of 19
CY7C1353G
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Arm® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
Internet of Things
Memory
cypress.com/clocks
cypress.com/interface
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
Cypress Developer Community
Community | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2004–2019. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or
firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress
reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property
rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants
you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce
the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or
indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as provided by
Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the
Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such
as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, “Security
Breach”). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In
addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted
by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or
circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the
responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk Device”
means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other
medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk
Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of
a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from
and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress
product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i)
Cypress’s published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to
use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 38-05515 Rev. *R
Revised March 25, 2019
ZBT is a trademark of Integrated Device Technology, Inc. NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation.
Page 19 of 19
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