CY7C1357A
CY7C1355A
256K x 36/512K x 18 Synchronous Flow-Thru
SRAM with NoBL™ Architecture
Features
• Zero Bus Latency, no dead cycles between write and
read cycles
• Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns
• Fast clock speed: 133, 117, and 100 MHz
• Fast OE access time: 6.5, 7.0, and 7.5ns
• Internally synchronized registered outputs eliminate
the need to control OE
•
•
•
•
•
•
•
•
•
•
•
3.3V –5% and +5% power supply
3.3V or 2.5V I/O supply
Single WEN (READ/WRITE) control pin
Positive clock-edge triggered, address, data, and
control signal registers for fully pipelined applications
Interleaved or linear four-word burst capability
Individual byte write (BWa–BWd) control (may be tied
LOW)
CEN pin to enable clock and suspend operations
Three chip enables for simple depth expansion
Automatic Power-down feature available using ZZ
mode or CE deselect.
JTAG boundary scan (except CY7C1357A)
Low-profile 119-bump, 14-mm × 22-mm BGA (Ball Grid
Array) for CY7C1355A, and 100-pin TQFP packages for
both devices
Functional Description
The CY7C1355A and CY7C1357A SRAMs are designed to
eliminate dead cycles when transitions from READ to WRITE
or vice versa. These SRAMs are optimized for 100 percent bus
utilization and achieves Zero Bus Latency (ZBL). They
integrate 262,144 × 36 and 524,288 × 18 SRAM cells, respectively, with advanced synchronous peripheral circuitry and a
2-bit counter for internal burst operation. These employ
high-speed, low power CMOS designs using advanced
triple-layer polysilicon, double-layer metal technology. Each
memory cell consists of Six transistors.
All synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, depth-expansion
Chip Enables (CE, CE2, and CE3), Cycle Start Input (ADV/LD),
Clock Enable (CEN), Byte Write Enables (BWa, BWb, BWc,
and BWd), and read-write control (WEN). BWc and BWd apply
to CY7C1355A only.
Address and control signals are applied to the SRAM during
one clock cycle, and one cycle later, its associated data
occurs, either read or write.
A Clock Enable (CEN) pin allows operation of the
CY7C1355A/CY7C1357A to be suspended as long as
necessary. All synchronous inputs are ignored when (CEN) is
HIGH and the internal device registers will hold their previous
values.
There are three Chip Enable pins (CE, CE2, CE3) that allow
the user to deselect the device when desired. If any one of
these three are not active when ADV/LD is LOW, no new
memory operation can be initiated and any burst cycle in
progress is stopped. However, any pending data transfers
(read or write) will be completed. The data bus will be in
high-impedance state one cycle after chip is deselected or a
write cycle is initiated.
The CY7C1355A and CY7C1357A have an on-chip 2-bit burst
counter. In the burst mode, the CY7C1355A and CY7C1357A
provide four cycles of data for a single address presented to
the SRAM. The order of the burst sequence is defined by the
MODE input pin. The MODE pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load
a new external address (ADV/LD = LOW) or increment the
internal burst counter (ADV/LD = HIGH)
Output Enable (OE), Sleep Enable (ZZ) and burst sequence
select (MODE) are the asynchronous signals. OE can be used
to disable the outputs at any given time. ZZ may be tied to
LOW if it is not used.
Four pins are used to implement JTAG test capabilities. The
JTAG circuitry is used to serially shift data to and from the
device. JTAG inputs use LVTTL/LVCMOS levels to shift data
during this testing mode of operation.
Selection Guide
7C1355A-133
7C1357A-133
7C1355A-117
7C1357A-117
7C1355A-100
7C1357A-100
Unit
Maximum Access Time
6.5
7
7.5
ns
Maximum Operating Current
410
385
350
mA
Maximum CMOS Standby Current
30
30
30
mA
Cypress Semiconductor Corporation
Document #: 38-05265 Rev. *B
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised January 18, 2003
CY7C1357A
CY7C1355A
Functional Block Diagram 256Kx36[1]
256K x 9 x 4
SRAM Array
Address
CEN
ADV/LD
WE
WEN
CE, CE1, CE2,CE3
Control
Input
Registers
DI
BWa, BWb
BWc, BWd
DO
ZZ
MODE
A0, A1,
A0, SA
A1, A
Control Logic
Sel
Mux
CLK
Output Buffers
OE
DQa-DQd
Functional Block Diagram 512Kx18[1]
512K x 9 x 2
SRAM Array
Address
CEN
ADV/LD
R/W
WEN
CE, CE1, CE2,CE3
Input
Registers
DI
BWa, BWb
Control
DO
ZZ
MODE
A0, A1,SA
A0, A1, A
Control Logic
Mux
Sel
CLK
OE
Output Buffers
DQa, DQb
Note:
1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information.
Document #: 38-05265 Rev. *B
Page 2 of 28
CY7C1357A
CY7C1355A
Pin Configurations
100-pin TQFP Packages
256Kx36—CY7C1355A
Top View
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
100-pin TQFP
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
MODE
SA
SA
SA
SA
SA1
SA0
TMS
TDI
VSS
VCC
TDO
TCK
A
A
A
A
A
A
A
31
Document #: 38-05265 Rev. *B
DQb
DQb
DQb
VCCQ
VSS
DQb
DQb
DQb
DQb
VSS
VCCQ
DQb
DQb
VSS
VSS
VCC
ZZ
DQa
DQa
VCCQ
VSS
DQa
DQa
DQa
DQa
VSS
VCCQ
DQa
DQa
DQa
NC
NC
NC
VCCQ
VSS
NC
NC
DQb
DQb
VSS
VCCQ
DQb
DQb
VSS
VCC
VCC
VSS
DQb
DQb
VCCQ
VSS
DQb
DQb
DQb
NC
VSS
VCCQ
NC
NC
NC
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
66
15
16
65
100-pin TQFP
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
51
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
A
NC
NC
VCCQ
VSS
NC
DQa
DQa
DQa
VSS
VCCQ
DQa
DQa
VSS
VSS
VCC
ZZ
DQa
DQa
VCCQ
VSS
DQa
DQa
NC
NC
VSS
VCCQ
NC
NC
NC
50
MODE
A
A
A
A
A1
A0
TMS
NC
TDI
NC
VSS
VCC
TDO
NC
TCK
NC
A
A
A
A
A
A
A
100
DQc
DQc
DQc
VCCQ
VSS
DQc
DQc
DQc
DQc
VSS
VCCQ
DQc
DQc
VSS
VCC
VCC
VSS
DQd
DQd
VCCQ
VSS
DQd
DQd
DQd
DQd
VSS
VCCQ
DQd
DQd
DQd
A
A
CE1
CE2
NC
NC
BWb
BWa
CE3
VCC
VSS
CLK
WEN
/WE
CEN
OE
ADV/LD
NC
A
A
A
A
A
CE1
CE2
BWd
BWc
BWb
BWa
CE3
VCC
VSS
CLK
WEN
/WE
CEN
OE
ADV/LD
NC
A
A
A
512Kx18—CY7C1357A
Top View
Page 3 of 28
CY7C1357A
CY7C1355A
Pin Configurations (continued)
119-ball Bump BGA
256Kx36—CY7C1355A
Top View
1
2
3
4
5
6
7
A
VCCQ
A
A
NC
A
A
VCCQ
B
NC
CE2
A
ADV/LD
A
CE3
NC
C
NC
A
A
VCC
A
A
NC
D
DQc
DQc
VSS
NC
VSS
DQb
DQb
E
DQc
DQc
VSS
CE1
VSS
DQb
DQb
F
VCCQ
DQc
VSS
OE
VSS
DQb
VCCQ
G
DQc
DQc
BWc
A
BWb
DQb
DQb
H
DQc
DQc
VSS
WEN
VSS
DQb
DQb
J
VCCQ
VCC
NC
VCC
NC
VCC
VCCQ
K
DQd
DQd
VSS
CLK
VSS
DQa
DQa
L
DQd
DQd
BWd
NC
BWa
DQa
DQa
M
VCCQ
DQd
VSS
CEN
VSS
DQa
VCCQ
N
DQd
DQd
VSS
A1
VSS
DQa
DQa
P
DQd
DQd
VSS
A0
VSS
DQa
DQa
R
NC
A
MODE
VCC
VSS
A
NC
T
NC
NC
A
A
A
NC
ZZ
U
VCCQ
TMS
TDI
TCK
TDO
NC
VCCQ
Document #: 38-05265 Rev. *B
Page 4 of 28
CY7C1357A
CY7C1355A
Pin Descriptions (CY7C1355A)
256K × 36
TQFP Pins
256K × 36
PBGA Pins
37,
36,
32, 33, 34, 35,
44, 45, 46, 47,
48, 49, 50, 81,
82, 83, 99, 100
4P
4N
2A, 3A, 5A, 6A,
3B, 5B, 2C, 3C,
5C, 6C, 4G, 2R,
6R, 3T, 4T, 5T
A0,
A1,
A
InputSynchronous Address Inputs: The address register is triggered by
Synchronous a combination of the rising edge of CLK, ADV/LD LOW, CEN LOW
and true chip enables. A0 and A1 are the two least significant bits of
the address field and set the internal burst counter if burst cycle is
initiated.
93,
94,
95,
96
5L
5G
3G
3L
BWa,
BWb,
BWc,
BWd
InputSynchronous Byte Write Enables: Each nine-bit byte has its own
Synchronous active LOW byte write enable. On load write cycles (when WEN and
ADV/LD are sampled LOW), the appropriate byte write signal (BWx)
must be valid. The byte write signal must also be valid on each cycle
of a burst write. Byte write signals are ignored when WEN is sampled
HIGH. The appropriate byte(s) of data are written into the device one
cycle later. BWa controls DQa pins; BWb controls DQb pins; BWc
controls DQc pins; BWd controls DQd pins. BWx can all be tied LOW
if always doing a write to the entire 36-bit word.
87
4M
CEN
InputSynchronous Clock Enable Input: When CEN is sampled HIGH, all
Synchronous other synchronous inputs, including clock are ignored and outputs
remain unchanged. The effect of CEN sampled HIGH on the device
outputs is as if the LOW-to-HIGH clock transition did not occur. For
normal operation, CEN must be sampled LOW at rising edge of clock.
88
4H
WEN
InputRead Write: WEN signal is a synchronous input that identifies
Synchronous whether the current loaded cycle and the subsequent burst cycles
initiated by ADV/LD is a Read or Write operation. The data bus activity
for the current cycle takes place one clock cycle later.
89
4K
CLK
98, 92
4E, 6B
CE1,
CE3
InputSynchronous Active LOW Chip Enable: CE1 and CE3 are used with
Synchronous CE2 to enable the CY7C1355A. CE1 or CE3 sampled HIGH or CE2
sampled LOW, along with ADV/LD LOW at the rising edge of clock,
initiates a deselect cycle. The data bus will be High-Z one clock cycle
after chip deselect is initiated.
97
2B
CE2
InputSynchronous Active High Chip Enable: CE2 is used with CE1 and
Synchronous CE3 to enable the chip. CE2 has inverted polarity but otherwise is
identical to CE1 and CE3.
86
4F
OE
Input
Asynchronous Output Enable: OE must be LOW to read data.
Asynchronous When OE is HIGH, the I/O pins are in high-impedance state. OE does
not need to be actively controlled for read and write cycles. In normal
operation, OE can be tied LOW.
85
4B
ADV/
LD
InputAdvance/Load: ADV/LD is a synchronous input that is used to load
Synchronous the internal registers with new address and control signals when it is
sampled LOW at the rising edge of clock with the chip is selected.
When ADV/LD is sampled HIGH, then the internal burst counter is
advanced for any burst that was in progress. The external addresses
and WEN are ignored when ADV/LD is sampled HIGH.
31
3R
MODE
64
7T
ZZ
Document #: 38-05265 Rev. *B
Name
Type
InputClock
InputStatic
Description
Clock: This is the clock input to CY7C1355A. Except for OE, ZZ, and
MODE, all timing references for the device are made with respect to
the rising edge of CLK.
Burst Mode: When MODE is HIGH or NC, the interleaved burst
sequence is selected. When MODE is LOW, the linear burst
sequence is selected. MODE is a static DC input.
InputSleep Enable: This active HIGH input puts the device in low power
Asynchronous consumption standby mode. For normal operation, this input has to
be either LOW or NC.
Page 5 of 28
CY7C1357A
CY7C1355A
Pin Descriptions (CY7C1355A) (continued)
256K × 36
TQFP Pins
256K × 36
PBGA Pins
51, 52, 53,
56–59, 62, 63
68, 69, 72–75,
78, 79, 80
1, 2, 3, 6–9, 12,
13
18, 19, 22–25,
28, 29, 30
(a) 6P, 7P, 7N,
6N, 6M, 6L, 7L,
6K, 7K,
(b) 7H, 6H, 7G,
6G, 6F, 6E, 7E,
7D, 6D,
(c) 2D, 1D, 1E,
2E, 2F, 1G, 2G,
1H, 2H,
(d) 1K, 2K, 1L,
2L, 2M, 1N, 2N,
1P, 2P
DQa
DQb
DQc
DQd
38
39
43
2U
3U
4U
TMS
TDI
TCK
Input
IEEE 1149.1 test inputs: LVTTL-level inputs. If Serial Boundary Scan
(JTAG) is not used, these pins can be floating (i.e., No Connect) or
be connected to VCC.
42
5U
TDO
Output
Power
IEEE 1149.1 test output: LVTTL-level output. If Serial Boundary
Scan (JTAG) is not used, these pins can be floating (i.e., No Connect).
15, 16, 41, 65, 4C, 2J, 4J, 6J,
91
4R
VCC
Supply
Power Supply: +3.3V –5% and +5%.
5, 10, 14, 17,
21, 26, 40, 55,
60, 66, 67, 71,
76, 90
VSS
Ground
Ground: GND.
VCCQ
I/O Power
Supply
NC
–
3D, 5D, 3E, 5E,
3F, 5F, 3H, 5H,
3K, 5K, 3M, 5M,
3N, 5N, 3P, 5P,
5R
4, 11, 20, 27, 54, 1A, 7A, 1F, 7F,
61, 70, 77
1J, 7J, 1M, 7M,
1U, 7U
84
4A, 1B, 7B, 1C,
7C, 4D, 3J, 5J,
4L, 1R, 7R, 1T,
2T, 6T, 6U
Name
Type
Description
Input/
Data Inputs/Outputs: Both the data input path and data output path
Output
are registered and triggered by the rising edge of CLK. Byte “a” is
Synchronous DQa pins; Byte “b” is DQb pins; Byte “c” is DQc pins; Byte “d” is DQd
pins.
Power Supply for the I/O circuitry.
No Connect: These signals are not internally connected. It can be
left floating or be connected to VCC or to GND.
Pin Descriptions (CY7C1357A)
512K × 18
TQFP Pins
Name
Type
Description
37,
36,
32, 33, 34, 35, 44,
45, 46, 47, 48, 49,
50, 80, 81, 82, 83,
99, 100
A0,
A1,
A
InputSynchronous
Synchronous Address Inputs: The address register is triggered by a
combination of the rising edge of CLK, ADV/LD LOW, CEN LOW and true
chip enables. A0 and A1 are the two least significant bits of the address
field and set the internal burst counter if burst cycle is initiated.
93,
94,
BWa,
BWb
InputSynchronous
Synchronous Byte Write Enables: Each nine-bit byte has its own active
low byte write enable. On load write cycles (when WEN and ADV/LD are
sampled LOW), the appropriate byte write signal (BWx) must be valid. The
byte write signal must also be valid on each cycle of a burst write. Byte
write signals are ignored when WEN is sampled HIGH. The appropriate
byte(s) of data are written into the device one cycle later. BWa controls
DQa pins; BWb controls DQb pins. BWx can all be tied LOW if always
doing write to the entire 18-bit word.
87
CEN
InputSynchronous
Synchronous Clock Enable Input: When CEN is sampled HIGH, all
other synchronous inputs, including clock are ignored and outputs remain
unchanged. The effect of CEN sampled HIGH on the device outputs is as
if the LOW-to-HIGH clock transition did not occur. For normal operation,
CEN must be sampled LOW at rising edge of clock.
Document #: 38-05265 Rev. *B
Page 6 of 28
CY7C1357A
CY7C1355A
Pin Descriptions (CY7C1357A) (continued)
512K × 18
TQFP Pins
Name
Type
Description
88
WEN
InputSynchronous
Read Write: WEN signal is a synchronous input that identifies whether
the current loaded cycle and the subsequent burst cycles initiated by
ADV/LD is a Read or Write operation. The data bus activity for the current
cycle takes place one clock cycle later.
89
CLK
InputClock
Clock: This is the clock input to CY7C1357A. Except for OE, ZZ and
MODE, all timing references for the device are made with respect to the
rising edge of CLK.
98,
92
CE1, CE3
InputSynchronous
Synchronous Active Low Chip Enable: CE1 and CE3 are used with CE2
to enable the CY7C1357A. CE1 or CE3 sampled HIGH or CE2 sampled
LOW, along with ADV/LD LOW at the rising edge of clock, initiates a
deselect cycle. The data bus will be High-Z one clock cycle after chip
deselect is initiated.
97
CE2
InputSynchronous
Synchronous Active High Chip Enable: CE2 is used with CE1 and CE3
to enable the chip. CE2 has inverted polarity but otherwise is identical to
CE1 and CE3.
86
OE
InputAsynchronous
Asynchronous Output Enable: OE must be LOW to read data. When
OE is HIGH, the I/O pins are in high-impedance state. OE does not need
to be actively controlled for read and write cycles. In normal operation, OE
can be tied LOW.
85
ADV/
LD
InputSynchronous
Advance/Load: ADV/LD is a synchronous input that is used to load the
internal registers with new address and control signals when it is sampled
LOW at the rising edge of clock with the chip is selected. When ADV/LD
is sampled HIGH, then the internal burst counter is advanced for any burst
that was in progress. The external addresses and WEN are ignored when
ADV/LD is sampled HIGH.
31
MODE
Input
Burst Mode: When MODE is HIGH or NC, the interleaved burst sequence
is selected. When MODE is LOW, the linear burst sequence is selected.
MODE is a static DC input.
64
ZZ
Input
Asynchronous
Sleep Enable: This active HIGH input puts the device in low power
consumption standby mode. For normal operation, this input has to be
either LOW or NC.
58, 59, 62, 63, 68,
69, 72, 73, 74
8, 9, 12, 13, 18, 19,
22, 23, 24
DQa
DQb
Input/
OutputSynchronous
Data Inputs/Outputs: Both the data input path and data output path are
registered and triggered by the rising edge of CLK. Byte “a” is DQa pins;
Byte “b” is DQb pins.
15, 16, 41, 65, 91
VCC
Supply
Power Supply: +3.3V –5% and +5%.
5, 10, 14, 17, 21, 26,
40, 55, 60, 66, 67,
71, 76, 90
VSS
Ground
Ground: GND.
4, 11, 20, 27, 54, 61,
70, 77
VCCQ
1-3, 6, 7, 25, 28-30,
51-53, 56, 57, 75,
78, 79, 84, 95, 96,
38,39,42,43
NC
Document #: 38-05265 Rev. *B
I/O Power Supply Power supply for the I/O circuitry.
–
No Connect: These signals are not internally connected. It can be left
floating or be connected to VCC or to GND.
Page 7 of 28
CY7C1357A
CY7C1355A
Partial Truth Table for Read/Write[2]
Function
Read
No Write
WEN
BWa
BWb
BWc[4]
BWd[4]
H
X
X
X
X
L
H
H
H
H
Write Byte a (DQa)
[3]
L
L
H
H
H
Write Byte b (DQb)
[3]
L
H
L
H
H
Write Byte c (DQc)[3]
L
H
H
L
H
[3]
L
H
H
H
L
L
L
L
L
L
Write Byte d (DQd}
Write all bytes
Sleep Mode
Interleaved Burst Address Table
(MODE = VCC or NC)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)[5]
A...A00
A...A01
A...A10
A...A11
A...A01
A...A00
A...A11
A...A10
A...A10
A...A11
A...A00
A...A01
A...A11
A...A10
A...A01
A...A00
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs must remain inactive for the duration of
tZZREC after the ZZ input returns LOW. CEN needs to active
before going into the ZZ mode and before you want to come
back out of the ZZ mode.
Linear Burst Address Table
(MODE = VSS)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)[5]
A...A00
A...A01
A...A10
A...A11
A...A01
A...A10
A...A11
A...A00
A...A10
A...A11
A...A00
A...A01
A...A11
A...A00
A...A01
A...A10
Notes:
2. L means logic LOW. H means logic HIGH. X means “Don’t Care.”
3. Multiple bytes may be selected during the same cycle.
4. BWc and BWd apply to 256K × 36 device only.
5. Upon completion of the Burst sequence, the counter wraps around to its initial state and continues counting.
Document #: 38-05265 Rev. *B
Page 8 of 28
CY7C1357A
CY7C1355A
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
IDDZZ
Sleep mode standby current
ZZ > VDD – 0.2V
10
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2V
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2V
2tCYC
ns
Truth Table[6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]
Operation
Deselect Cycle
Continue Deselect/NOP[18]
Read Cycle (Begin Burst)
Read Cycle (Continue Burst)[18]
Dummy Read (Begin Burst)[19]
Dummy Read (Continue Burst)[18, 19]
Write Cycle (Begin Burst)
Write Cycle (Continue Burst)[18]
Abort Write (Begin Burst)[19]
Abort Write (Continue Burst)[18, 19]
Ignore Clock Edge/NOP[20]
Previous
Cycle
Address
Used
WEN ADV/LD
CE
CEN
BWx
OE
DQ
(1 cycle later)
X
X
X
L
H
L
X
X
High-Z
Deselect
X
X
H
X
L
X
X
High-Z
X
External
H
L
L
L
X
X
Q
Read
Next
X
H
X
L
X
X
Q
X
External
H
L
L
L
X
H
High-Z
Read
Next
X
H
X
L
X
H
High-Z
X
External
L
L
L
L
L
X
D
Write
Next
X
H
X
L
L
X
D
X
External
L
L
L
L
H
X
High-Z
Write
Next
X
H
X
L
H
X
High-Z
X
X
X
H
X
H
X
X
-
IEEE 1149.1 Serial Boundary Scan (JTAG)
Overview
This device (except for CY7C1357A) incorporates a serial
boundary scan access port (TAP). This port is designed to
operate in a manner consistent with IEEE Standard
1149.1-1990 (commonly referred to as JTAG), but does not
implement all of the functions required for IEEE 1149.1
compliance. Certain functions have been modified or eliminated because their implementation places extra delays in the
critical speed path of the device. Nevertheless, the device
supports the standard TAP controller architecture (the TAP
controller is the state machine that controls the TAPs
operation) and can be expected to function in a manner that
does not conflict with the operation of devices with IEEE
Standard 1149.1-compliant TAPs. The TAP operates using
LVTTL/ LVCMOS logic level signaling.
Disabling the JTAG Feature
It is possible to use this device without using the JTAG feature.
To disable the TAP controller without interfering with normal
operation of the device, TCK should be tied LOW (VSS) to
prevent clocking the device. TDI and TMS are internally pulled
up and may be unconnected. They may alternately be pulled
up to VCC through a resistor. TDO should be left unconnected.
Upon power-up the device will come up in a reset state which
will not interfere with the operation of the device.
Test Access Port
TCK—Test Clock (INPUT)
Clocks all TAP events. All inputs are captured on the rising
edge of TCK and all outputs propagate from the falling edge
of TCK.
Notes:
6. This assumes that CEN, CE, CE2, and CE2 are all True.
7. All addresses, control and data-in are only required to meet set-up and hold time with respect to the rising edge of clock. Data out is valid after a clock-to-data
delay from the rising edge of clock.
8. DQc and DQd apply to 256Kx36 device only.
9. L means logic LOW. H means logic HIGH. X means “Don’t Care.” High-Z means High Impedance. BWx = L means [BWa*BWb*BWc*BWd] equals LOW. BWx
= H means [BWa*BWb*BWc*BWd] equals HIGH. BWc and BWd apply to 256K × 36 device only.
10. CE = H means CE and CE2 are LOW along with CE2 being HIGH. CE = L means CE or CE2 is HIGH or CE2 is LOW. CE = X means CE, CE2, and CE2 are
“Don’t Care.”
11. BWa enables WRITE to byte “a” (DQa pins). BWb enables WRITE to byte “b” (DQb pins). BWc enables WRITE to byte “c” (DQc pins). BWd enables WRITE to
byte “d” (DQd pins). DQc, DQd, BWc, and BWd apply to 256K × 36 device only.
12. The device is not in Sleep Mode, i.e., the ZZ pin is LOW.
13. During Sleep Mode, the ZZ pin is HIGH and all the address pins and control pins are “Don’t Care.” The Sleep Mode can only be entered one cycle after the
WRITE cycle, otherwise the WRITE cycle may not be completed.
14. All inputs, except OE, ZZ, and MODE pins, must meet set-up time and hold time specification against the clock (CLK) LOW-to-HIGH transition edge.
15. OE may be tied to LOW for all the operation. This device automatically turns off the output driver during WRITE cycle.
16. Device outputs are ensured to be in High-Z during device power-up.
17. This device contains a two-bit burst counter. The address counter is incremented for all Continue Burst cycles. Address wraps to the initial address every fourth
burst cycle.
18. Continue Burst cycles, whether READ or WRITE, use the same control signals. The type of cycle performed, READ or WRITE, depends upon the WEN control
signal at the BEGIN BURST cycle. A Continue Deselect cycle can only be entered if a Deselect cycle is executed first.
19. Dummy Read and Abort WRITE cycles can be entered to set up subsequent READ or WRITE cycles or to increment the burst counter.
20. When an Ignore Clock Edge cycle enters, the output data (Q) will remain the same if the previous cycle is READ cycle or remain High-Z if the previous cycle is
WRITE or Deselect cycle.
Document #: 38-05265 Rev. *B
Page 9 of 28
CY7C1357A
CY7C1355A
TMS—Test Mode Select (INPUT)
Bypass Register
The TMS input is sampled on the rising edge of TCK. This is
the command input for the TAP controller state machine. It is
allowable to leave this pin unconnected if the TAP is not used.
The pin is pulled up internally, resulting in a logic HIGH level.
The bypass register is a single-bit register that can be placed
between TDI and TDO. It allows serial test data to be passed
through the device TAP to another device in the scan chain
with minimum delay. The bypass register is set LOW (VSS)
when the BYPASS instruction is executed.
TDI—Test Data In (INPUT)
The TDI input is sampled on the rising edge of TCK. This is the
input side of the serial registers placed between TDI and TDO.
The register placed between TDI and TDO is determined by
the state of the TAP controller state machine and the
instruction that is currently loaded in the TAP instruction
register (refer toFigure 1). It is allowable to leave this pin
unconnected if it is not used in an application. The pin is pulled
up internally, resulting in a logic HIGH level. TDI is connected
to the most significant bit (MSB) of any register. (See
Figure 2.)
Boundary Scan Register
TDO—Test Data Out (OUTPUT)
The Boundary scan register is connected to all the input and
bidirectional I/O pins (not counting the TAP pins) on the device.
This also includes a number of NC pins that are reserved for
future needs. There are a total of 70 bits for x36 device and 51
bits for x18 device. The boundary scan register, under the
control of the TAP controller, is loaded with the contents of the
device I/O ring when the controller is in Capture-DR state and
then is placed between the TDI and TDO pins when the
controller is moved to Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE-Z instructions can be used
to capture the contents of the I/O ring.
The TDO output pin is used to serially clock data-out from the
registers. The output that is active depending on the state of
the TAP state machine (refer to Figure 1). Output changes in
response to the falling edge of TCK. This is the output side of
the serial registers placed between TDI and TDO. TDO is
connected to the least significant bit (LSB) of any register.
(See Figure 2.)
The Boundary Scan Order table describes the order in which
the bits are connected. The first column defines the bit’s
position in the boundary scan register. The MSB of the register
is connected to TDI, and LSB is connected to TDO. The
second column is the signal name and the third column is the
bump number. The third column is the TQFP pin number and
the fourth column is the BGA bump number.
Performing a TAP Reset
Identification (ID) Register
The TAP circuitry does not have a reset pin (TRST, which is
optional in the IEEE 1149.1 specification). A RESET can be
performed for the TAP controller by forcing TMS HIGH (VCC)
for five rising edges of TCK and pre-loads the instruction
register with the IDCODE command. This type of reset does
not affect the operation of the system logic. The reset affects
test logic only.
At power-up, the TAP is reset internally to ensure that TDO is
in a High-Z state.
The ID Register is a 32-bit register that is loaded with a device
and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the
instruction register. The register is then placed between the
TDI and TDO pins when the controller is moved into Shift-DR
state. Bit 0 in the register is the LSB and the first to reach TDO
when shifting begins. The code is loaded from a 32-bit on-chip
ROM. It describes various attributes of the device as described
in the Identification Register Definitions table.
Test Access Port Registers
TAP Controller Instruction Set
Overview
Overview
The various TAP registers are selected (one at a time) via the
sequences of ones and zeros input to the TMS pin as the TCK
is strobed. Each of the TAPs registers are serial shift registers
that capture serial input data on the rising edge of TCK and
push serial data out on subsequent falling edge of TCK. When
a register is selected, it is connected between the TDI and
TDO pins.
There are two classes of instructions defined in the IEEE
Standard 1149.1-1990; the standard (public) instructions and
device specific (private) instructions. Some public instructions
are mandatory for IEEE 1149.1 compliance. Optional public
instructions must be implemented in prescribed ways.
Instruction Register
The instruction register holds the instructions that are
executed by the TAP controller when it is moved into the run
test/idle or the various data register states. The instructions
are three bits long. The register can be loaded when it is
placed between the TDI and TDO pins. The parallel outputs of
the instruction register are automatically preloaded with the
IDCODE instruction upon power-up or whenever the controller
is placed in the test-logic reset state. When the TAP controller
is in the Capture-IR state, the two least significant bits of the
serial instruction register are loaded with a binary “01” pattern
to allow for fault isolation of the board-level serial test data
path.
Document #: 38-05265 Rev. *B
Although the TAP controller in this device follows the IEEE
1149.1 conventions, it is not IEEE 1149.1 compliant because
some of the mandatory instructions are not fully implemented.
The TAP on this device may be used to monitor all input and
I/O pads, but can not be used to load address, data, or control
signals into the device or to preload the I/O buffers. In other
words, the device will not perform IEEE 1149.1 EXTEST,
INTEST, or the preload portion of the SAMPLE/PRELOAD
command.
When the TAP controller is placed in Capture-IR state, the two
least significant bits of the instruction register are loaded with
01. When the controller is moved to the Shift-IR state the
instruction is serially loaded through the TDI input (while the
previous contents are shifted out at TDO). For all instructions,
the TAP executes newly loaded instructions only when the
Page 10 of 28
CY7C1357A
CY7C1355A
controller is moved to Update-IR state. The TAP instruction
sets for this device are listed in the following tables.
this device, so the device TAP controller is not fully IEEE
1149.1-compliant.
EXTEST
When the SAMPLE/PRELOAD instruction is loaded in the
instruction register and the TAP controller is in the Capture-DR
state, a snap shot of the data in the device’s input and I/O
buffers is loaded into the boundary scan register. Because the
device system clock(s) are independent from the TAP Clock
(TCK), it is possible for the TAP to attempt to capture the input
and I/O ring contents while the buffers are in transition (i.e., in
a metastable state). Although allowing the TAP to sample
metastable inputs will not harm the device, repeatable results
can not be expected. To guarantee that the boundary scan
register will capture the correct value of a signal, the device
input signals must be stabilized long enough to meet the TAP
controller’s capture set up plus hold time (tCS plus tCH). The
device clock input(s) need not be paused for any other TAP
operation except capturing the input and I/O ring contents into
the boundary scan register.
EXTEST is an IEEE 1149.1 mandatory public instruction. It is
to be executed whenever the instruction register is loaded with
all 0s. EXTEST is not implemented in this device.
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the device responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is one difference between two instructions. Unlike SAMPLE/PRELOAD instruction, EXTEST places
the device outputs in a High-Z state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the ID register when the controller is in
Capture-DR mode and places the ID register between the TDI
and TDO pins in Shift-DR mode. The IDCODE instruction is
the default instruction loaded in the instruction upon power-up
and at any time the TAP controller is placed in the test-logic
reset state.
SAMPLE-Z
If the High-Z instruction is loaded in the instruction register, all
output pins are forced to a High-Z state and the boundary scan
register is connected between TDI and TDO pins when the
TAP controller is in a Shift-DR state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is an IEEE 1149.1 mandatory instruction.
The PRELOAD portion of the command is not implemented in
Document #: 38-05265 Rev. *B
Moving the controller to Shift-DR state then places the
boundary scan register between the TDI and TDO pins.
Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the Update-DR
state with the SAMPLE/PRELOAD instruction loaded in the
instruction register has the same effect as the Pause-DR
command.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP controller is in the Shift-DR state, the
bypass register is placed between TDI and TDO. This allows
the board level scan path to be shortened to facilitate testing
of other devices in the scan path.
Page 11 of 28
CY7C1357A
CY7C1355A
1[21]
TEST-LOGIC
RESET
0
0
REUN-TEST/
IDLE
1
1
1
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
0
SHIFT-DR
0
SHIFT-IR
1
1
1
EXIT1-DR
1
EXIT1-IR
0
0
PAUSE-DR
0
0
PAUSE-IR
1
1
0
0
EXIT2-DR
EXIT2-IR
1
1
UPDATE-DR
1
0
UPDATE-IR
1
0
Figure 1. TAP Controller State Diagram
Note:
21. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05265 Rev. *B
Page 12 of 28
CY7C1357A
CY7C1355A
ZZ
0
Bypass Register
Selection
Circuitry
2
TDI
1
0
1
0
1
0
Selection
Circuitry
TDO
Instruction Register
31 30
29
.
.
2
Identification Register
[22]
x
.
.
.
.
2
Boundary Scan Register [22]
TDI
TAP Controller
TDI
Figure 2. TAP Controller Block Diagram
TAP Electrical Characteristics Over the Operating Range
Parameter
VIH
Description
Test Conditions
Input High (Logic 1) Voltage[23, 24]
Voltage[23, 24]
Min.
Max.
Unit
2.0
VCC + 0.3
V
–0.3
0.8
V
–5.0
5.0
µA
VIl
Input Low (Logic 0)
ILI
Input Leakage Current
0V < VIN < VCC
ILI
TMS and TDI Input Leakage Current
0V < VIN < VCC
–30
30
µA
ILO
Output Leakage Current
Output disabled,
0V < VIN < VCCQ
–5.0
5.0
µA
VOLC
LVCMOS Output Low Voltage[23, 25]
IOLC = 100 µA
0.2
V
VOHC
LVCMOS Output High
Voltage[23, 25]
IOHC = 100 µA
VOLT
LVTTL Output Low Voltage[23]
VOHT
Voltage[23]
IOLT = 8.0 mA
VCC – 0.2
V
0.4
V
LVTTL Output High
IOHT = 8.0 mA
2.4
V
Notes:
22.X = 69 for the x36 configuration;
X = 50 for the x18 configuration.
23. All Voltage referenced to VSS (GND).
24. Overshoot: VIH(AC) VIH; all inputs static;
Inputs[33, 34, 35]
VCC = max.; CLK frequency = 0
40
190
180
170
mA
15
30
30
30
mA
ISB4
Device deselected; VCC = max.;
all inputs < VSS + 0.2 or > VCC – 0.2;
all inputs static; CLK frequency = 0
Notes:
28. Please refer to waveform (d).
29. Power supply ramp up should be monotonic.
30. Overshoot: VIH < +6.0V for t < tKC /2;Undershoot:VIL < -2.0V for t < tKC /2.
31. MODE pin has an internal pull-up and ZZ pin has an internal pull-down. These two pins exhibit an input leakage current of ±50 µA.
32. ICC is given with no output current. ICC increases with greater output loading and faster cycle times.
33. “Device Deselected” means the device is in Power-Down mode as defined in the truth table. “Device Selected” means the device is active.
34. Typical values are measured at 3.3V, 25°C, and 20 ns cycle time.
35. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f = 0 means no input lines are changing.
Document #: 38-05265 Rev. *B
Page 18 of 28
CY7C1357A
CY7C1355A
Capacitance[25]
Parameter
Description
Test Conditions
CI
Input Capacitance
CI/O
Input/Output Capacitance DQ
TA[36] = 25°C,
VCC = 3.3V
Typ.
f = 1 MHz,
Max.
Unit
4
4
pF
7
6.5
pF
Thermal Resistance
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
TQFP Typ.
Unit
Still Air, soldered on a 4.25 ×1.125 inch, four-layer PCB
25
°C/W
9
°C/W
AC Test Loads and Waveforms
R = 317Ω
VCCQ
OUTPUT
Z0 =50Ω
VCCQ
RL = 50Ω
INCLUDING
JIG AND
SCOPE
(a)
Vcctyp
Vccmin
90%
10%
90%
10%
5 pF
R = 351Ω
VTH = 1.5V
t PU = 200us
ALL INPUT PULSES
OUTPUT
GND
For proper RESET
bring Vcc down to 0V
≤ 1 V/ns
≤ 1 V/ns
(c)
(b)
(d)
Switching Characteristics Over the Operating Range[37]
133-MHz
Parameter
Description
Min.
Max.
117 MHz
Min.
Max.
100 MHz
Min.
Max.
Unit
Clock
tKC
Clock Cycle Time
7.5
8.5
10
ns
tKH
Clock HIGH Time
2.5
3.0
3.5
ns
tKL
Clock LOW Time
2.5
3.0
3.5
ns
Output Times
tKQ
Clock to Output Valid
tKQX
Clock to Output Invalid
2.0
2.0
2.0
ns
tKQLZ
Clock to Output in Low-Z[25, 38, 39]
3.0
3.0
3.0
ns
tKQHZ
Clock to Output in
High-Z[25, 38, 39]
tOEQ
OE to Output Valid
Low-Z[25, 38, 39]
tOELZ
OE to Output in
tOEHZ
OE to Output in High-Z[25, 38, 39]
6.5
2
3.5
7.0
2
3.5
0
3.5
7.5
2
3.5
0
3.5
3.5
ns
4.0
ns
0
3.5
ns
ns
3.5
ns
Set-up Times
tS
tSD
Address and Controls[40]
Data
In[40]
1.5
1.5
1.8
ns
1.5
1.5
1.8
ns
Hold Times
tH
Address and Controls[40]
0.5
0.5
0.5
ns
tHD
Data In[40]
0.5
0.5
0.5
ns
Notes:
36. TA is the case temperature.
37. Test conditions as specified with the output loading as shown in part (a) of AC Test Loads unless otherwise noted.
38. Output loading is specified with CL = 5 pF as in part (a) of AC Test Loads.
39. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tOELZ.
40. This is a synchronous device. All synchronous inputs must meet specified setup and hold time, except for “don’t care” as defined in the truth table.
Document #: 38-05265 Rev. *B
Page 19 of 28
CY7C1357A
CY7C1355A
Switching Waveforms
Read Timing[41, 42, 43, 44, 45]
tKC
tKH
tKL
CLK
CLK
tS
tH
tS
tH
tS
tH
CKE
CEN
R/W
WEN
A
ADDRESS
A1
A2
BWa, BWb
BWx
BWc, BWd
tS
tH
CE
CE
tS
tH
ADV/LD
ADV/LD
OE
OE
tKQLZ
DQ
DQx
Q(A1)
Read
tKQ
(CKE# HIGH, eliminates
current L-H clock edge)
tKQX
Q(A2 )
Read
Q(A2 +1 )
Q(A2 +2 )
Q(A2+3 )
BURST READ
(Burst Wraps around
to initial state)
tKQHZ
Q(A2 )
Deselec
t
Notes:
41. Q(A1) represents the first output from the external address A1. Q(A2) represents the first output from the external address A2; Q(A2+1) represents the next
output data in the burst sequence of the base address A2, etc. where address bits SA0 and SA1 are advancing for the four word burst in the sequence defined
by the state of the MODE input.
42. CE2 timing transitions are identical to the CE signal. For example, when CE is LOW on this waveform, CE2 is LOW. CE2 timing transitions are identical but
inverted to the CE signal. For example, when CE is LOW on this waveform, CE2 is HIGH.
43. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
44. WEN is “Don’t Care” when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the WEN
signal when new address and control are loaded into the SRAM.
45. BWc and BWd apply to 256K × 36 device only.
Document #: 38-05265 Rev. *B
Page 20 of 28
CY7C1357A
CY7C1355A
Switching Waveforms (continued)
Write Timing[42, 43, 44, 45, 46, 47]
tKC
tKH
tKL
CLK
CLK
tS
tH
CKE
CEN
tS
tH
R/W
WEN
tS
ADDRESS
A
tH
A1
A2
tS
BWa, BWb
BWx
BWc, BWd
BW(A1)
tH
BW(A2 )
BW(A2+1)
tS
tH
tS
tH
BW(A2 +2)
BW(A2+3)
BW(A2)
CE
CE
ADV/LD
ADV/LD
OE
OE
tSD
DQ
DQx
tHD
(CKE# HIGH, eliminates
current L-H clock edge)
D(A1 )
Write
D(A2)
Write
D(A2+1)
D(A2+2)
Burst Write
(Burst Wraps around
to initial state)
D(A2+3)
D(A2)
Deselect
Notes:
46. D(A1) represents the first input to the external address A1. D(A2) represents the first input to the external address A2; D(A2+1) represents the next input data
in the burst sequence of the base address A2, etc. where address bits SA0 and SA1 are advancing for the four word burst in the sequence defined by the
state of the MODE input.
47. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when WEN signal is sampled LOW when ADV/LD
is sampled LOW. The byte write information comes in one cycle before the actual data is presented to the SRAM.
Document #: 38-05265 Rev. *B
Page 21 of 28
CY7C1357A
CY7C1355A
Switching Waveforms (continued)
Read/Write Timing[42, 45, 47, 48]
tKC
tKH
tKL
CLK
tS
tH
tS
tH
tS
tH
CKE#
R/W#
ADDRESS
A1
A2
A3
tS
BWa#, BWb#
BWc#, BWd#
A4
A5
BW(A4)
BW(A5)
A6
A7
A8
A9
tH
BW(A2)
tS
tH
tS
tH
CE#
ADV/LD#
OE#
tKQ
DATA Out (Q)
tKQHZ
tKQLZ
Q(A1)
tKQX
Q(A3)
Q(A6)
Read
Read
DATA In (D)
D(A2)
Write
Q(A7)
Read
D(A4)
D(A5)
Write
D(A8)
Write
Note:
48. Q(A1) represents the first output from the external address A1. D(A2) represents the input data to the SRAM corresponding to address A2.
Document #: 38-05265 Rev. *B
Page 22 of 28
CY7C1357A
CY7C1355A
Switching Waveforms (continued)
CEN Timing[42, 45, 47, 48, 49]
tKC
tKH
tKL
CLK
CLK
tS
tH
CEN
CKE#
tS
tH
tS
tH
R/W#
WEN
ADDRESS
A
A1
A2
A3
tS
tH
tS
tH
BWa#, BW
BWb#
x
BWc#, BWd#
A4
A5
CE#
CE
tS
tH
ADV/LD#
ADV/LD
OE#
OE
tKQ
tKQHZ
DATA Out (Q)
Q(A1)
tKQLZ
DATA In (D)
Q(A3)
tKQX
Q(A4)
tSD tHD
D(A2)
Note:
49. CEN when sampled HIGH on the rising edge of clock will block that L-H transition of the clock from propagating into the SRAM. The part will behave as if the
L-H clock transition did not occur. All internal register in the SRAM will retain their previous state.
Document #: 38-05265 Rev. *B
Page 23 of 28
CY7C1357A
CY7C1355A
Switching Waveforms (continued)
CE Timing[42, 45, 47, 50, 51]
tKC
tKH
tKL
CLK
CLK
tS
tH
CEN
CKE#
tS
tH
R/W#
WEN
tS
ADDRESS
A
tH
A1
A2
A3
tS
tH
tS
tH
BWa#, BWb#
BWx
BWc#, BWd#
tS
A4
A5
tH
CE#
CE
ADV/LD#
ADV/LD
tOEQ
OE#
OE
tKQHZ
tOELZ
DATA Out (Q)
DATA In (D)
Q(A1)
tKQLZ
tKQ
tOEHZ
Q(A2)
Q(A4)
tKQX
tSD tHD
D(A3)
Notes:
50. Q(A1) represents the first output from the external address A1. D(A3) represents the input data to the SRAM corresponding to address A3, etc.
51. When either one of the Chip enables (CE, CE2 or CE2) is sampled inactive at the rising clock edge, a chip deselect cycle is initiated. The data-bus High-Z
one cycle after the initiation of the deselect cycle. This allows for any pending data transfers (reads or writes) to be completed.
Document #: 38-05265 Rev. *B
Page 24 of 28
CY7C1357A
CY7C1355A
Switching Waveforms (continued)
ZZ Mode Timing [ 52, 53]
CLK
CE1
LOW
CE2
HIGH
CE3
ZZ
tZZS
IDD
IDD(active)
tZZREC
IDDZZ
I/Os
Three-state
Note:
52. Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device.
53. I/Os are in three-state when exiting ZZ sleep mode.
Ordering Information
Speed
(MHz)
Ordering Code
Package
Name
Package Type
Operating
Range
133
CY7C1355A-133AC
CY7C1357A-133AC
A101
100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack
Commercial
117
CY7C1355A-117AC
A101
100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack
Commercial
A101
100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack
CY7C1355A-117AI
100
Industrial
CY7C1355A-117BGC
BG119
119-lead BGA (14 × 22 × 2.4 mm)
CY7C1355A-117BGI
BG119
119-lead BGA (14 × 22 × 2.4 mm)
CY7C1355A-100AC
CY7C1357A-100AC
A101
100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack
Commercial
CY7C1357A-100AI
A101
100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack
Industrial
CY7C1355A-100BGC
Document #: 38-05265 Rev. *B
BG119
119-lead BGA (14 × 22 × 2.4 mm)
Commercial
Industrial
Commercial
Page 25 of 28
CY7C1357A
CY7C1355A
Package Diagrams
100-pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm) A101
51-85050-A
Document #: 38-05265 Rev. *B
Page 26 of 28
CY7C1357A
CY7C1355A
Package Diagrams (continued)
119-lead BGA (14 × 22 × 2.4) BG119
51-85115-*A
No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation. All product and company names mentioned
in this document are the trademarks of their respective holders.
Document #: 38-05265 Rev. *B
Page 27 of 28
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1357A
CY7C1355A
Document Title: CY7C1355A/CY7C1357A 256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL™ Architecture
Document Number: 38-05265
REV
ECN
Issue Date
Orig. of
Change
Description of Change
**
114118
7/16/02
KKV
New Data Sheet
*A
117837
08/26/02
HGK
Removed BGA package from 1357A
Removed JTAG from 1357A
Removed 1357A1 and 1355A1 part numbers
*B
123146
01/18/03
RBI
Updated power-up requirements in Operating Range and in AC Test Loads
and Waveforms.
Document #: 38-05265 Rev. *B
Page 28 of 28
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