CY7C1368C
9-Mbit (256K x 32) Pipelined DCD Sync SRAM
Functional Description[1]
Features
• Registered inputs and outputs for pipelined operation
• Optimal for performance (Double-Cycle deselect)
— Depth expansion without wait state
• 256K × 32-bit common I/O architecture
• 3.3V core power supply (VDD)
• 2.5V/3.3V I/O power supply (VDDQ)
• Fast clock-to-output times
— 2.8 ns (for 250-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel®
Pentium® interleaved or linear burst sequences
• Multiple chip enables for depth expansion: Three chip
enables for A package version and Two chip enables
for AJ package version
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous Output Enable
• Available in JEDEC-standard lead-free 100-Pin TQFP
package
• “ZZ” Sleep Mode option
The CY7C1368C SRAM integrates 256K x 32 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE1), depth-expansion Chip Enables (CE2 and CE3[2]), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables (BWA,
BWB, BWC, BWD, and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and the
ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle. This part supports Byte
Write operations (see Pin Descriptions and Truth Table for
further details). Write cycles can be one to four bytes wide as
controlled by the byte write control inputs. GW active LOW
causes all bytes to be written. This device incorporates an
additional pipelined enable register which delays turning off
the output buffers an additional cycle when a deselect is
executed.This feature allows depth expansion without penal
izing system performance.
The CY7C1368C operates from a +3.3V core power supply
while all outputs may operate with either a +2.5 or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
250 MHz
200 MHz
166 MHz
Unit
Maximum Access Time
2.8
3.0
3.5
ns
Maximum Operating Current
250
220
180
mA
Maximum CMOS Standby Current
40
40
40
mA
Notes:
1. For best-practice recommendations, please refer to the Cypress application note System Design Guidelines on http://www.cypress.com.
2. CE3 is for A version (3 Chip enable option) only.
Cypress Semiconductor Corporation
Document #: 38-05686 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 14, 2006
[+] Feedback
CY7C1368C
Functional Block Diagram-CY7C1368C (256K x 32)
ADDRESS
REGISTER
A0,A1,A
2 A[1:0]
MODE
ADV
CLK
BURST
Q1
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
BWD
DQD
BYTE
WRITE REGISTER
DQD
BYTE
WRITE DRIVER
BWC
DQc
BYTE
WRITE REGISTER
DQC
BYTE
WRITE DRIVER
DQB
BYTE
WRITE REGISTER
DQB
BYTE
WRITE DRIVER
BWB
BWA
BWE
GW
CE1
CE2
CE3
OE
ZZ
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
DQs
E
DQA
BYTE
WRITE DRIVER
DQA
BYTE
WRITE REGISTER
ENABLE
REGISTER
MEMORY
ARRAY
PIPELINED
ENABLE
INPUT
REGISTERS
SLEEP
CONTROL
Document #: 38-05686 Rev. *F
Page 2 of 18
[+] Feedback
CY7C1368C
Pin Configurations
100-Pin TQFP Pinout (2-Chip Enable) (AJ version)
CE1
CE2
BWD
BWC
BWB
BWA
A
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CY7C1368C
(256K x 32)
NC
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQb
DQb
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
NC
Document #: 38-05686 Rev. *F
A
A
A
A
A
A
A
NC/18M
NC
NC/72M
NC/36M
VSS
VDD
MODE
A
A
A
A
A1
A0
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
NC
Page 3 of 18
[+] Feedback
CY7C1368C
Pin Configurations (continued)
100-Pin TQFP Pinout (3-Chip Enable) (A version)
CE1
CE2
BWD
BWC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1368C
(256K x 32)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
NC
Document #: 38-05686 Rev. *F
A
A
A
A
A
A
A
A
NC/18M
NC/72M
NC/36M
VSS
VDD
MODE
A
A
A
A
A1
A0
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
NC
Page 4 of 18
[+] Feedback
CY7C1368C
Pin Descriptions
Pin
A0, A1, A
TQFP
Type
Description
InputAddress Inputs used to select one of the 256K address locations. Sampled at
37, 36, 32, 33,
34, 35, 44, 45, Synchronous the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and
46, 47, 48, 49,
CE3[2] are sampled active. A[1:0] are fed to the two-bit counter.
50, 80, 81, 82,
99, 100, 92
(AJC), 43 (AC)
BWA, BWB, 93, 94
BWC, BWD
InputByte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes
Synchronous to the SRAM. Sampled on the rising edge of CLK.
GW
88
InputGlobal Write Enable Input, active LOW. When asserted LOW on the rising edge
Synchronous of CLK, a global write is conducted (ALL bytes are written, regardless of the values
on BW[A:D] and BWE).
BWE
87
InputByte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This
Synchronous signal must be asserted LOW to conduct a byte write.
CLK
89
CE1
98
InputChip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1
is HIGH. CE1 is sampled only when a new external address is loaded.
CE2
97
InputChip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE1 and CE3 to select/deselect the device. CE2 is sampled only
when a new external address is loaded.
CE3[2]
92
InputChip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE1 and CE2 to select/deselect the device. Not available for AJ
package version.CE3[2] is assumed active throughout this document for BGA. CE3
is sampled only when a new external address is loaded.
OE
86
InputOutput Enable, asynchronous input, active LOW. Controls the direction of the
Asynchronous I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O
pins are tri-stated, and act as input data pins. OE is masked during the first clock
of a read cycle when emerging from a deselected state.
ADV
83
InputAdvance Input signal, sampled on the rising edge of CLK, active LOW. When
Synchronous asserted, it automatically increments the address in a burst cycle.
ADSP
84
InputAddress Strobe from Processor, sampled on the rising edge of CLK, active
Synchronous LOW. When asserted LOW, addresses presented to the device are captured in the
address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is
deasserted HIGH.
ADSC
85
InputAddress Strobe from Controller, sampled on the rising edge of CLK, active
Synchronous LOW. When asserted LOW, addresses presented to the device are captured in the
address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
ZZ
64
InputZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a
Asynchronous non-time-critical “sleep” condition with data integrity preserved. For normal
operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down.
DQs
I/OBidirectional Data I/O lines. As inputs, they feed into an on-chip data register that
2, 3, 6, 7, 8, 9,
12, 13, 18, 19, Synchronous is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by the addresses presented during the previous
22, 23, 24, 25,
clock rise of the read cycle. The direction of the pins is controlled by OE. When OE
28, 29, 52, 53,
56, 57, 58, 59,
is asserted LOW, the pins behave as outputs. When HIGH, DQs are placed in a
62, 63, 68, 69,
tri-state condition.
72, 73, 74, 75,
78, 79
VDD
15, 41, 65, 91
VSS
17, 40, 67, 90
InputClock
Clock Input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
Power Supply Power supply inputs to the core of the device.
Document #: 38-05686 Rev. *F
Ground
Ground for the core of the device.
Page 5 of 18
[+] Feedback
CY7C1368C
Pin Descriptions (continued)
Pin
TQFP
Type
VDDQ
4, 11, 20, 27,
54, 61, 70, 77
I/O Power
Supply
Power supply for the I/O circuitry.
VSSQ
5, 10, 21, 26,
55, 60, 71, 76
I/O Ground
Ground for the I/O circuitry.
MODE
31
NC
1, 16, 30, 38,
39, 42,
43(AJC), 51,
66, 80
InputStatic
Description
Selects Burst Order. When tied to GND selects linear burst sequence. When tied
to VDD or left floating selects interleaved burst sequence. This is a strap pin and
should remain static during device operation. Mode Pin has an internal pull-up.
No Connects. Not internally connected to the die.
NC/(18M,36M, 72M, 144M, 288M, 576M, 1G) These pins are not connected.
They will be used for expansion to the 18M, 36M, 72M, 144M, 288M, 576M and 1G
densities.
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
The CY7C1368C supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Synchronous Chip Selects CE1, CE2, CE3 and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
chip selects are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1
is HIGH. The address presented to the address inputs is
stored into the address advancement logic and the Address
Register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within tco if OE is active LOW. The only exception
occurs when the SRAM is emerging from a deselected state
to a selected state, its outputs are always tri-stated during the
first cycle of the access. After the first cycle of the access, the
outputs are controlled by the OE signal. Consecutive single
read cycles are supported.
Document #: 38-05686 Rev. *F
The CY7C1368C is a double-cycle deselect part. Once the
SRAM is deselected at clock rise by the chip select and either
ADSP or ADSC signals, its output will tri-state immediately
after the next clock rise.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
chip select is asserted active. The address presented is
loaded into the address register and the address
advancement logic while being delivered to the memory core.
The write signals (GW, BWE, and BW[A:D]) and ADV inputs are
ignored during this first cycle.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the corresponding address location in the memory core. If GW is HIGH,
then the write operation is controlled by BWE and BW[A:D]
signals. The CY7C1368C provides byte write capability that
is described in the Write Cycle Description table. Asserting the
Byte Write Enable input (BWE) with the selected Byte Write
input will selectively write to only the desired bytes. Bytes not
selected during a byte write operation will remain unaltered. A
synchronous self-timed write mechanism has been provided
to simplify the write operations.
Because the CY7C1368C is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQs are automatically tri-stated whenever
a write cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) chip select is asserted active, and (4)
the appropriate combination of the write inputs (GW, BWE,
and BW[A:D]) are asserted active to conduct a write to the
desired byte(s). ADSC triggered write accesses require a
single clock cycle to complete. The address presented is
loaded into the address register and the address
advancement logic while being delivered to the memory core.
The ADV input is ignored during this cycle. If a global write is
conducted, the data presented to the DQX is written into the
corresponding address location in the memory core. If a byte
write is conducted, only the selected bytes are written. Bytes
not selected during a byte write operation will remain
Page 6 of 18
[+] Feedback
CY7C1368C
Interleaved Burst Address Table
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
(MODE = Floating or VDD)
Because the CY7C1368C is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQX inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQX are automatically tri-stated
whenever a write cycle is detected, regardless of the state of
OE.
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Burst Sequences
The CY7C1368C provides a two-bit wraparound counter, fed
by A[1:0], that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input. Both read and write burst operations
are supported
Linear Burst Address Table (MODE = GND)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LOW.
Truth Table[3, 4, 5, 6, 7]
Operation
Address
Used CE1 CE3 CE2 ZZ ADSP ADSC
Deselected Cycle, Power-down
None
H
Deselected Cycle, Power-down
None
L
Deselected Cycle, Power-down
None
L
Deselected Cycle, Power-down
None
L
Deselected Cycle, Power-down
None
L
ZZ Mode, Power-down
ADV
WRITE
OE
CLK
DQ
X
L
X
L
X
X
X
L-H
Tri-state
X
L
L
L
X
X
X
X
L-H
Tri-state
H
X
L
L
X
X
X
X
L-H
Tri-state
X
L
L
H
L
X
X
X
L-H
Tri-state
H
X
L
H
L
X
X
X
L-H
Tri-state
X
None
X
X
X
H
X
X
X
X
X
X
Tri-state
Read Cycle, Begin Burst
External
L
L
H
L
L
X
X
X
L
L-H
Q
Read Cycle, Begin Burst
External
L
L
H
L
L
X
X
X
H
L-H
Tri-state
Write Cycle, Begin Burst
External
L
L
H
L
H
L
X
L
X
L-H
D
Read Cycle, Begin Burst
External
L
L
H
L
H
L
X
H
L
L-H
Q
Read Cycle, Begin Burst
External
L
L
H
L
H
L
X
H
H
L-H
Tri-state
Next
X
X
X
L
H
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Notes:
3. X = “Don't Care.” H = Logic HIGH, L =Logic LOW.
4. WRITE = L when any one or more Byte Write enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW = L. WRITE = H when all Byte write enable signals
(BWA, BWB, BWC, BWD), BWE, GW=H.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: D]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05686 Rev. *F
Page 7 of 18
[+] Feedback
CY7C1368C
Truth Table[3, 4, 5, 6, 7] (continued)
Address
Used CE1 CE3 CE2 ZZ ADSP ADSC
Next
X
X
X
L
H
H
Operation
Read Cycle, Continue Burst
ADV
WRITE
OE
CLK
DQ
L
H
H
L-H
Tri-state
X
H
L
H
L
L-H
Q
L
X
H
L
H
H
L-H
Tri-state
L
H
H
L
L
X
L-H
D
L
L
X
L-H
D
H
H
L
L-H
Q
H
H
H
L-H
Tri-state
H
H
L
L-H
Q
H
H
H
L-H
Tri-state
H
L
X
L-H
D
H
L
X
L-H
D
Read Cycle, Continue Burst
Next
H
X
X
L
Read Cycle, Continue Burst
Next
H
X
X
Write Cycle, Continue Burst
Next
X
X
X
Write Cycle, Continue Burst
Next
H
X
X
L
X
H
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
Write Cycle, Suspend Burst
Current
X
X
X
L
H
H
Write Cycle, Suspend Burst
Current
H
X
X
L
X
H
Truth Table for Read/Write[3, 4]
Function
GW
BWE
BWA
BWB
BWC
BWD
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write byte A - (DQA and DQPA)
H
L
L
H
H
H
Write byte B - (DQB and DQPB)
H
L
H
L
H
H
Write byte C - (DQC and DQPC)
H
L
H
H
L
H
Write byte D - (DQD and DQPD)
H
L
H
H
H
L
Write all bytes
H
L
L
L
L
L
Write all bytes
L
X
X
X
X
X
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
IDDZZ
sleep mode standby current
ZZ > VDD − 0.2V
50
mA
tZZS
Device operation to ZZ
ZZ > VDD − 0.2V
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2V
tZZI
ZZ recovery time
This parameter is sampled
tRZZI
ZZ inactive to exit sleep current
This parameter is sampled
Document #: 38-05686 Rev. *F
2tCYC
ns
2tCYC
0
ns
ns
Page 8 of 18
[+] Feedback
CY7C1368C
Maximum Ratings
DC Input Voltage ..................................... –0.5V to VDD+0.5V
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Static Discharge Voltage............................................ >2001V
Storage Temperature .................................... –65°C to +150°
(per MIL-STD-883,Method 3015)
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Latch-up Current...................................................... >200 mA
Operating Range
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
Supply Voltage on VDDQ Relative to GND ...... –0.5V to +VDD
Range
DC Voltage Applied to Outputs
in Tri-State ........................................... –0.5V to VDDQ +0.5V
Commercial
Ambient
Temperature
0°C to +70°C
Industrial
–40°C to +85°C
VDD
VDDQ
3.3V –
5%/+10%
2.5V – 5%
to VDD
Electrical Characteristics Over the Operating Range[8, 9]
Parameter
Description
Test Conditions
Min.
Max.
Unit
3.135
3.6
V
for 3.3V I/O
3.135
VDD
V
for 2.5V I/O
2.375
2.625
V
VDD
Power Supply Voltage
VDDQ
I/O Supply Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage[8]
for 3.3V I/O
VIL
Input LOW Voltage[8]
for 2.5V I/O
IX
Input Leakage Current
except ZZ and MODE
GND ≤ VI ≤ VDDQ
Input Current of MODE
Input = VSS
–30
for 3.3V I/O, IOH = –4.0 mA
2.4
for 2.5V I/O, IOH = –1.0 mA
2.0
for 3.3V I/O, IOL = 8.0 mA
V
0.4
for 2.5V I/O, IOL = 1.0 mA
V
0.4
V
2.0
VDD + 0.3V
V
for 2.5V I/O
1.7
VDD + 0.3V
V
for 3.3V I/O
–0.3
0.8
V
–0.3
0.7
V
–5
5
µA
Input = VDD
Input Current of ZZ
V
5
Input = VSS
30
µA
5
µA
4-ns cycle, 250 MHz
250
mA
5-ns cycle, 200 MHz
220
mA
6-ns cycle,166 MHz
180
mA
mA
GND ≤ VI ≤ VDDQ, Output Disabled
Output Leakage Current
IDD
VDD Operating Supply Current VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
µA
µA
–5
Input = VDD
IOZ
µA
–5
Automatic CE
Power-down
Current—TTL Inputs
VDD = Max., Device Deselected,
VIN ≥ VIH or VIN ≤ VIL,
f = fMAX = 1/tCYC
ISB2
Automatic CE
Power-down
Current—CMOS Inputs
VDD = Max., Device Deselected, All speeds
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
f=0
40
mA
ISB3
Automatic CE
Power-down
Current—CMOS Inputs
VDD = Max., Device Deselected,
or VIN ≤ 0.3V or
VIN > VDDQ – 0.3V,
f = fMAX = 1/tCYC
mA
Automatic CE Power-down
Current—TTL Inputs
VDD = Max., Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = 0
ISB1
ISB4
4-ns cycle, 250 MHz
130
5-ns cycle, 200 MHz
120
6-ns cycle,166 MHz
110
4-ns cycle, 250 MHz
120
5-ns cycle, 200 MHz
110
6-ns cycle,166 MHz
100
All speeds
40
mA
Notes:
8. Overshoot: VIH(AC) < VDD+1.5V(Pulse width less than tCYC/2), undershoot: VIL(AC)> –2V(Pulse width less than tCYC/2).
9. Power-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document #: 38-05686 Rev. *F
Page 9 of 18
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CY7C1368C
Capacitance[10]
Parameter
Test Conditions
100 TQFP
Max.
TA = 25°C, f = 1 MHz,
VDD = 3.3V
VDDQ = 2.5V
4
pF
4
pF
4
pF
Description
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CI/O
Input/Output Capacitance
Unit
Thermal Characteristics[10]
Parameter
ΘJA
ΘJC
Description
Test Conditions
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51
Thermal Resistance
(Junction to case)
100 TQFP Package
Unit
29.41
°C/W
6.13
°C/W
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
Z0 = 50Ω
10%
INCLUDING
JIG AND
SCOPE
2.5V I/O Test Load
R = 351Ω
(b)
(c)
10%
(a)
90%
10%
90%
GND
5 pF
VT = 1.25V
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50Ω
Z0 = 50Ω
≤ 1 ns
≤ 1 ns
R = 1667Ω
2.5V
OUTPUT
90%
10%
90%
GND
5 pF
VT = 1.5V
(a)
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50Ω
R =1538Ω
INCLUDING
JIG AND
SCOPE
(b)
≤ 1 ns
≤ 1 ns
(c)
Note:
10. Tested initially and after any design or process change that may affect these parameters
Document #: 38-05686 Rev. *F
Page 10 of 18
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CY7C1368C
Switching Characteristics Over the Operating Range
[15, 16]
–250
Parameter
tPOWER
Description
Min.
[11]
VDD(Typical) to the first Access
–200
Max.
Min.
–166
Max.
Min.
Max.
Unit
1
1
1
ms
Clock
tCYC
Clock Cycle Time
4.0
5.0
6.0
ns
tCH
Clock HIGH
1.8
2.0
2.4
ns
tCL
Clock LOW
1.8
2.0
2.4
ns
Output Times
tCO
Data Output Valid After CLK Rise
tDOH
Data Output Hold After CLK Rise
2.8
1.25
tCLZ
Clock to Low-Z
[12, 13, 14]
1.25
tCHZ
Clock to High-Z[12, 13, 14]
1.25
tOEV
OE LOW to Output Valid
tOELZ
tOEHZ
OE LOW to Output
Low-Z[12, 13, 14]
OE HIGH to Output
High-Z[12, 13, 14]
3.0
1.25
1.25
1.25
2.8
1.25
2.8
0
3.5
1.25
3.0
0
2.8
ns
1.25
3.0
ns
3.5
ns
3.5
ns
0
3.0
ns
ns
3.5
ns
Set-up Times
tAS
Address Set-up Before CLK Rise
tADS
ADSC, ADSP Set-up Before CLK
Rise
tADVS
ADV Set-up Before CLK Rise
tWES
1.4
1.5
1.5
ns
1.5
1.5
ns
1.4
1.5
1.5
ns
GW, OE, BW[A:D] Set-up Before CLK
Rise
1.4
1.5
1.5
ns
tDS
Data Input Set-up Before CLK Rise
1.4
1.5
1.5
ns
tCES
Chip Enable Set-up Before CLK
Rise
1.4
1.5
1.5
ns
tAH
Address Hold After CLK Rise
0.4
0.5
0.5
ns
tADH
ADSP, ADSC Hold After CLK Rise
0.4
0.5
0.5
ns
tADVH
ADV Hold After CLK Rise
0.4
0.5
0.5
ns
tWEH
GW, BWE, BW[A:D] Hold After CLK
Rise
0.4
0.5
0.5
ns
tDH
Data Input Hold After CLK Rise
0.4
0.5
0.5
ns
tCEH
Chip Enable Hold After CLK Rise
0.4
0.5
0.5
ns
Hold Times
Notes:
11. This part has a voltage regulator internally; tpower is the time that the power needs to be supplied above VDD minimum initially before a read or write operation
can be initiated.
12. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
13. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
14. This parameter is sampled and not 100% tested.
15. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25 V when VDDQ = 2.5 V.
16. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05686 Rev. *F
Page 11 of 18
[+] Feedback
CY7C1368C
Switching Waveforms
Read Timing[17]
tCYC
CLK
tCH
tADS
tCL
tADH
ADSP
tADS
tADH
ADSC
tAS
ADDRESS
tAH
A1
A2
tWES
A3
Burst continued with
new base address
tWEH
GW, BWE,BW
[A:D]
tCES
Deselect
cycle
tCEH
CE
tADVS tADVH
ADV
ADV suspends burst
OE
t
Data Out (Q)
High-Z
CLZ
t OEHZ
Q(A1)
tOEV
tCO
t OELZ
tDOH
Q(A2)
t CHZ
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A3)
t CO
Single READ
BURST READ
DON’T CARE
Burst wraps around
to its initial state
UNDEFINED
Note:
17. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document #: 38-05686 Rev. *F
Page 12 of 18
[+] Feedback
CY7C1368C
Switching Waveforms (continued)
Write Timing[17, 18]
t CYC
CLK
tCH
tADS
tCL
tADH
ADSP
tADS
ADSC extends burst
tADH
tADS
tADH
ADSC
tAS
tAH
A1
ADDRESS
A2
A3
Byte write signals are ignored for first cycle when
ADSP initiates burst
tWES tWEH
BWE,
BW[A:D]
tWES tWEH
GW
tCES
tCEH
CE
tADVS tADVH
ADV
ADV suspends burst
OE
t
DS
Data in (D)
High-Z
t
OEHZ
t
DH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Note:
18. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:D] LOW.
Document #: 38-05686 Rev. *F
Page 13 of 18
[+] Feedback
CY7C1368C
Switching Waveforms (continued)
Read/Write Timing[17, 19, 20]
tCYC
CLK
tCL
tCH
tADS
tADH
tAS
tAH
ADSP
ADSC
ADDRESS
A1
A2
A3
A4
A5
A6
D(A5)
D(A6)
tWES tWEH
BWE, BW[A:D]
tCES
tCEH
CE
ADV
OE
tDS
tCO
Data In (D)
tOELZ
High-Z
tCLZ
Data Out (Q)
tDH
High-Z
Q(A1)
Back-to-Back READs
tOEHZ
D(A3)
Q(A2)
Q(A4)
Single WRITE
DON’T CARE
Q(A4+1)
Q(A4+2)
BURST READ
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Notes:
19. The data bus (Q) remains in tri-state following a WRITE cycle unless a new read access is initiated by ADSP or ADSC.
20. GW is HIGH.
Document #: 38-05686 Rev. *F
Page 14 of 18
[+] Feedback
CY7C1368C
Switching Waveforms (continued)
ZZ Mode Timing [21, 22.]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
DESELECT or READ Only
(except ZZ)
Outputs (Q)
High-Z
DON’T CARE
Notes:
21.Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.
22.DQs are in tri-state when exiting ZZ sleep mode.
Document #: 38-05686 Rev. *F
Page 15 of 18
[+] Feedback
CY7C1368C
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz)
166
200
250
Ordering Code
CY7C1368C-166AXC
Package
Diagram
Part and Package Type
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(3 Chip enable)
CY7C1368C-166AJXC
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(2 Chip enable)
CY7C1368C-166AXI
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(3 Chip enable)
CY7C1368C-166AJXI
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(2 Chip enable)
CY7C1368C-200AXC
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(3 Chip enable)
CY7C1368C-200AJXC
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(2 Chip enable)
CY7C1368C-200AXI
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(3 Chip enable)
CY7C1368C-200AJXI
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(2 Chip enable)
CY7C1368C-250AXC
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(3 Chip enable)
CY7C1368C-250AJXC
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(2 Chip enable)
CY7C1368C-250AXI
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(3 Chip enable)
CY7C1368C-250AJXI
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(2 Chip enable)
Document #: 38-05686 Rev. *F
Operating
Range
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Page 16 of 18
[+] Feedback
CY7C1368C
Package Diagram
100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050)
16.00±0.20
1.40±0.05
14.00±0.10
100
81
80
1
20.00±0.10
22.00±0.20
0.30±0.08
0.65
TYP.
30
12°±1°
(8X)
SEE DETAIL
A
51
31
50
0.20 MAX.
0.10
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
0.25
NOTE:
1. JEDEC STD REF MS-026
GAUGE PLANE
0°-7°
R 0.08 MIN.
0.20 MAX.
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0.60±0.15
0.20 MIN.
51-85050-*B
1.00 REF.
DETAIL
A
Intel and Pentium are registered trademarks, and i486 is a trademark, of Intel Corporation. PowerPC is a registered trademark
of IBM. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05686 Rev. *F
Page 17 of 18
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedback
CY7C1368C
Document History Page
Document Title: CY7C1368C 9-Mbit (256K x 32) Pipelined DCD Sync SRAM
Document Number: 38-05686
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
286269
See ECN
PCI
New data sheet
*A
323636
See ECN
PCI
Changed frequency of 225 MHz to 250 MHz
Added tCYC to 4.0 ns for 250 MHz
Changed ΘJA and ΘJC for TQFP Package from 25 and 9 °C/W to 29.41 and
6.13 °C/W respectively
Added Industrial temperature range
Replaced Snooze with Sleep in the ZZ Mode Electrical Characteristics
Added 3 chip enable and 2 chip enable for AX and AJX packages in the
ordering information table
*B
332879
See ECN
PCI
Shaded 250 MHz speed bin in the AC/DC Table and Selection Guide
Added Address Expansion pins in the Pin Definition Table
Modified VOL, VOH test conditions
Corrected VDDQ from (2.5V – 5% to VDD) to (3.3V −5%/+10%) on page# 9
Updated Ordering Information Table
*C
377095
See ECN
PCI
Changed ISB2 from 30 to 40 mA
Modified test condition in note# 9 from VIH < VDD to VIH < VDD
*D
408725
See ECN
RXU
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Converted from Preliminary to Final
Replaced Package Name column with Package Diagram in the Ordering
Information table
Updated the ordering information
*E
429278
See ECN
NXR
Added 2.5VI/O option
Updated Ordering Information Table
*F
501828
See ECN
VKN
Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND
Updated the Ordering Information table.
Document #: 38-05686 Rev. *F
Page 18 of 18
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