CY7C1381S
CY7C1383S
18-Mbit (512K × 36/1M × 18)
Flow-Through SRAM
18-Mbit (512K × 36/1M × 18) Flow-Through SRAM
Features
Functional Description
■
Supports 133 MHz bus operations
■
512K × 36 and 1M × 18 common I/O
■
3.3 V core power supply (VDD)
■
2.5 V or 3.3 V I/O supply (VDDQ)
■
Fast clock-to-output time
❐ 6.5 ns (133 MHz version)
■
Provides high performance 2-1-1-1 access rate
■
User selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■
Separate processor and controller address strobes
■
Synchronous self-timed write
■
Asynchronous output enable
■
Available in JEDEC-standard Pb-free 100-pin TQFP
■
ZZ sleep mode option
The CY7C1381S/CY7C1383S is a 3.3 V, 512K × 36 and 1M × 18
synchronous flow through SRAMs, designed to interface with
high-speed microprocessors with minimum glue logic. Maximum
access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit
on-chip counter captures the first address in a burst and
increments the address automatically for the rest of the burst
access. All synchronous inputs are gated by registers controlled
by a positive edge triggered clock input (CLK). The synchronous
inputs include all addresses, all data inputs, address pipelining
chip enable (CE1), depth-expansion chip enables (CE2 and
CE3), burst control inputs (ADSC, ADSP, and ADV), write
enables (BWx, and BWE), and global write (GW). Asynchronous
inputs include the output enable (OE) and the ZZ pin.
The CY7C1381S/CY7C1383S allows interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the processor
address strobe (ADSP) or the cache controller address strobe
(ADSC) inputs. Address advancement is controlled by the
address advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when address strobe processor (ADSP) or address strobe
controller (ADSC) are active. Subsequent burst addresses can
be internally generated as controlled by the advance pin (ADV).
The CY7C1381S/CY7C1383S operates from a +3.3 V core
power supply while all outputs operate with a +2.5 V or +3.3 V
supply. All inputs and outputs are JEDEC-standard and
JESD8-5-compatible.
Selection Guide
Description
133 MHz
Unit
Maximum Access Time
6.5
ns
Maximum Operating Current
210
mA
Maximum CMOS Standby Current
70
mA
Cypress Semiconductor Corporation
Document Number: 001-43825 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 23, 2016
CY7C1381S
CY7C1383S
Logic Block Diagram – CY7C1381S
ADDRESS
REGISTER
A0, A1, A
A [1:0]
MODE
Q1
ADV
BURST
COUNTER
AND LOGIC
Q0
CLR
CLK
ADSC
ADSP
DQ D , DQP D
DQ D , DQP D
BW D
BYTE
BYTE
WRITE REGISTER
WRITE REGISTER
DQ C , DQP C
DQ C , DQP C
BW C
WRITE REGISTER
WRITE REGISTER
DQ B , DQP B
MEMORY
ARRAY
DQ B , DQP B
BW B
SENSE
AMPS
OUTPUT
BUFFERS
DQs
DQP A
DQP B
DQP C
WRITE REGISTER
DQP D
WRITE REGISTER
DQ A , DQP
DQ A , DQP
BW A
BYTE
A
WRITE REGISTER
BYTE
BWE
WRITE REGISTER
INPUT
REGISTERS
GW
ENABLE
REGISTER
CE1
CE2
CE3
OE
SLEEP
Logic Block Diagram – CY7C1383S
A0,A1,A
ADDRESS
REGISTER
A[1:0]
MODE
BURST Q1
COUNTER AND
ADV
Q0
DQ B ,DQP B
BW B
DQ A ,DQP A
BW A
DQ B ,DQP B
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQs
DQP A
DQP B
DQ A ,DQP A
WRITE DRIVER
BWE
GW
CE 1
CE 2
CE 3
ENABLE
INPUT
REGISTERS
OE
SLEEP
CONTROL
Document Number: 001-43825 Rev. *F
Page 2 of 22
CY7C1381S
CY7C1383S
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Single Read Accesses ................................................ 6
Single Write Accesses Initiated by ADSP ................... 6
Single Write Accesses Initiated by ADSC ................... 6
Burst Sequences ......................................................... 6
Sleep Mode ................................................................. 6
Interleaved Burst Address Table ................................. 7
Linear Burst Address Table ......................................... 7
ZZ Mode Electrical Characteristics .............................. 7
Truth Table ........................................................................ 8
Truth Table for Read/Write .............................................. 9
Truth Table for Read/Write .............................................. 9
Maximum Ratings ........................................................... 10
Operating Range ............................................................. 10
Electrical Characteristics ............................................... 10
Capacitance .................................................................... 11
Document Number: 001-43825 Rev. *F
Thermal Resistance ........................................................ 11
AC Test Loads and Waveforms ..................................... 11
Switching Characteristics .............................................. 12
Timing Diagrams ............................................................ 13
Ordering Information ...................................................... 17
Ordering Code Definitions ......................................... 17
Package Diagrams .......................................................... 18
Acronyms ........................................................................ 19
Document Conventions ................................................. 19
Units of Measure ....................................................... 19
Document History Page ................................................. 20
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC® Solutions ...................................................... 22
Cypress Developer Community ................................. 22
Technical Support ..................................................... 22
Page 3 of 22
CY7C1381S
CY7C1383S
Pin Configurations
NC
NC
NC
CY7C1383S
(1M × 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Document Number: 001-43825 Rev. *F
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
NC
VSSQ
VDDQ
NC
NC
NC
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDDQ
VSSQ
NC
NC
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS/DNU
VDD
NC
VSS
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
VSSQ
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
CY7C1381S
(512K × 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
DQPC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
VSS/DNU
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
A
A
CE1
CE2
NC
NC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
A
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout (3 Chip Enable)
Page 4 of 22
CY7C1381S
CY7C1383S
Pin Definitions
Name
A0, A1, A
I/O
Description
InputAddress Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the
Synchronous CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit
counter.
InputByte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM.
BWA, BWB,
BWC, BWD Synchronous Sampled on the rising edge of CLK.
GW
CLK
InputGlobal Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global write is
Synchronous conducted (all bytes are written, regardless of the values on BW[A:D] and BWE).
InputClock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
CE1
InputChip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
Synchronous and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a
new external address is loaded.
CE2
InputChip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded.
CE3
InputChip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded.
OE
InputOutput Enable, Asynchronous Input, Active LOW. Controls the direction of the I/O pins. When LOW,
Asynchronou the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data
s
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
InputAdvance Input Signal. Sampled on the rising edge of CLK. When asserted, it automatically increments
Synchronous the address in a burst cycle.
ADSP
InputAddress Strobe from Processor, Sampled on the Rising Edge of CLK, Active LOW. When asserted
Synchronous LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is
ignored when CE1 is deasserted HIGH.
ADSC
InputAddress Strobe from Controller, Sampled on the Rising Edge of CLK, Active LOW. When asserted
Synchronous LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
BWE
InputByte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal must be asserted
Synchronous LOW to conduct a byte write.
ZZ
InputZZ Sleep Input. This active HIGH input places the device in a non-time critical sleep condition with data
Asynchronou integrity preserved. For normal operation, this pin must be LOW or left floating. ZZ pin has an internal
s
pull down.
DQs
I/OBidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the
Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX
are placed in a tri-state condition.The outputs are automatically tri-stated during the data portion of a
write sequence, during the first clock when emerging from a deselected state, and when the device is
deselected, regardless of the state of OE.
DQPX
I/OBidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During write
Synchronous sequences, DQPX is controlled by BWX correspondingly.
MODE
VDD
Input-Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating
selects interleaved burst sequence. This is a strap pin and must remain static during device operation.
Mode pin has an internal pull up.
Power Supply Power Supply Inputs to the Core of the Device.
Document Number: 001-43825 Rev. *F
Page 5 of 22
CY7C1381S
CY7C1383S
Pin Definitions (continued)
Name
VDDQ
VSS
VSSQ
NC
VSS/DNU
I/O
Description
I/O Power
Supply
Power Supply for the I/O Circuitry.
Ground
Ground for the Core of the Device.
I/O Ground
–
Ground for the I/O Circuitry.
No Connects. Not internally connected to the die. 36M, 72M, 144M, 288M, 576M, and 1G are address
expansion pins and are not internally connected to the die.
Ground/DNU This pin can be connected to ground or can be left floating.
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (t CDV) is 6.5 ns (133 MHz device).
The CY7C1381S/CY7C1383S supports secondary cache in
systems utilizing a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with the processor address strobe
(ADSP) or the controller address strobe (ADSC). Address
advancement through the burst sequence is controlled by the
ADV input. A two-bit on-chip wraparound burst counter captures
the first address in a burst sequence and automatically
increments the address for the rest of the burst access.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BWX) inputs. A global write enable
(GW) overrides all byte write inputs and writes data to all four
bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
Three synchronous chip selects (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1 is
HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, and (2) ADSP or ADSC is asserted LOW (if the access is
initiated by ADSC, the write inputs must be deasserted during
this first cycle). The address presented to the address inputs is
latched into the address register and the burst counter and/or
control logic, and later presented to the memory core. If the OE
input is asserted LOW, the requested data is available at the data
outputs with a maximum to tCDV after clock rise. ADSP is ignored
if CE1 is HIGH.
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted active,
and (2) ADSP is asserted LOW. The addresses presented are
loaded into the address register and the burst inputs (GW, BWE,
and BWX) are ignored during this first clock cycle. If the write
inputs are asserted active (see Truth Table for Read/Write on
page 9 for appropriate states that indicate a write) on the next
Document Number: 001-43825 Rev. *F
clock rise, the appropriate data is latched and written into the
device. Byte writes are allowed. All IOs are tri-stated during a
byte write. As this is a common I/O device, the asynchronous OE
input signal must be deasserted and the IOs must be tri-stated
prior to the presentation of data to DQs. As a safety precaution,
the data lines are tri-stated once a write cycle is detected,
regardless of the state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BWX)
indicate a write access. ADSC is ignored if ADSP is active LOW.
The addresses presented are loaded into the address register
and the burst counter, the control logic, or both, and delivered to
the memory core The information presented to DQ[A:D] is written
into the specified address location. Byte writes are allowed. All
IOs are tri-stated when a write is detected, even a byte write.
Since this is a common I/O device, the asynchronous OE input
signal must be deasserted and the IOs must be tri-stated prior to
the presentation of data to DQs. As a safety precaution, the data
lines are tri-stated once a write cycle is detected, regardless of
the state of OE.
Burst Sequences
The CY7C1381S/CY7C1383S provides an on-chip two-bit
wraparound burst counter inside the SRAM. The burst counter is
fed by A[1:0], and can follow either a linear or interleaved burst
order. The burst order is determined by the state of the MODE
input. A LOW on MODE selects a linear burst sequence. A HIGH
on MODE selects an interleaved burst order. Leaving MODE
unconnected causes the device to default to a interleaved burst
sequence.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation sleep mode. Two clock cycles
are required to enter into or exit from this sleep mode. While in
this mode, data integrity is guaranteed. Accesses pending when
entering the sleep mode are not considered valid nor is the
completion of the operation guaranteed. The device must be
deselected prior to entering the sleep mode. CE1, CE2, CE3,
ADSP, and ADSC must remain inactive for the duration of tZZREC
after the ZZ input returns LOW.
Page 6 of 22
CY7C1381S
CY7C1383S
Interleaved Burst Address Table
Linear Burst Address Table
(MODE = Floating or VDD)
(MODE = GND)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
00
01
01
00
Fourth
Address
A1:A0
10
11
00
01
10
11
11
10
01
10
11
00
10
11
00
01
10
11
00
01
11
10
01
00
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
IDDZZ
Sleep mode standby current
ZZ > VDD– 0.2 V
–
80
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2 V
–
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2 V
2tCYC
–
ns
tZZI
ZZ active to sleep current
This parameter is sampled
–
2tCYC
ns
tRZZI
ZZ inactive to exit sleep current
This parameter is sampled
0
–
ns
Document Number: 001-43825 Rev. *F
Page 7 of 22
CY7C1381S
CY7C1383S
Truth Table
The truth table for CY7C1381S/CY7C1383S follows. [1, 2, 3, 4, 5]
Cycle Description
Address Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK
DQ
Deselected Cycle, Power Down
None
H
X
X
L
X
L
X
X
X
L–H Tri-State
Deselected Cycle, Power Down
None
L
L
X
L
L
X
X
X
X
L–H Tri-State
Deselected Cycle, Power Down
None
L
X
H
L
L
X
X
X
X
L–H Tri-State
Deselected Cycle, Power Down
None
L
L
X
L
H
L
X
X
X
L–H Tri-State
Deselected Cycle, Power Down
None
X
X
X
L
H
L
X
X
X
L–H Tri-State
Sleep Mode, Power Down
None
X
X
X
H
X
X
X
X
X
Read Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
L
L–H Q
Read Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
H
L–H Tri-State
Write Cycle, Begin Burst
External
L
H
L
L
H
L
X
L
X
L–H D
Read Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
L
L–H Q
Read Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
H
L–H Tri-State
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
L
L–H Q
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L–H Tri-State
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L–H Q
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L–H Tri-State
Write Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L–H D
Write Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L–H D
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L–H Q
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L–H Tri-State
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L–H Q
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L–H Tri-State
Write Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L–H D
Write Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L–H D
X
Tri-State
Notes
1. X = Don't Care, H = Logic HIGH, L = Logic LOW.
2. WRITE = L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
4. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the
ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for
the remainder of the write cycle.
5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive
or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 001-43825 Rev. *F
Page 8 of 22
CY7C1381S
CY7C1383S
Truth Table for Read/Write
The read/write truth table for CY7C1381S follows. [6, 7]
Function
GW
BWE
BWD
BWC
BWB
BWA
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write Byte A (DQA, DQPA)
H
L
H
H
H
L
Write Byte B(DQB, DQPB)
H
L
H
H
L
H
Write Bytes A, B (DQA, DQB, DQPA, DQPB)
H
L
H
H
L
L
Write Byte C (DQC, DQPC)
H
L
H
L
H
H
Write Bytes C, A (DQC, DQA, DQPC, DQPA)
H
L
H
L
H
L
Write Bytes C, B (DQC, DQB, DQPC, DQPB)
H
L
H
L
L
H
Write Bytes C, B, A (DQC, DQB, DQA, DQPC, DQPB,
DQPA)
H
L
H
L
L
L
Write Byte D (DQD, DQPD)
H
L
L
H
H
H
Write Bytes D, A (DQD, DQA, DQPD, DQPA)
H
L
L
H
H
L
Write Bytes D, B (DQD, DQA, DQPD, DQPA)
H
L
L
H
L
H
Write Bytes D, B, A (DQD, DQB, DQA, DQPD, DQPB,
DQPA)
H
L
L
H
L
L
Write Bytes D, B (DQD, DQB, DQPD, DQPB)
H
L
L
L
H
H
Write Bytes D, B, A (DQD, DQC, DQA, DQPD, DQPC,
DQPA)
H
L
L
L
H
L
GW
BWE
BWB
BWA
Write Bytes D, C, A (DQD, DQB, DQA, DQPD, DQPB,
DQPA)
H
L
L
L
Write All Bytes
H
L
L
L
Write All Bytes
L
X
X
X
Read
H
H
X
X
Read
H
L
H
H
Write Byte A – (DQA and DQPA)
H
L
H
L
Write Byte B – (DQB and DQPB)
H
L
L
H
Write All Bytes
H
L
L
L
Write All Bytes
L
X
X
X
Truth Table for Read/Write
The read/write truth table for CY7C1383S follows. [6, 7]
Function
Notes
6. X = Don't Care, H = Logic HIGH, L = Logic LOW.
7. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write is done based on which byte write is active.
Document Number: 001-43825 Rev. *F
Page 9 of 22
CY7C1381S
CY7C1383S
Maximum Ratings
DC Input Voltage ................................ –0.5 V to VDD + 0.5 V
Exceeding the maximum ratings may impair the useful life of the
device. For user guidelines, not tested.
Storage Temperature ............................... –65 °C to +150 °C
Ambient Temperature with
Power Applied ......................................... –55 °C to +125 °C
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(per MIL-STD-883, Method 3015) .......................... > 2001 V
Latch up Current .................................................... > 200 mA
Operating Range
Supply Voltage on VDD Relative to GND .....–0.3 V to +4.6 V
Supply Voltage on VDDQ Relative to GND .... –0.3 V to +VDD
Range
Ambient
Temperature
DC Voltage Applied to Outputs
in Tri-State ........................................–0.5 V to VDDQ + 0.5 V
Commercial
0 °C to +70 °C
VDD
VDDQ
3.3 V– 5% / 2.5 V – 5% to
+ 10%
VDD
Electrical Characteristics
Over the Operating Range
Parameter [8, 9]
Description
VDD
Power Supply Voltage
VDDQ
I/O Supply Voltage
VOH
Output HIGH Voltage
Output LOW Voltage
VOL
Input HIGH Voltage
VIH
IX
Min
Max
Unit
3.135
3.6
V
for 3.3 V I/O
3.135
VDD
V
for 2.5 V I/O
2.375
2.625
V
for 3.3 V I/O, IOH = –4.0 mA
2.4
–
V
for 2.5 V I/O, IOH = –1.0 mA
2.0
–
V
for 3.3 V I/O, IOL = 8.0 mA
–
0.4
V
for 2.5 V I/O, IOL = 1.0 mA
–
0.4
V
for 3.3 V I/O
2.0
VDD + 0.3 V
V
for 2.5 V I/O
1.7
VDD + 0.3 V
V
for 3.3 V I/O
–0.3
0.8
V
for 2.5 V I/O
–0.3
0.7
V
Input Leakage Current except ZZ GND VI VDDQ
and MODE
–5
5
A
Input Current of MODE
–30
–
A
Input LOW Voltage
VIL
[8]
Test Conditions
[8]
Input = VSS
Input = VDD
–
5
A
Input = VSS
–5
–
A
Input = VDD
–
30
A
Output Leakage Current
GND VI VDD, Output Disabled
–5
5
A
VDD Operating Supply Current
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
7.5-ns cycle,
133 MHz
–
210
mA
ISB1
Automatic CE Power Down
Current – TTL Inputs
Max VDD, Device Deselected,
VIN VIH or VIN VIL, f = fMAX,
inputs switching
7.5-ns cycle,
133 MHz
–
140
mA
ISB2
Automatic CE Power Down
Current – CMOS Inputs
7.5-ns cycle,
Max VDD, Device Deselected,
VIN VDD – 0.3 V or VIN 0.3 V, 133 MHz
f = 0, inputs static
–
70
mA
ISB3
Automatic CE Power Down
Current – CMOS Inputs
Max VDD, Device Deselected,
7.5-ns cycle,
VIN VDDQ – 0.3 V or VIN 0.3 V, 133 MHz
f = fMAX, inputs switching
–
130
mA
Input Current of ZZ
IOZ
IDD
[10]
Notes
8. Overshoot: VIH(AC) < VDD + 1.5 V (pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (pulse width less than tCYC/2).
9. Tpower up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
10. The operation current is calculated with 50% read cycle and 50% write cycle.
Document Number: 001-43825 Rev. *F
Page 10 of 22
CY7C1381S
CY7C1383S
Electrical Characteristics (continued)
Over the Operating Range
Parameter [8, 9]
Description
Test Conditions
Automatic CE Power Down
Current – TTL Inputs
ISB4
7.5-ns cycle,
133 MHz
Max VDD, Device Deselected,
VIN VDD – 0.3 V or VIN 0.3 V,
f = 0, inputs static
Min
Max
Unit
–
80
mA
Capacitance
Parameter [11]
100-pin TQFP
Package
Unit
5
pF
5
pF
5
pF
Test Conditions
100-pin TQFP
Package
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
28.66
°C/W
4.08
°C/W
Description
Test Conditions
CIN
Input capacitance
TA = 25 °C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 2.5 V
CCLK
Clock input capacitance
CIO
Input/Output capacitance
Thermal Resistance
Parameter [11]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317
3.3 V
OUTPUT
OUTPUT
RL = 50
Z0 = 50
VT = 1.5V
(a)
INCLUDING
JIG AND
SCOPE
Z0 = 50
VT = 1.25V
(a)
R = 351
10%
(c)
ALL INPUT PULSES
VDDQ
INCLUDING
JIG AND
SCOPE
1 ns
(b)
GND
5 pF
90%
10%
90%
1 ns
R = 1667
2.5 V
OUTPUT
RL = 50
GND
5 pF
2.5 V I/O Test Load
OUTPUT
ALL INPUT PULSES
VDDQ
R = 1538
(b)
10%
90%
10%
90%
1 ns
1 ns
(c)
Note
11. Tested initially and after any design or process change that may affect these parameters.
Document Number: 001-43825 Rev. *F
Page 11 of 22
CY7C1381S
CY7C1383S
Switching Characteristics
Over the Operating Range
Parameter [12, 13]
tPOWER
Description
VDD(Typical) to the first Access [14]
133 MHz
Unit
Min
Max
1
–
ms
Clock
tCYC
Clock Cycle Time
7.5
–
ns
tCH
Clock HIGH
2.1
–
ns
tCL
Clock LOW
2.1
–
ns
Output Times
tCDV
Data Output Valid After CLK Rise
–
6.5
ns
tDOH
Data Output Hold After CLK Rise
2.0
–
ns
2.0
–
ns
0
4.0
ns
–
3.2
ns
0
–
ns
–
4.0
ns
[15, 16, 17]
tCLZ
Clock to Low Z
tCHZ
Clock to High Z [15, 16, 17]
tOEV
OE LOW to Output Valid
tOELZ
tOEHZ
OE LOW to Output Low Z
[15, 16, 17]
OE HIGH to Output High Z
[15, 16, 17]
Setup Times
tAS
Address Setup Before CLK Rise
1.5
–
ns
tADS
ADSP, ADSC Setup Before CLK Rise
1.5
–
ns
tADVS
ADV Setup Before CLK Rise
1.5
–
ns
tWES
GW, BWE, BW[A:D] Setup Before CLK Rise
1.5
–
ns
tDS
Data Input Setup Before CLK Rise
1.5
–
ns
tCES
Chip Enable Setup
1.5
–
ns
tAH
Address Hold After CLK Rise
0.5
–
ns
tADH
ADSP, ADSC Hold After CLK Rise
0.5
–
ns
tWEH
GW, BWE, BW[A:D] Hold After CLK Rise
0.5
–
ns
tADVH
ADV Hold After CLK Rise
0.5
–
ns
tDH
Data Input Hold After CLK Rise
0.5
–
ns
tCEH
Chip Enable Hold After CLK Rise
0.5
–
ns
Hold Times
Notes
12. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
13. Test conditions shown in (a) of Figure 2 on page 11 unless otherwise noted.
14. This part has a voltage regulator internally; tPOWER is the time that the power is supplied above VDD(minimum) initially, before a read or write operation can be initiated.
15. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 2 on page 11. Transition is measured ± 200 mV from steady-state voltage.
16. At any voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus.
These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High Z
prior to Low Z under the same system condition.
17. This parameter is sampled and not 100% tested.
Document Number: 001-43825 Rev. *F
Page 12 of 22
CY7C1381S
CY7C1383S
Timing Diagrams
Figure 3. Read Cycle Timing [18]
tCYC
CLK
t
t ADS
CH
t CL
tADH
ADSP
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
t
GW, BWE,BW
WES
t
WEH
X
t CES
Deselect Cycle
t CEH
CE
t
ADVS
t
ADVH
ADV
ADV suspends burst
OE
t OEV
t OEHZ
t CLZ
Data Out (Q)
High-Z
Q(A1)
t CDV
t OELZ
t CHZ
t DOH
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
t CDV
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
Note
18. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document Number: 001-43825 Rev. *F
Page 13 of 22
CY7C1381S
CY7C1383S
Timing Diagrams (continued)
Figure 4. Write Cycle Timing [19, 20]
t CYC
CLK
t
t ADS
CH
t
CL
tADH
ADSP
t ADS
ADSC extends burst
tADH
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
A3
Byte write signals are ignored for first cycle when
ADSP initiates burst
t WES tWEH
BWE,
BW X
t
WES
t
WEH
GW
t CES
tCEH
CE
t ADVS tADVH
ADV
ADV suspends burst
OE
t
Data in (D)
High-Z
t
DS
t
DH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
OEHZ
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Notes
19. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
20. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.
Document Number: 001-43825 Rev. *F
Page 14 of 22
CY7C1381S
CY7C1383S
Timing Diagrams (continued)
Figure 5. Read/Write Cycle Timing [21, 22, 23]
tCYC
CLK
t
t ADS
CH
t
CL
tADH
ADSP
ADSC
t AS
A1
ADDRESS
tAH
A2
A3
A4
t
BWE, BW
WES
t
A5
A6
D(A5)
D(A6)
WEH
X
t CES
tCEH
CE
ADV
OE
t DS
Data In (D)
Data Out (Q)
High-Z
t
OEHZ
Q(A1)
tDH
t OELZ
D(A3)
tCDV
Q(A4)
Q(A2)
Back-to-Back READs
Single WRITE
Q(A4+1)
BURST READ
DON’T CARE
Q(A4+2)
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Notes
21. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
22. The data bus (Q) remains in high Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
23. GW is HIGH.
Document Number: 001-43825 Rev. *F
Page 15 of 22
CY7C1381S
CY7C1383S
Timing Diagrams (continued)
Figure 6. ZZ Mode Timing [24, 25]
CLK
t
ZZ
I
t ZZREC
ZZ
t ZZI
SUPPLY
I
DDZZ
t RZZI
ALL INPUTS
DESELECT or READ Only
(except ZZ)
Outputs (Q)
High-Z
DON’T CARE
Notes
24. Device must be deselected when entering ZZ mode. See Truth Table on page 8 for all possible signal conditions to deselect the device.
25. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 001-43825 Rev. *F
Page 16 of 22
CY7C1381S
CY7C1383S
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit
www.cypress.com for actual products offered.
Speed
(MHz)
133
Package
Diagram
Ordering Code
CY7C1381S-133AXC
Part and Package Type
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Operating
Range
Commercial
CY7C1383S-133AXC
Ordering Code Definitions
CY
7
C 138X S - 133
A
X
C
Temperature Range:
C = Commercial
Pb-free
Package Type:
A = 100-pin TQFP
Frequency Range: 133 MHz
Die Revision
Part Identifier: 138X = 1381 or 1383
1381 = FT, 512Kb × 36 (18Mb)
1383 = FT, 1Mb × 36 (18Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-43825 Rev. *F
Page 17 of 22
CY7C1381S
CY7C1383S
Package Diagrams
Figure 7. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
51-85050 *E
Document Number: 001-43825 Rev. *F
Page 18 of 22
CY7C1381S
CY7C1383S
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CMOS
Complementary Metal Oxide Semiconductor
I/O
Input/Output
°C
degree Celsius
LSB
Least Significant Bit
MHz
megahertz
MSB
Most Significant Bit
µA
microampere
OE
Output Enable
mA
milliampere
SRAM
Static Random Access Memory
mm
millimeter
TQFP
Thin Quad Flat Pack
ms
millisecond
TTL
Transistor-Transistor Logic
mV
millivolt
WE
Write Enable
ns
nanosecond
Document Number: 001-43825 Rev. *F
Symbol
Unit of Measure
ohm
%
percent
pF
picofarad
V
volt
W
watt
Page 19 of 22
CY7C1381S
CY7C1383S
Document History Page
Document Title: CY7C1381S/CY7C1383S, 18-Mbit (512K × 36/1M × 18) Flow-Through SRAM
Document Number: 001-43825
Rev.
ECN No.
Issue Date
Orig. of
Change
**
1898286
See ECN
VKN /
AESA
New data sheet.
*A
2082246
See ECN
JASM
Changed status from Preliminary to Final.
*B
2950645
06/11/2010
VKN
Updated Ordering Information (Removed invalid parts).
Updated Package Diagrams.
*C
3196490
03/15/2011
NJY
Added Ordering Code Definitions.
Updated Package Diagrams.
Added Acronyms and Units of Measure.
Updated to new template.
*D
3569737
04/02/2012
PRIT
Updated Functional Description (Removed the Note “For best practices or
recommendations, please refer to the Cypress application note AN1064,
SRAM System Design Guidelines on www.cypress.com.” and its reference,
removed the Note “CE3, CE2 are for 100-pin TQFP and 165-ball FBGA
packages only. 119-ball BGA is offered only in 1 chip enable.” and its
reference).
Updated Pin Configurations (Removed 119-ball BGA and 165-ball FBGA
package related information).
Updated Pin Definitions (Removed the Note “CE3, CE2 are for 100-pin TQFP
and 165-ball FBGA packages only. 119-ball BGA is offered only in 1 chip
enable.” and its references, removed JTAG related information).
Updated Functional Overview (Removed the Note “CE3, CE2 are for 100-pin
TQFP and 165-ball FBGA packages only. 119-ball BGA is offered only in 1 chip
enable.” and its references).
Removed IEEE 1149.1 Serial Boundary Scan (JTAG).
Removed TAP Controller State Diagram.
Removed TAP Controller Block Diagram.
Removed TAP Timing.
Removed TAP AC Switching Characteristics.
Removed 3.3 V TAP AC Test Conditions.
Removed 3.3 V TAP AC Output Load Equivalent.
Removed 2.5 V TAP AC Test Conditions.
Removed 2.5 V TAP AC Output Load Equivalent.
Removed TAP DC Electrical Characteristics and Operating Conditions.
Removed Identification Register Definitions.
Removed Scan Register Sizes.
Removed Identification Codes.
Removed Boundary Scan Order (corresponding to 119-ball BGA and 165-ball
FBGA).
Updated Operating Range (Removed Industrial Range).
Updated Electrical Characteristics (Removed 100 MHz frequency related information).
Updated Capacitance (Removed 119-ball BGA and 165-ball FBGA package
related information).
Updated Thermal Resistance (Removed 119-ball BGA and 165-ball FBGA
package related information).
Updated Switching Characteristics (Removed 100 MHz frequency related
information).
Updated Package Diagrams (Removed 119-ball BGA and 165-ball FBGA
package related information).
*E
3975671
04/20/2013
PRIT
Replaced all instances of IO with I/O across the document.
Completing Sunset Review.
Document Number: 001-43825 Rev. *F
Description of Change
Page 20 of 22
CY7C1381S
CY7C1383S
Document History Page (continued)
Document Title: CY7C1381S/CY7C1383S, 18-Mbit (512K × 36/1M × 18) Flow-Through SRAM
Document Number: 001-43825
Rev.
ECN No.
Issue Date
Orig. of
Change
*F
5187232
03/23/2016
PRIT
Document Number: 001-43825 Rev. *F
Description of Change
Updated Package Diagrams:
spec 51-85050 – Changed revision from *D to *E.
Updated to new template.
Completing Sunset Review.
Page 21 of 22
CY7C1381S
CY7C1383S
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/clocks
cypress.com/interface
cypress.com/powerpsoc
cypress.com/memory
PSoC
cypress.com/psoc
Touch Sensing
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/support
cypress.com/touch
USB Controllers
Wireless/RF
cypress.com/psoc
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation 2008-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you under its copyright rights in the Software, a personal, non-exclusive, nontransferable license (without the right to sublicense) (a) for Software provided in source code form, to modify
and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either
directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units. Cypress also grants you a personal, non-exclusive, nontransferable, license (without the right
to sublicense) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely to the minimum
extent that is necessary for you to exercise your rights under the copyright license granted in the previous sentence. Any other use, reproduction, modification, translation, or compilation of the Software
is prohibited.
CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes to this document without further notice. Cypress does not
assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or
programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application
made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of
weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or
hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any
component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole
or in part, and Company shall and hereby does release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. Company shall indemnify
and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress
products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-43825 Rev. *F
Intel and Pentium are registered trademarks, and i486 is a trademark of Intel Corporation.
Revised March 23, 2016
Page 22 of 22
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