CY7C1399BN

CY7C1399BN 256K (32K x 8) Static RAM Features • Temperature Ranges — Industrial: –40°C to 85°C — Automotive-A: –40°C to 85°C • Single 3.3V power supply • Ideal for low-voltage cache memory applications • High speed: 12 ns • Low active power — 180 mW (max.) • Low-power alpha immune 6T cell • Available in Pb-free and non Pb-free Plastic SOJ and TSOP I packages expansion is provided by an active LOW Chip Enable (CE) and active LOW Output Enable (OE) and tri-state drivers. The device has an automatic power-down feature, reducing the power consumption by more than 95% when deselected. An active LOW Write Enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins is present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and Write Enable (WE) is HIGH. The CY7C1399BN is available in 28-pin standard 300-mil-wide SOJ and TSOP Type I packages. Functional Description[1] The CY7C1399BN is a high-performance 3.3V CMOS Static RAM organized as 32,768 words by 8 bits. Easy memory Logic Block Diagram Pin Configurations SOJ Top View A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 INPUT BUFFER I/O0 I/O1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 CE WE OE ROW DECODER I/O2 SENSE AMPS 32K x 8 ARRAY I/O3 I/O4 I/O5 COLUMN DECODER POWER DOWN I/O6 I/O7 A 10 A 11 A 12 A 13 Selection Guide -12 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (µA) Commercial Commercial (L) Industrial Automotive-A 12 55 500 50 500 -15 15 50 500 50 500 500 -20 20 45 500 50 Note: 1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com. A 14 Cypress Semiconductor Corporation Document #: 001-06490 Rev. *A • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 31, 2006 [+] [+] Feedback CY7C1399BN Pin Configuration TSOP Top View OE A1 A2 A3 A4 WE VCC A5 A6 A7 A8 A9 A10 A11 22 23 24 25 26 27 28 1 2 3 4 5 6 7 21 20 19 18 17 16 15 14 13 12 11 10 9 8 A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A14 A13 A12 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC to Relative GND[2] .... –0.5V to +4.6V DC Voltage Applied to Outputs in High Z State[2] ....................................–0.5V to VCC + 0.5V DC Input Voltage[2] .................................–0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... >200 mA Operating Range Range Commercial Industrial Automotive-A Ambient Temperature 0°C to +70°C –40°C to +85°C –40°C to +85°C VCC 3.3V ±300 mV Electrical Characteristics Over the Operating Range[1] -12 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[2] Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current— TTL Inputs Automatic CE Power-Down Current— CMOS Inputs[3] GND ≤ VI ≤ VCC, Output Disabled VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE ≥ VIH, VIN ≥ VIH, or VIN ≤ VIL, f = fMAX Comm’l Comm’l (L) Ind’l Auto-A ISB2 Max. VCC, CE ≥ VCC – 0.3V, Comm’l VIN ≥ VCC – 0.3V, or VIN ≤ 0.3V, Comm’l (L) WE ≥VCC – 0.3V or WE ≤ 0.3V, Ind’l f = fMAX Auto-A Notes: 2. Minimum voltage is equal to – 2.0V for pulse durations of less than 20 ns. 3. Device draws low standby current regardless of switching on the addresses. -15 Min. Max. 2.4 0.4 0.4 2.2 –0.3 –1 –5 VCC + 0.3V 0.8 +1 +5 50 5 4 5 5 500 50 500 500 50 500 500 2.2 2.4 -20 Min. Max. Unit V 0.4 VCC + 0.3V 0.8 +1 +5 45 5 V V V µA µA mA mA mA Test Conditions VCC = Min., IOH = –2.0 mA VCC = Min., IOL = 4.0 mA Min. 2.4 2.2 –0.3 –1 –5 Max. VCC + 0.3V 0.8 +1 +5 55 5 4 5 –0.3 –1 –5 500 µA µA µA µA Document #: 001-06490 Rev. *A Page 2 of 8 [+] [+] Feedback CY7C1399BN Capacitance[4] Parameter CIN: Addresses CIN: Controls COUT Output Capacitance Description Input Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max. 5 6 6 Unit pF pF pF AC Test Loads and Waveforms[5] 3.3V OUTPUT INCLUDING JIG AND SCOPE CL R2 351Ω R1 317 Ω 3.0V GND 10% ALL INPUT PULSES 90% 90% 10% ≤ 3 ns Equivalent to: OUTPUT THÉVENINEQUIVALENT 167Ω 1.73V ≤ 3 ns Switching Characteristics Over the Operating Range[5] -12 Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z[6] Z[6, 7] 3 6 0 12 12 8 8 0 0 8 7 0 7 3 3 15 10 10 0 0 10 8 0 7 3 0 15 20 12 12 0 0 12 10 0 7 Z[6, 7] 0 5 3 7 0 20 OE HIGH to High CE HIGH to High 3 12 5 0 6 3 7 12 12 3 15 6 0 6 15 15 3 20 7 20 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Min. -15 Max. Min. -20 Max. Unit CE LOW to Low Z[6] CE LOW to Power-Up CE HIGH to Power-Down Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE LOW to High Z [8] [6] Write Cycle[8, 9] WE HIGH to Low Z Notes: 4. Tested initially and after any design or process changes that may affect these parameters. 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and capacitance CL = 30 pF. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. tHZOE, tHZCE, tHZWE are specified with CL = 5 pF as in AC Test Loads. Transition is measured ±500 mV from steady state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 001-06490 Rev. *A Page 3 of 8 [+] [+] Feedback CY7C1399BN Data Retention Characteristics (Over the Operating Range - L version only) Parameter VDR ICCDR tCDR tR Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = VDR = 2.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V Conditions Min. 2.0 0 0 tRC 20 Max. Unit V µA ns ns Data Retention Waveform DATA RETENTION MODE VCC CE 3.0V tCDR VDR > 2V 3.0V tR Switching Waveforms Read Cycle No. 1[10, 11] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Read Cycle No. 2[11, 12] tRC CE tACE OE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZOE tHZCE DATA VALID tPD DATA OUT HIGH IMPEDANCE ICC 50% ISB Notes: 10. Device is continuously selected. OE, CE = VIL. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE transition LOW. Document #: 001-06490 Rev. *A Page 4 of 8 [+] [+] Feedback CY7C1399BN Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled)[8, 13, 14] tWC ADDRESS CE tAW WE tSA tPWE tHA OE tSD DATA I/O NOTE 15 tHZOE DATAINVALID tHD Write Cycle No. 2 (CE Controlled)[8, 13, 14] tWC ADDRESS CE tSA tAW WE tSD DATA I/O DATAINVALID tHD tHA tSCE Write Cycle No. 3 (WE Controlled, OE LOW)[9, 14] tWC ADDRESS CE tAW WE tSA tHA tSD DATA I/O NOTE 15 tHZWE Notes: 13. Data I/O is high impedance if OE = VIH. 14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 15. During this period, the I/Os are in the output state and input signals should not be applied. tHD DATA IN VALID tLZWE Document #: 001-06490 Rev. *A Page 5 of 8 [+] [+] Feedback CY7C1399BN Truth Table CE H L L L WE X H L H OE X L X H Input/Output High Z Data Out Data In High Z Read Write Deselect, Output Disabled Mode Deselect/Power-Down Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 12 Ordering Code CY7C1399BN-12VC CY7C1399BN-12VXC CY7C1399BN-12ZC CY7C1399BN-12ZXC CY7C1399BNL-12ZC CY7C1399BNL-12ZXC CY7C1399BN-12VXI 15 CY7C1399BN-15VC CY7C1399BN-15VXC CY7C1399BN-15ZC CY7C1399BN-15ZXC CY7C1399BNL-15ZXC CY7C1399BNL-15VXC CY7C1399BN-15VI CY7C1399BN-15VXI CY7C1399BN-15ZI CY7C1399BN-15ZXI CY7C1399BN-15VXA 20 CY7C1399BN-20ZXC 51-85031 51-85071 51-85071 51-85031 51-85071 51-85031 51-85071 Package Diagram 51-85031 Package Type 28-Lead Molded SOJ 28-Lead Molded SOJ (Pb-free) 28-Lead TSOP I 28-Lead TSOP I (Pb-free) 28-Lead TSOP I 28-Lead TSOP I (Pb-free) 28-Lead Molded SOJ (Pb-free) 28-Lead Molded SOJ 28-Lead Molded SOJ (Pb-free) 28-Lead TSOP I 28-Lead TSOP I (Pb-free) 28-Lead TSOP I (Pb-free) 28-Lead Molded SOJ (Pb-free) 28-Lead Molded SOJ 28-Lead Molded SOJ (Pb-free) 28-Lead TSOP I 28-Lead TSOP I (Pb-free) 28-Lead Molded SOJ (Pb-free) 28-Lead TSOP I (Pb-free) Automotive-A Commercial Industrial Industrial Commercial Operating Range Commercial Please contact local sales representative regarding availability of these parts. Document #: 001-06490 Rev. *A Page 6 of 8 [+] [+] Feedback CY7C1399BN Package Diagrams NOTE : 1. JEDEC STD REF MO088 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.006 in (0.152 mm) PER SIDE 3. DIMENSIONS IN INCHES MIN. MAX. 28-Lead (300-Mil) Molded SOJ (51-85031) PIN 1 ID 14 1 DETAIL A EXTERNAL LEAD DESIGN 0.291 0.300 0.330 0.350 0.013 0.019 OPTION 1 OPTION 2 0.026 0.032 0.014 0.020 15 28 0.697 0.713 0.120 0.140 0.050 TYP. SEATING PLANE 0.007 0.013 0.004 A 0.025 MIN. 0.262 0.272 51-85031-*C 28-Lead TSOP 1 (8x13.4 mm) (51-85071) 51-85071-*G All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-06490 Rev. *A Page 7 of 8 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] [+] Feedback CY7C1399BN Document History Page Document Title: CY7C1399BN 256K (32K x 8) Static RAM Document Number: 001-06490 REV. ** *A ECN NO. 423877 498575 ISSUE DATE See ECN See ECN ORIG. OF CHANGE NXR NXR New Data Sheet Added Automotive-A range Removed IOS parameter from DC Electrical Characteristics table Updated Ordering Information table. DESCRIPTION OF CHANGE Document #: 001-06490 Rev. *A Page 8 of 8 [+] [+] Feedback