CY7C1399BN-15ZXIT

CY7C1399BN 256 K (32 K × 8) Static RAM Features Functional Description ■ Temperature Ranges ❐ Industrial: –40 °C to 85 °C ❐ Commercial: 0 °C to 70 °C ❐ Automotive-A: –40 °C to 85 °C ■ Single 3.3 V power supply The CY7C1399BN is a high-performance 3.3 V CMOS Static RAM organized as 32,768 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE) and active LOW Output Enable (OE) and tristate drivers. The device has an automatic power-down feature, reducing the power consumption by more than 95% when deselected. ■ Ideal for low-voltage cache memory applications ■ High speed: 12 ns ■ Low active power ❐ 180 mW (max) ■ Low-power alpha immune 6T cell ■ Available in pb-free and non pb-free plastic SOJ and TSOPI packages An active LOW Write Enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins is present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and Write Enable (WE) is HIGH. The CY7C1399BN is available in 28-pin standard 300-mil-wide SOJ and TSOP Type I packages. Logic Block Diagram g I/O0 INPUT BUFFER I/O1 ROW DECODER I/O2 SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 32K x 8 ARRAY I/O3 I/O4 I/O5 CE WE I/O6 POWER DOWN COLUMN DECODER I/O7 Cypress Semiconductor Corporation Document #: 001-06490 Rev. *D • A 14 A 12 A 13 A 11 A 10 OE 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 26, 2011 CY7C1399BN Selection Guide Description –12 –15 Maximum access time (ns) 12 15 Maximum operating current (mA) 55 50 Commercial 500 – Commercial (L) 50 – Industrial 500 500 – 500 Maximum CMOS standby current (μA) Automotive-A Pin Configuration SOJ Top View TSOP Top View OE A1 A2 A3 A4 WE VCC A5 A6 A7 A8 A9 A10 A11 Document #: 001-06490 Rev. *D 22 23 24 25 26 27 28 1 2 3 4 5 6 7 21 20 19 18 17 16 15 14 13 12 11 10 9 8 A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A14 A13 A12 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 Page 2 of 12 CY7C1399BN Maximum Ratings Static discharge voltage........................................... >2001 V (per MIL-STD-883, Method 3015) Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Latch-up current ..................................................... >200 mA Storage temperature ................................ –65 °C to +150 °C Ambient temperature with power applied ........................................... –55 °C to +125 °C Operating Range Supply voltage on VCC to relative GND[1] .....–0.5 V to +4.6 V Range Ambient Temperature VCC DC voltage applied to outputs in high Z State[1] .................................. –0.5 V to VCC + 0.5 V Commercial 0 °C to +70 °C 3.3 V ±300 mV DC input voltage[1] ............................... –0.5 V to VCC + 0.5 V Industrial –40 °C to +85 °C Automotive-A –40 °C to +85 °C Output current into outputs (LOW) .............................. 20 mA Electrical Characteristics Over the Operating Range[1] Parameter Description –12 Test Conditions Min –15 Max Unit Max Min 2.4 – 2.4 – V – 0.4 – 0.4 V VOH Output HIGH voltage Min VCC, IOH = –2.0 mA VOL Output LOW voltage Min VCC, IOL = 4.0 mA VIH Input HIGH voltage 2.2 VCC + 0.3 V 2.2 VCC + 0.3 V V VIL[1] Input LOW voltage –0.3 0.8 –0.3 0.8 V IIX Input leakage current –1 +1 –1 +1 μA IOZ Output leakage current GND ≤ VIN ≤ VCC, Output disabled –5 +5 –5 +5 μA ICC VCC operating supply current – 55 – 50 mA ISB1 Automatic CE Max VCC, CE ≥ VIH, power-down current— VIN ≥ VIH, or VIN ≤ VIL, TTL inputs f = fMAX Comm’l – 5 – – mA Comm’l (L) – 4 – – mA Ind’l – 5 – 5 mA Auto-A – – – 5 mA – 500 – – μA – 50 – – μA – 500 – 500 μA – – – 500 μA ISB2 Max VCC, IOUT = 0 mA, f = fMAX = 1/tRC Automatic CE Max VCC, CE ≥ VCC – 0.3 V, Comm’l Power-down current— VIN ≥ VCC – 0.3 V, or VIN ≤ 0.3 V, Comm’l (L) CMOS inputs[2] WE ≥VCC – 0.3 V or WE ≤ 0.3 V, Ind’l f = fMAX Auto-A Notes 1. Minimum voltage is equal to – 2.0 V for pulse durations of less than 20 ns. 2. Device draws low standby current regardless of switching on the addresses. Document #: 001-06490 Rev. *D Page 3 of 12 CY7C1399BN Capacitance Parameter[5] Description CIN: Addresses Input capacitance CIN: Controls COUT Test Conditions TA = 25 °C, f = 1 MHz, VCC = 3.3 V Output capacitance Max Unit 5 pF 6 pF 6 pF AC Test Loads and Waveforms[4] R1 317 Ω ALL INPUT PULSES 3.3 V 3.0 V OUTPUT INCLUDING JIG AND SCOPE 10% CL R2 351 Ω GND ≤ 3 ns 90% Equivalent to: 90% 10% THÉVENINEQUIVALENT 167 Ω OUTPUT 1.73 V ≤ 3 ns Notes 3. Tested initially and after any design or process changes that may affect these parameters. 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH and capacitance CL = 30 pF. Document #: 001-06490 Rev. *D Page 4 of 12 CY7C1399BN Switching Characteristics Over the Operating Range[6] Parameter Description –12 Min –15 Max Min Max Unit Read Cycle tRC Read cycle time 12 – 15 – ns tAA Address to data valid – 12 – 15 ns tOHA Data hold from address change 3 – 3 – ns tACE CE LOW to data valid – 12 – 15 ns tDOE OE LOW to data valid – 5 – 6 ns tLZOE OE LOW to low Z[7] 0 – 0 – ns – 5 – 6 ns 3 – 3 – ns [7, 8] tHZOE OE HIGH to high Z tLZCE Z[7] CE LOW to low Z[7, 8] tHZCE CE HIGH to high – 6 – 7 ns tPU CE LOW to power-up 0 – 0 – ns CE HIGH to power-down – 12 – 15 ns tWC Write cycle time 12 – 15 – ns tSCE CE LOW to write end 8 – 10 – ns tAW Address setup to write end 8 – 10 – ns tHA Address hold from write end 0 – 0 – ns tSA Address setup to write start 0 – 0 – ns tPWE WE pulse width 8 – 10 – ns tSD Data setup to write end 7 – 8 – ns tHD Data hold from write end – ns tPD Write Cycle[9, 10] 0 – 0 tHZWE WE low to high Z[9] – 7 – 7 ns tLZWE WE high to low Z[7] 3 – 3 – ns Notes 5. Tested initially and after any design or process changes that may affect these parameters. 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH and capacitance CL = 30 pF. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. tHZOE, tHZCE, tHZWE are specified with CL = 5 pF as in AC Test Loads. Transition is measured ±500 mV from steady state voltage. 9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 10. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 001-06490 Rev. *D Page 5 of 12 CY7C1399BN Data Retention Characteristics (Over the Operating Range - L version only) Parameter Description VDR VCC for data retention ICCDR Data retention current tCDR Chip deselect to data retention time tR Operation recovery time Conditions VCC = VDR = 2.0 V, CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V Min Max Unit 2.0 – V 0 20 μA 0 – ns tRC – ns Data Retention Waveform DATA RETENTION MODE VDR > 2 V 3.0 V VCC 3.0 V tR tCDR CE Switching Waveforms Figure 1. Read Cycle No. 1[11, 12] tRC ADDRESS tAA tOHA DATA I/O PREVIOUS DATA VALID DATA OUT VALID Figure 2. Read Cycle No. 2[12, 13] tRC CE tACE OE DATA I/O tDOE tLZOE HIGH IMPEDANCE tHZOE tHZCE HIGH IMPEDANCE DATA OUT VALID tLZCE VCC SUPPLY CURRENT tPD tPU ICC 50% 50% ISB Notes 11. Device is continuously selected. OE, CE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. Document #: 001-06490 Rev. *D Page 6 of 12 CY7C1399BN Switching Waveforms (continued) Figure 3. Write Cycle No. 1 (WE Controlled)[9, 14, 15] tWC ADDRESS CE tAW tHA tSA WE tPWE OE tSD DATA I/O NOTE 16 tHD DATA IN VALID tHZOE Figure 4. Write Cycle No. 2 (CE Controlled)[9, 14, 15] tWC ADDRESS tSCE CE tSA tAW tHA WE tSD DATA I/O tHD DATA IN VALID Figure 5. Write Cycle No. 3 (WE Controlled, OE LOW)[10, 15] tWC ADDRESS CE tAW WE tHA tSA tSD DATA I/O tHD DATA IN VALID NOTE 16 tHZWE tLZWE Notes 14. Data I/O is high impedance if OE = VIH. 15. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 16. During this period, the I/Os are in the output state and input signals should not be applied. Document #: 001-06490 Rev. *D Page 7 of 12 CY7C1399BN Truth Table CE WE OE Input/Output Mode Power H X X High Z Deselect/Power-down Standby (ISB) L H L Data Out Read Active (ICC) L L X Data In Write Active (ICC) L H H High Z Deselect, Output disabled Active (ICC) Ordering Information Cypress offers other versions of this type of product in many different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Speed (ns) 12 Ordering Code Package Diagram CY7C1399BN-12VXC 51-85031 CY7C1399BN-12ZXC 51-85071 CY7C1399BNL-12ZXC 15 Package Type 28-pin molded SOJ (Pb-free) Operating Range Commercial 28-pin TSOP I (Pb-free) 28-pin TSOP I (Pb-free) CY7C1399BN-12VXI 51-85031 28-pin molded SOJ (Pb-free) Industrial CY7C1399BN-15ZXI 51-85071 28-pin TSOP I (Pb-free) Industrial CY7C1399BN-15VXA 51-85031 28-pin molded SOJ (Pb-free) Automotive-A Contact your local sales representative regarding availability of these parts. Ordering Code Definitions CY 7 C 1 399 BN L - ## X V C Temperature Range: A = Automotive-A C = Commercial I = Industrial Package Type: V = Molded SOJ Z = TSOP I X = Pb-free Access time in ns L = Low power Process Technology BN = 0.25 µm 399 = 256-Kb density with data width × 8 bits 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS 7 = SRAM CY = Cypress Document #: 001-06490 Rev. *D Page 8 of 12 CY7C1399BN Package Diagrams Figure 6. 28-pin (300-Mil) Molded SOJ (51-85031) 51-85031 *E Figure 7. 28-pin TSOP 1 (8 × 13.4 mm) (51-85071) 51-85071 *I Document #: 001-06490 Rev. *D Page 9 of 12 CY7C1399BN Acronyms Acronym Document Conventions Description Units of Measure BHE byte high enable BLE byte low enable ns nanosecond CE chip enable V volt CMOS complementary metal oxide semiconductor µA microampere I/O input/output mA milliampere OE output enable SRAM static random access memory mV millivolt TSOP thin small outline package mW milliwatt WE write enable MHz megahertz Document #: 001-06490 Rev. *D Symbol Unit of Measure pF picofarad °C degree Celsius W watt Page 10 of 12 CY7C1399BN Document History Page Document Title: CY7C1399BN 256 K (32 K × 8) Static RAM Document Number: 001-06490 Revision ECN Orig. of Change Submission Date ** 423877 NXR See ECN New Data Sheet *A 498575 NXR See ECN Added Automotive-A range Removed IOS parameter from DC Electrical Characteristics table Updated Ordering Information table. *B 2896382 AJU 03/19/2010 Removed obsolete part numbers from Ordering Information table and updated package diagrams. *C 3053362 PRAS 10/08/2010 Removed pruned part numbers CY7C1399BNL-15VXC and CY7C1399BNL-15VXCT. Added Ordering Code Definitions. *D 3383869 TAVA 09/26/2011 Added Commercial temperature range under Features section on page 1. Removed reference to AN1064-SRAM System Design Guidelines on page 1. Modified the notes in figures under Read cycle and Write cycle sections. Updated template according to current Cypress standards. Rearranged sections for better clarity. Revised package diagrams. Added Acronyms and Units of measure. Document #: 001-06490 Rev. *D Description of Change Page 11 of 12 CY7C1399BN Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2006-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-06490 Rev. *D Revised September 26, 2011 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 12 of 12