THIS SPEC IS OBSOLETE
Spec No:
38-05357
Spec Title:
CY7C1441AV33, 36-MBIT (1M X 36) FLOWTHROUGH SRAM
Replaced by: NONE
CY7C1441AV33
36-Mbit (1M × 36) Flow-Through SRAM
36-Mbit (1M × 36) Flow-Through SRAM
Features
Functional Description
■
Supports 133-MHz bus operations
■
1M × 36 common I/O
■
3.3 V core power supply
■
2.5 V or 3.3 V I/O power supply
■
Fast clock-to-output times
❐ 6.5 ns (133-MHz version)
■
Provide high-performance 2-1-1-1 access rate
■
User-selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■
Separate processor and controller address strobes
■
Synchronous self-timed write
■
Asynchronous output enable
■
CY7C1441AV33 available in JEDEC-standard Pb-free 100-pin
TQFP package, Pb-free 165-ball FBGA package.
■
IEEE 1149.1 JTAG-Compatible Boundary Scan
■
“ZZ” Sleep Mode option
The CY7C1441AV33 are 3.3 V, 1M × 36 Synchronous
Flow-through SRAMs, respectively designed to interface with
high-speed microprocessors with minimum glue logic. Maximum
access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit
on-chip counter captures the first address in a burst and
increments the address automatically for the rest of the burst
access. All synchronous inputs are gated by registers controlled
by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining Chip Enable (CE1), depth-expansion Chip
Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and
ADV), Write Enables (BWx, and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and the ZZ
pin.
The CY7C1441AV33 allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the Processor
Address Strobe (ADSP) or the cache Controller Address Strobe
(ADSC) inputs. Address advancement is controlled by the
Address Advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV).
The CY7C1441AV33 operates from a +3.3 V core power supply
while all outputs may operate with either a +2.5 or +3.3 V supply.
All
inputs
and
outputs
are
JEDEC-standard
JESD8-5-compatible.
For a complete list of related documentation, click here.
Selection Guide
Description
133 MHz
Unit
Maximum Access Time
6.5
ns
Maximum Operating Current
310
mA
Maximum CMOS Standby Current
120
mA
Cypress Semiconductor Corporation
Document Number: 38-05357 Rev. *N
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 21, 2017
CY7C1441AV33
Logic Block Diagram – CY7C1441AV33
ADDRESS
REGISTER
A 0, A1, A
A [1:0]
MODE
BURST Q1
COUNTER
AND LOGIC
Q0
CLR
ADV
CLK
ADSC
ADSP
DQ D , DQP D
BW D
BYTE
WRITE REGISTER
DQ C, DQP C
BW C
BYTE
WRITE REGISTER
DQ D , DQP D
BYTE
WRITE REGISTER
DQ C, DQP C
BYTE
WRITE REGISTER
DQ B , DQP B
BW B
DQ B , DQP B
BYTE
BYTE
WRITE REGISTER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQ s
DQP A
DQP B
DQP C
DQP D
WRITE REGISTER
DQ A , DQP A
BW A
BWE
DQ A , DQPA
BYTE
BYTE
WRITE REGISTER
WRITE REGISTER
GW
ENABLE
REGISTER
CE1
CE2
INPUT
REGISTERS
CE3
OE
ZZ
SLEEP
CONTROL
Document Number: 38-05357 Rev. *N
Page 2 of 34
CY7C1441AV33
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 6
Functional Overview ........................................................ 7
Single Read Accesses ................................................ 7
Single Write Accesses Initiated by ADSP ................... 7
Single Write Accesses Initiated by ADSC ................... 7
Burst Sequences ......................................................... 8
Sleep Mode ................................................................. 8
Interleaved Burst Address Table ................................. 8
Linear Burst Address Table ......................................... 8
ZZ Mode Electrical Characteristics .............................. 8
Truth Table ........................................................................ 9
Truth Table for Read/Write ............................................ 10
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 11
Disabling the JTAG Feature ...................................... 11
Test Access Port (TAP) ............................................. 11
PERFORMING A TAP RESET .................................. 11
TAP REGISTERS ...................................................... 11
TAP Instruction Set ................................................... 11
TAP Controller State Diagram ....................................... 13
TAP Controller Block Diagram ...................................... 14
TAP Timing ...................................................................... 14
TAP AC Switching Characteristics ............................... 15
3.3 V TAP AC Test Conditions ....................................... 16
3.3 V TAP AC Output Load Equivalent ......................... 16
2.5 V TAP AC Test Conditions ....................................... 16
2.5 V TAP AC Output Load Equivalent ......................... 16
TAP DC Electrical Characteristics and Operating
Conditions ....................................................................... 16
Document Number: 38-05357 Rev. *N
Identification Register Definitions ................................ 17
Scan Register Sizes ....................................................... 17
Identification Codes ....................................................... 17
Boundary Scan Order .................................................... 18
Maximum Ratings ........................................................... 19
Operating Range ............................................................. 19
Electrical Characteristics ............................................... 19
DC Electrical Characteristics ..................................... 19
Capacitance .................................................................... 20
Thermal Resistance ........................................................ 20
AC Test Loads and Waveforms ..................................... 21
Switching Characteristics .............................................. 22
Timing Diagrams ............................................................ 23
Ordering Information ...................................................... 27
Ordering Code Definitions ......................................... 27
Package Diagrams .......................................................... 28
Acronyms ........................................................................ 30
Document Conventions ................................................. 30
Units of Measure ....................................................... 30
Document History Page ................................................. 31
Sales, Solutions, and Legal Information ...................... 34
Worldwide Sales and Design Support ....................... 34
Products .................................................................... 34
PSoC® Solutions ....................................................... 34
Cypress Developer Community ................................. 34
Technical Support ..................................................... 34
Page 3 of 34
CY7C1441AV33
Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1441AV33
(1M × 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
MODE
A
A
A
A
A1
A0
NC/72M
A
VSS
VDD
A
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQPC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
Document Number: 38-05357 Rev. *N
Page 4 of 34
CY7C1441AV33
Pin Configurations (continued)
Figure 2. 165-ball FBGA (15 × 17 × 1.4 mm) pinout
CY7C1441AV33 (1M × 36)
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/288M
1
A
CE1
BWC
BWB
CE3
BWE
ADSC
ADV
A
NC
NC/144M
A
CE2
BWD
BWA
CLK
GW
OE
ADSP
A
NC/576M
DQPC
DQC
NC
DQC
VDDQ
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VDDQ
NC/1G
DQB
DQPB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
DQC
NC
DQD
DQC
VDD
VDDQ
DQB
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
DQC
NC
DQD
VDDQ
VDDQ
NC
VDDQ
VDD
VDD
VDD
VDDQ
NC
VDDQ
DQB
NC
DQA
DQB
DQB
ZZ
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
R
VDDQ
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQPD
DQD
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
VDD
VSS
VDDQ
VDDQ
DQA
NC
DQA
DQPA
NC
NC/72M
A
A
TDI
A
A1
VSS
NC
TDO
A
A
A
A
MODE
A
A
A
TMS
A0
TCK
A
A
A
A
Document Number: 38-05357 Rev. *N
Page 5 of 34
CY7C1441AV33
Pin Definitions
Name
A0, A1, A
I/O
Description
InputAddress Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the
Synchronous CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit
counter.
BWA, BWB,
InputByte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM.
BWC, BWD Synchronous Sampled on the rising edge of CLK.
GW
CLK
InputGlobal Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global write
Synchronous is conducted (ALL bytes are written, regardless of the values on BWX and BWE).
InputClock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
CE1
InputChip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
Synchronous and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a
new external address is loaded.
CE2
InputChip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE3 to select/deselect the device. CE2 is sampled only when a new external address is loaded.
CE3
InputChip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE2 to select/deselect the device. CE3 is assumed active throughout this document for BGA. CE3
is sampled only when a new external address is loaded.
OE
Output Enable, Asynchronous Input, Active LOW. Controls the direction of the I/O pins. When LOW,
InputAsynchronou the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
s
ADV
InputAdvance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it automatically
Synchronous increments the address in a burst cycle.
ADSP
InputAddress Strobe from Processor, Sampled on the Rising Edge of CLK, Active LOW. When asserted
Synchronous LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is
ignored when CE1 is deasserted HIGH
ADSC
InputAddress Strobe from Controller, Sampled on the Rising Edge of CLK, Active LOW. When asserted
Synchronous LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
BWE
InputByte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal must be asserted
Synchronous LOW to conduct a byte write.
ZZ
ZZ “sleep” Input, Active HIGH. When asserted HIGH places the device in a non-time-critical “sleep”
InputAsynchronou condition with data integrity preserved. For normal operation, this pin must be LOW or left floating. ZZ
pin has an internal pull down.
s
DQs
I/OBidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX
are placed in a tri-state condition.The outputs are automatically tri-stated during the data portion of a
write sequence, during the first clock when emerging from a deselected state, and when the device is
deselected, regardless of the state of OE.
DQPX
I/OBidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During write
Synchronous sequences, DQPx is controlled by BW[A:H] correspondingly.
MODE
VDD
Input-Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating
selects interleaved burst sequence. This is a strap pin and should remain static during device operation.
Mode Pin has an internal pull up.
Power Supply Power Supply Inputs to the Core of the Device.
Document Number: 38-05357 Rev. *N
Page 6 of 34
CY7C1441AV33
Pin Definitions (continued)
Name
VDDQ
VSS
VSSQ
I/O
Description
I/O Power
Supply
Power Supply for the I/O Circuitry.
Ground
Ground for the Core of the Device.
I/O Ground
Ground for the I/O Circuitry.
TDO
JTAG serial Serial Data-Out to the JTAG Circuit. Delivers data on the negative edge of TCK. If the JTAG feature
is not being utilized, this pin should be left unconnected. This pin is not available on TQFP packages.
output
Synchronous
TDI
JTAG serial Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being
input
utilized, this pin can be left floating or connected to VDD through a pull up resistor. This pin is not available
Synchronous on TQFP packages.
TMS
JTAG serial Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being
input
utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages.
Synchronous
TCK
JTAG-Clock Clock Input to the JTAG Circuitry. If the JTAG feature is not being utilized, this pin must be connected
to VSS. This pin is not available on TQFP packages.
NC
–
No Connects. Not internally connected to the die. 72M, 144M and 288M are address expansion pins
are not internally connected to the die.
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
–
No Connects. Not internally connected to the die. NC/72M, NC/144M, NC/288M, NC/576M and NC/1G
are address expansion pins are not internally connected to the die.
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (t CDV) is 6.5 ns (133-MHz device).
The CY7C1441AV33 supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™ processors.
The linear burst sequence is suited for processors that utilize a
linear burst sequence. The burst order is user-selectable, and is
determined by sampling the MODE input. Accesses can be
initiated with either the Processor Address Strobe (ADSP) or the
Controller Address Strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captures the first
address in a burst sequence and automatically increments the
address for the rest of the burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWx) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to all
four bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1 is
HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
Document Number: 38-05357 Rev. *N
active, and (2) ADSP or ADSC is asserted LOW (if the access is
initiated by ADSC, the write inputs must be deasserted during
this first cycle). The address presented to the address inputs is
latched into the address register and the burst counter/control
logic and presented to the memory core. If the OE input is
asserted LOW, the requested data is available at the data
outputs a maximum to tCDV after clock rise. ADSP is ignored if
CE1 is HIGH.
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted active,
and (2) ADSP is asserted LOW. The addresses presented are
loaded into the address register and the burst inputs (GW, BWE,
and BWX)are ignored during this first clock cycle. If the write
inputs are asserted active (see Write Cycle Descriptions table for
appropriate states that indicate a write) on the next clock rise, the
appropriate data is latched and written into the device. Byte
writes are allowed. All IOs are tri-stated during a byte write.Since
this is a common I/O device, the asynchronous OE input signal
must be deasserted and the IOs must be tri-stated prior to the
presentation of data to DQs. As a safety precaution, the data
lines are tri-stated once a write cycle is detected, regardless of
the state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BWX)
indicate a write access. ADSC is ignored if ADSP is active LOW.
Page 7 of 34
CY7C1441AV33
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the memory
core. The information presented to DQS is written into the
specified address location. Byte writes are allowed. All IOs are
tri-stated when a write is detected, even a byte write. Since this
is a common I/O device, the asynchronous OE input signal must
be deasserted and the IOs must be tri-stated prior to the
presentation of data to DQs. As a safety precaution, the data
lines are tri-stated once a write cycle is detected, regardless of
the state of OE.
Burst Sequences
CE3, ADSP, and ADSC must remain inactive for the duration of
tZZREC after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Fourth
Address
A1:A0
The CY7C1441AV33 provides an on-chip two-bit wraparound
burst counter inside the SRAM. The burst counter is fed by A[1:0],
and can follow either a linear or interleaved burst order. The burst
order is determined by the state of the MODE input. A LOW on
MODE selects a linear burst sequence. A HIGH on MODE
selects an interleaved burst order. Leaving MODE unconnected
causes the device to default to a interleaved burst sequence.
Linear Burst Address Table
Sleep Mode
(MODE = GND)
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
Fourth
Address
A1:A0
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
Document Number: 38-05357 Rev. *N
Test Conditions
ZZ > VDD– 0.2 V
ZZ > VDD – 0.2 V
ZZ < 0.2 V
This parameter is sampled
This parameter is sampled
Min
Max
Unit
–
–
100
2tCYC
–
2tCYC
mA
ns
ns
ns
ns
2tCYC
–
0
–
Page 8 of 34
CY7C1441AV33
Truth Table
The truth table for CY7C1441AV33 follows. [1, 2, 3, 4, 5]
Cycle Description
Address Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK
DQ
Deselected Cycle, Power down
None
H
X
X
L
X
L
X
X
X
L–H Tri-State
Deselected Cycle, Power down
None
L
L
X
L
L
X
X
X
X
L–H Tri-State
Deselected Cycle, Power down
None
L
X
H
L
L
X
X
X
X
L–H Tri-State
Deselected Cycle, Power down
None
L
L
X
L
H
L
X
X
X
L–H Tri-State
Deselected Cycle, Power down
None
X
X
X
L
H
L
X
X
X
L–H Tri-State
Sleep Mode, Power down
None
X
X
X
H
X
X
X
X
X
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
External
External
External
External
External
Next
Next
Next
L
L
L
L
L
X
X
H
H
H
H
H
H
X
X
X
L
L
L
L
L
X
X
X
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
X
X
X
L
L
L
H
H
H
X
X
X
X
X
L
L
L
X
X
L
H
H
H
H
H
L
H
X
L
H
L
H
L
L–H
Q
L–H Tri-State
L–H
D
L–H
Q
L–H Tri-State
L–H
Q
L–H Tri-State
L–H
Q
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L–H Tri-State
Write Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L–H
D
Write Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L–H
D
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L–H
Q
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L–H Tri-State
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L–H
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L–H Tri-State
Write Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L–H
D
Write Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L–H
D
X
Tri-State
Q
Notes
1. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
2. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
4. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care
for the remainder of the write cycle.
5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 38-05357 Rev. *N
Page 9 of 34
CY7C1441AV33
Truth Table for Read/Write
Function (CY7C1441AV33) [6, 7]
GW
BWE
BWD
BWC
BWB
BWA
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write Byte A (DQA, DQPA)
H
L
H
H
H
L
Write Byte B(DQB, DQPB)
H
L
H
H
L
H
Write Bytes A, B (DQA, DQB, DQPA, DQPB)
H
L
H
H
L
L
Write Byte C (DQC, DQPC)
H
L
H
L
H
H
Write Bytes C, A (DQC, DQA, DQPC, DQPA)
H
L
H
L
H
L
Write Bytes C, B (DQC, DQB, DQPC, DQPB)
H
L
H
L
L
H
Write Bytes C, B, A (DQC, DQB, DQA, DQPC, DQPB,
DQPA)
H
L
H
L
L
L
Write Byte D (DQD, DQPD)
H
L
L
H
H
H
Write Bytes D, A (DQD, DQA, DQPD, DQPA)
H
L
L
H
H
L
Write Bytes D, B (DQD, DQA, DQPD, DQPA)
H
L
L
H
L
H
Write Bytes D, B, A (DQD, DQB, DQA, DQPD, DQPB,
DQPA)
H
L
L
H
L
L
Write Bytes D, B (DQD, DQB, DQPD, DQPB)
H
L
L
L
H
H
Write Bytes D, B, A (DQD, DQC, DQA, DQPD, DQPC,
DQPA)
H
L
L
L
H
L
Write Bytes D, C, A (DQD, DQB, DQA, DQPD, DQPB,
DQPA)
H
L
L
L
L
H
Write All Bytes
H
L
L
L
L
L
Write All Bytes
L
X
X
X
X
X
Notes
6. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
7. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write is done based on which byte write is active.
Document Number: 38-05357 Rev. *N
Page 10 of 34
CY7C1441AV33
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1441AV33 incorporates a serial boundary scan test
access port (TAP). This part is fully compliant with 1149.1. The
TAP operates using JEDEC-standard 3.3 V or 2.5 V I/O logic
levels.
The CY7C1441AV33 contains a TAP controller, instruction
register, boundary scan register, bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull up resistor. TDO
should be left unconnected. Upon power up, the device comes
up in a reset state which does not interfere with the operation of
the device.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. TDI is internally pulled
up and can be unconnected if the TAP is unused in an
application. TDI is connected to the most significant bit (MSB) of
any register.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine. The output changes on the falling edge
of TCK. TDO is connected to the least significant bit (LSB) of any
register.
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
At power up, the TAP is reset internally to ensure that TDO
comes up in a High Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
scan data into and out of the SRAM test circuitry. Only one
register can be selected at a time through the instruction register.
Document Number: 38-05357 Rev. *N
Data is serially loaded into the TDI ball on the rising edge of TCK.
Data is output on the TDO ball on the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 14. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This shifts data through the SRAM with
minimal delay. The bypass register is set LOW (VSS) when the
BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The length of the boundary scan
register for the SRAM in different packages is listed in the Scan
Register Sizes on page 17.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI,
and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions on
page 17.
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Identification Codes on page 17. Three of these instructions are
listed as RESERVED and should not be used. The other five
instructions are described in this section in detail.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
Page 11 of 34
CY7C1441AV33
the instruction once it is shifted in, the TAP controller must be
moved into the Update-IR state.
IDCODE
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO balls and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a High Z state until the next command is given during the
“Update IR” state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
Document Number: 38-05357 Rev. *N
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells prior to the selection
of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required – that is, while data captured
is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the shift-DR controller state.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #89
(for 165-ball FBGA package) or bit #138 (for 209-ball FBGA
package). When this scan cell, called the “extest output bus
tri-state”, is latched into the preload register during the
“Update-DR” state in the TAP controller, it directly controls the
state of the output (Q-bus) pins, when the EXTEST is entered as
the current instruction. When HIGH, it enables the output buffers
to drive the output bus. When LOW, this bit places the output bus
into a High Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell latches into the preload
register. When the EXTEST instruction is entered, this bit directly
controls the output Q-bus pins. Note that this bit is pre-set HIGH
to enable the output when the device is powered-up, and also
when the TAP controller is in the “Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Page 12 of 34
CY7C1441AV33
TAP Controller State Diagram
1
TEST-LOGIC
RESET
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
0
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
1
1
EXIT1-IR
0
1
0
PAUSE-DR
0
PAUSE-IR
1
0
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-DR
UPDATE-IR
1
0
1
EXIT1-DR
0
1
0
1
0
The 0/1 next to each state represents the value of TMS at the rising edge of TCK.
Document Number: 38-05357 Rev. *N
Page 13 of 34
CY7C1441AV33
TAP Controller Block Diagram
0
Bypass Register
2 1 0
TDI
Selection
Circuitry
Selection
Circuitry
Instruction Register
TDO
31 30 29 . . . 2 1 0
Identification Register
x . . . . . 2 1 0
Boundary Scan Register
TCK
TAP CONTROLLER
TM S
TAP Timing
Figure 3. TAP Timing
1
2
Test Clock
(TCK)
3
t
t TH
t TMSS
t TMSH
t TDIS
t TDIH
TL
4
5
6
t CYC
Test Mode Select
(TMS)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CARE
Document Number: 38-05357 Rev. *N
UNDEFINED
Page 14 of 34
CY7C1441AV33
TAP AC Switching Characteristics
Over the Operating Range
Parameter [9, 10]
Description
Min
Max
Unit
Clock
tTCYC
TCK Clock Cycle Time
50
–
ns
tTF
TCK Clock Frequency
–
20
MHz
tTH
TCK Clock HIGH time
20
–
ns
tTL
TCK Clock LOW time
20
–
ns
tTDOV
TCK Clock LOW to TDO Valid
–
10
ns
tTDOX
TCK Clock LOW to TDO Invalid
0
–
ns
tTMSS
TMS Setup to TCK Clock Rise
5
–
ns
tTDIS
TDI Setup to TCK Clock Rise
5
–
ns
tCS
Capture Setup to TCK Rise
5
–
ns
tTMSH
TMS Hold after TCK Clock Rise
5
–
ns
tTDIH
TDI Hold after Clock Rise
5
–
ns
tCH
Capture Hold after Clock Rise
5
–
ns
Output Times
Setup Times
Hold Times
Notes
9. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
10. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns.
Document Number: 38-05357 Rev. *N
Page 15 of 34
CY7C1441AV33
3.3 V TAP AC Test Conditions
2.5 V TAP AC Test Conditions
Input pulse levels ...............................................VSS to 3.3 V
Input pulse levels ............................................... VSS to 2.5 V
Input rise and fall times ...................................................1 ns
Input rise and fall time ....................................................1 ns
Input timing reference levels ......................................... 1.5 V
Input timing reference levels ....................................... 1.25 V
Output reference levels ................................................ 1.5 V
Output reference levels .............................................. 1.25 V
Test load termination supply voltage ............................ 1.5 V
Test load termination supply voltage .......................... 1.25 V
3.3 V TAP AC Output Load Equivalent
2.5 V TAP AC Output Load Equivalent
1.25V
1.5V
50Ω
50Ω
TDO
TDO
Z O = 50 Ω
Z O = 50 Ω
20p F
20p F
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 3.135 V to 3.6 V unless otherwise noted)
Parameter [11]
VOH1
VOH2
VOL1
VOL2
VIH
VIL
IX
Description
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Conditions
Max
Unit
IOH = –4.0 mA
VDDQ = 3.3 V
2.4
–
V
IOH = –1.0 mA
VDDQ = 2.5 V
2.0
–
V
IOH = –100 µA
VDDQ = 3.3 V
2.9
–
V
VDDQ = 2.5 V
2.1
–
V
IOL = 8.0 mA
VDDQ = 3.3 V
–
0.4
V
IOL = 1.0 mA
VDDQ = 2.5 V
–
0.4
V
IOL = 100 µA
VDDQ = 3.3 V
–
0.2
V
VDDQ = 2.5 V
–
0.2
V
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Min
GND < VIN < VDDQ
VDDQ = 3.3 V
2.0
VDD + 0.3
V
VDDQ = 2.5 V
1.7
VDD + 0.3
V
VDDQ = 3.3 V
–0.3
0.8
V
VDDQ = 2.5 V
–0.3
0.7
V
–5
5
µA
Note
11. All voltages referenced to VSS (GND).
Document Number: 38-05357 Rev. *N
Page 16 of 34
CY7C1441AV33
Identification Register Definitions
Instruction Field
CY7C1441AV33 (1M × 36)
Revision Number (31:29)
000
Device Depth (28:24)
01011
Architecture/Memory Type(23:18) [12]
000001
Bus Width/Density(17:12)
100111
Cypress JEDEC ID Code (11:1)
00000110100
ID Register Presence Indicator (0)
1
Description
Describes the version number.
Reserved for Internal Use
Defines memory type and architecture
Defines width and density
Allows unique identification of SRAM vendor.
Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size (× 36)
Instruction Bypass
3
Bypass
1
ID
32
Boundary Scan Order (165-ball FBGA package)
89
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM output drivers to a High Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does
not affect SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Note
12. Bit #24 is “1” in the ID Register Definitions for both 2.5 V and 3.3 V versions of this device.
Document Number: 38-05357 Rev. *N
Page 17 of 34
CY7C1441AV33
Boundary Scan Order
165-ball FBGA [13, 14]
CY7C1441AV33 (1M × 36)
Bit #
Ball ID
Bit #
Ball ID
Bit #
Ball ID
Bit #
Ball ID
1
N6
26
E11
51
A3
76
N1
2
N7
N10
27
D11
52
A2
77
N2
3
28
G10
53
B2
78
P1
4
P11
29
F10
54
C2
79
R1
5
P8
30
E10
55
B1
80
R2
6
R8
31
D10
56
A1
81
P3
7
R9
32
C11
57
C1
82
R3
8
P9
33
A11
58
D1
83
P2
9
P10
34
B11
59
E1
84
R4
10
R10
35
A10
60
F1
85
P4
11
R11
36
B10
61
G1
86
N5
12
H11
37
A9
62
D2
87
P6
13
N11
38
B9
63
E2
88
R6
89
Internal
14
M11
39
C10
64
F2
15
L11
40
A8
65
G2
16
K11
41
B8
66
H1
17
J11
42
A7
67
H3
18
M10
43
B7
68
J1
19
L10
44
B6
69
K1
20
K10
45
A6
70
L1
21
J10
46
B5
71
M1
22
H9
47
J2
H10
48
A5
A4
72
23
73
K2
24
G11
49
B4
74
L2
25
F11
50
B3
75
M2
Notes
13. Balls which are NC (No Connect) are preset LOW.
14. Bit# 89 is preset HIGH.
Document Number: 38-05357 Rev. *N
Page 18 of 34
CY7C1441AV33
Maximum Ratings
DC Input Voltage ................................ –0.5 V to VDD + 0.5 V
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature ............................... –65 C to +150 C
Ambient Temperature with
Power Applied ......................................... –55C to +125 C
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(per MIL-STD-883, Method 3015) .......................... > 2001 V
Latch-up Current .................................................... > 200 mA
Operating Range
Supply Voltage on VDD Relative to GND .....–0.3 V to +4.6 V
Range
Supply Voltage on VDDQ Relative to GND .... –0.3 V to +VDD
DC Voltage Applied to Outputs
in Tri-State ........................................–0.5 V to VDDQ + 0.5 V
Commercial
Industrial
Ambient
Temperature
0 °C to +70 °C
–40 °C to +85 °C
VDD
VDDQ
3.3 V– 5% / 2.5 V – 5% to
+ 10%
VDD
Electrical Characteristics
Over the Operating Range
DC Electrical Characteristics
Over the Operating Range
Parameter [15, 16]
Description
Test Conditions
Min
Max
Unit
VDD
Power Supply Voltage
VDDQ
I/O Supply Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
for 3.3 V I/O, IOL = 8.0 mA
VIH
Input HIGH Voltage[15]
for 3.3 V I/O
VIL
Input LOW Voltage[15]
IX
Input Leakage Current except ZZ GND VI VDDQ
and MODE
Input Current of MODE
Input = VSS
Input = VDD
Input Current of ZZ
Input = VSS
Input = VDD
–
30
A
IOZ
Output Leakage Current
GND VI VDDQ, Output Disabled
–5
5
A
IDD
VDD Operating Supply Current
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
7.5-ns
cycle, 133
MHz
–
310
mA
ISB1
Automatic CE Power down
Current – TTL Inputs
Max VDD, Device Deselected,
VIN VIH or VIN VIL, f = fMAX,
inputs switching
7.5-ns
cycle, 133
MHz
–
180
mA
ISB2
Automatic CE Power down
Current – CMOS Inputs
7.5-ns
Max VDD, Device Deselected,
VIN VDD – 0.3 V or VIN 0.3 V, cycle, 133
MHz
f = 0, inputs static
–
120
mA
3.135
3.6
V
for 3.3 V I/O
3.135
VDD
V
for 2.5 V I/O
2.375
2.625
V
for 3.3 V I/O, IOH = –4.0 mA
2.4
–
V
for 2.5 V I/O, IOH = –1.0 mA
2.0
–
V
–
0.4
V
for 2.5 V I/O, IOL = 1.0 mA
–
0.4
V
2.0
VDD + 0.3 V
V
for 2.5 V I/O
1.7
VDD + 0.3 V
V
for 3.3 V I/O
–0.3
0.8
V
for 2.5 V I/O
–0.3
0.7
V
–5
5
A
–30
–
A
–
5
A
–5
–
A
Notes
15. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).
16. TPower-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document Number: 38-05357 Rev. *N
Page 19 of 34
CY7C1441AV33
Electrical Characteristics (continued)
Over the Operating Range
DC Electrical Characteristics (continued)
Over the Operating Range
Parameter [15, 16]
Description
Test Conditions
Min
Max
Unit
ISB3
Automatic CE Power down
Current – CMOS Inputs
7.5-ns
Max VDD, Device Deselected,
VIN VDDQ – 0.3 V or VIN 0.3 V, cycle, 133
MHz
f = fMAX, inputs switching
–
180
mA
ISB4
Automatic CE Power down
Current – TTL Inputs
Max VDD, Device Deselected,
VIN VDD – 0.3 V or VIN 0.3 V,
f = 0, inputs static
–
135
mA
7.5-ns
cycle, 133
MHz
Capacitance
Parameter [17]
Description
CIN
Input capacitance
CCLK
Clock input capacitance
CIO
Input/Output capacitance
Test Conditions
TA = 25 C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 2.5 V
100-pin TQFP 165-ball FBGA Unit
Max
Max
6.5
7
pF
3
7
pF
5.5
6
pF
Thermal Resistance
Parameter [17]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51.
100-pin TQFP 165-ball FBGA Unit
Package
Package
25.21
20.8
C/W
2.28
3.2
C/W
Note
17. Tested initially and after any design or process change that may affect these parameters.
Document Number: 38-05357 Rev. *N
Page 20 of 34
CY7C1441AV33
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317
3.3 V
OUTPUT
OUTPUT
RL = 50
Z0 = 50
GND
5 pF
R = 351
VT = 1.5 V
INCLUDING
JIG AND
SCOPE
(a)
ALL INPUT PULSES
VDDQ
10%
90%
10%
90%
1 ns
1 ns
(c)
(b)
2.5 V I/O Test Load
R = 1667
2.5 V
OUTPUT
OUTPUT
RL = 50
Z0 = 50
GND
5 pF
R = 1538
VT = 1.25 V
(a)
Document Number: 38-05357 Rev. *N
ALL INPUT PULSES
VDDQ
INCLUDING
JIG AND
SCOPE
(b)
10%
90%
10%
90%
1 ns
1 ns
(c)
Page 21 of 34
CY7C1441AV33
Switching Characteristics
Over the Operating Range
Parameter [18, 19]
tPOWER
Description
VDD(typical) to the first access [20]
-133
Unit
Min
Max
1
–
ms
Clock
tCYC
Clock cycle time
7.5
–
ns
tCH
Clock HIGH
2.5
–
ns
tCL
Clock LOW
2.5
–
ns
Output Times
tCDV
Data output valid after CLK rise
–
6.5
ns
tDOH
Data output hold after CLK rise
2.5
–
ns
2.5
–
ns
–
3.8
ns
–
3.0
ns
0
–
ns
–
3.0
ns
[21, 22, 23]
tCLZ
Clock to low Z
tCHZ
Clock to high Z [21, 22, 23]
tOEV
OE LOW to output valid
tOELZ
tOEHZ
OE LOW to output low Z
[21, 22, 23]
OE HIGH to output high Z
[21, 22, 23]
Setup Times
tAS
Address setup before CLK rise
1.5
–
ns
tADS
ADSP, ADSC setup before CLK rise
1.5
–
ns
tADVS
ADV setup before CLK rise
1.5
–
ns
tWES
GW, BWE, BWX setup before CLK rise
1.5
–
ns
tDS
Data input setup before CLK rise
1.5
–
ns
tCES
Chip enable setup
1.5
–
ns
tAH
Address hold after CLK rise
0.5
–
ns
tADH
ADSP, ADSC hold after CLK rise
0.5
–
ns
tWEH
GW, BWE, BWX hold after CLK rise
0.5
–
ns
tADVH
ADV hold after CLK rise
0.5
–
ns
tDH
Data input hold after CLK rise
0.5
–
ns
tCEH
Chip enable hold after CLK rise
0.5
–
ns
Hold Times
Notes
18. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
19. Test conditions shown in (a) of Figure 4 on page 21 unless otherwise noted.
20. This part has a voltage regulator internally; tPOWER is the time that the power must be supplied above VDD(minimum) initially, before a read or write operation can be
initiated.
21. tCHZ, tCLZ ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 4 on page 21. Transition is measured ±200 mV from steady-state voltage.
22. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High Z prior to Low Z under the same system conditions.
23. This parameter is sampled and not 100% tested.
Document Number: 38-05357 Rev. *N
Page 22 of 34
CY7C1441AV33
Timing Diagrams
Figure 5. Read Cycle Timing [24]
tCYC
CLK
t
t ADS
CH
t CL
tADH
ADSP
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
t
GW, BWE,BW
t
WES
WEH
X
t CES
Deselect Cycle
t CEH
CE
t
ADVS
t
ADVH
ADV
ADV suspends burst
OE
t OEV
t OEHZ
t CLZ
Data Out (Q)
High-Z
Q(A1)
t CDV
t OELZ
t CHZ
t DOH
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
t CDV
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
.
Note
24. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document Number: 38-05357 Rev. *N
Page 23 of 34
CY7C1441AV33
Timing Diagrams (continued)
Figure 6. Write Cycle Timing [25, 26]
t CYC
CLK
t
t ADS
CH
t
CL
tADH
ADSP
t ADS
ADSC extends burst
tADH
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
A3
Byte write signals are ignored for first cycle when
ADSP initiates burst
t WES tWEH
BWE,
BW
X
t
WES
t
WEH
GW
t CES
tCEH
CE
t ADVS tADVH
ADV
ADV suspends burst
OE
t
Data in (D)
High-Z
t
DS
t
DH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
OEHZ
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
.
Notes
25. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
26. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW
Document Number: 38-05357 Rev. *N
Page 24 of 34
CY7C1441AV33
Timing Diagrams (continued)
Figure 7. Read/Write Cycle Timing [27, 28, 29]
tCYC
CLK
t
t ADS
CH
t
CL
tADH
ADSP
ADSC
t AS
ADDRESS
A1
tAH
A2
A3
A4
t
WES
t
A5
A6
WEH
BWE, BW X
t CES
tCEH
CE
ADV
OE
t DS
Data In (D)
Data Out (Q)
High-Z
t
OEHZ
Q(A1)
tDH
t OELZ
D(A3)
D(A5)
Q(A4)
Q(A2)
Back-to-Back READs
D(A6)
t CDV
Single WRITE
Q(A4+1)
BURST READ
DON’T CARE
Q(A4+2)
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
.
Note
27. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
28. The data bus (Q) remains in high Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
29. GW is HIGH.
Document Number: 38-05357 Rev. *N
Page 25 of 34
CY7C1441AV33
Timing Diagrams (continued)
Figure 8. ZZ Mode Timing [30, 31]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t
ALL INPUTS
(except ZZ)
Outputs (Q)
RZZI
DESELECT or READ Only
High-Z
DON’T CARE
Notes
30. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
31. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 38-05357 Rev. *N
Page 26 of 34
CY7C1441AV33
Ordering Information
Cypress offers other versions of this type of product in different configurations and features. The following table contains only the list
of parts that are currently available.
For a complete listing of all options, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products, or contact your local sales representative.
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
133
Ordering Code
Package
Diagram
Part and Package Type
CY7C1441AV33-133AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
CY7C1441AV33-133AXI
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
CY7C1441AV33-133BZI
51-85165 165-ball FBGA (15 × 17 × 1.4 mm)
CY7C1441AV33-133BZXI
51-85165 165-ball FBGA (15 × 17 × 1.4 mm) Pb-free
Ordering Code Definitions
CY
7
C 1441 A V33 - 133 XX X
X
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type: XX = A or BZ
A = 100-pin TQFP
BZ = 165-ball FBGA
Frequency Range: 133 MHz
VDD = 3.3 V
Process Technology: A 90 nm
Part Identifier: 1441 = FT, 1Mb × 36 (36Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAMs
Company ID: CY = Cypress
Document Number: 38-05357 Rev. *N
Page 27 of 34
CY7C1441AV33
Package Diagrams
Figure 9. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
51-85050 *E
Document Number: 38-05357 Rev. *N
Page 28 of 34
CY7C1441AV33
Package Diagrams (continued)
Figure 10. 165-ball FBGA (15 × 17 × 1.40 mm) (0.45 Ball Diameter) Package Outline, 51-85165
51-85165 *E
Document Number: 38-05357 Rev. *N
Page 29 of 34
CY7C1441AV33
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CMOS
Complementary metal oxide semiconductor
FBGA
Fine-Pitch Ball Grid Array
°C
degree Celsius
I/O
Input/Output
MHz
megahertz
JTAG
Joint Test Action Group
µA
microampere
LSB
Least Significant Bit
mA
milliampere
MSB
Most Significant Bit
mm
millimeter
ms
millisecond
OE
Output Enable
SRAM
Static Random Access Memory
TAP
Test Access Port
TCK
Test Clock
TDI
Test Data-In
TDO
Test Data-Out
TMS
Test Mode Select
TQFP
Thin Quad Flat Pack
Document Number: 38-05357 Rev. *N
Symbol
Unit of Measure
ns
nanosecond
ohm
%
percent
pF
picofarad
V
volt
W
watt
Page 30 of 34
CY7C1441AV33
Document History Page
Document Title: CY7C1441AV33, 36-Mbit (1M × 36) Flow-Through SRAM
Document Number: 38-05357
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
**
124459
CJM
03/06/03
New data sheet.
Part number changed from previous revision. New and old part number differ
by the letter “A”.
*A
254910
SYT
See ECN
Updated Logic Block Diagram – CY7C1441AV33.
Updated Logic Block Diagram – CY7C1443AV33.
Updated Logic Block Diagram – CY7C1447AV33.
Updated Identification Register Definitions (Added Note 12 (32-Bit Vendor I.D
Code changed)).
Added Boundary Scan Order
Updated Electrical Characteristics (Updated DC Electrical Characteristics
(Updated the values of IX , IDD, ISB1, ISB2, ISB3, and ISB4 parameters)).
Updated Switching Characteristics (Added tPOWER parameter and its details).
Modified Timing Diagrams.
Updated Package Diagrams (Removed 119-ball PBGA Package, changed
165-ball FBGA (15 × 17 × 1.20 mm) BB165C (spec 51-85165 **) to 165-ball
FBGA (15 × 17 × 1.40 mm) BB165C (spec 51-85165 *A), changed 209-Lead
PBGA (14 × 22 × 2.20 mm) BG209 (spec 51-85143) to 209-ball FBGA (14 ×
22 × 1.76 mm) BB209A (spec 51-85167)).
*B
300131
SYT
See ECN
Updated Features (Removed 150 MHz and 117 MHz frequencies related
information).
Updated Selection Guide (Removed 150 MHz and 117 MHz frequencies
related information).
Updated Electrical Characteristics (Updated DC Electrical Characteristics
(Removed 150 MHz and 117 MHz frequencies related information)).
Updated Thermal Resistance (Replaced values of JA and JC parameters
from TBD to 25.21 °C/W and 2.58 °C/W respectively for 100-pin TQFP
package).
Updated Switching Characteristics (Removed 150 MHz and 117 MHz
frequencies related information).
Updated Ordering Information (Added Pb-free information for 100-pin TQFP,
165-ball FBGA and 209-ball FBGA Packages, added ‘Pb-free BG and BZ
packages availability’ comment below the Ordering Information).
*C
320813
SYT
See ECN
Updated Pin Configurations (Changed H9 pin from VSSQ to VSS for 209-ball
FBGA).
Updated Electrical Characteristics (Changed the test condition for VOL
parameter from VDD = Min. to VDD = Max., replaced the TBD’s with their
respective values for IDD, ISB1, ISB2, ISB3 and ISB4 parameters).
Updated Thermal Resistance (Replaced values of JA and JC parameters
from TBD to respective Thermal Values for 165-ball FBGA and 209-ball FBGA
Packages).
Updated Capacitance (Changed values of CIN, CCLK and CI/O parameters to
6.5 pF, 3 pF and 5.5 pF from 5 pF, 5 pF and 7 pF for 100-pin TQFP Package)
Updated Ordering Information (Removed “Pb-free BG and BZ packages
availability” comment below the Ordering Information).
Document Number: 38-05357 Rev. *N
Page 31 of 34
CY7C1441AV33
Document History Page (continued)
Document Title: CY7C1441AV33, 36-Mbit (1M × 36) Flow-Through SRAM
Document Number: 38-05357
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
*D
331551
SYT
See ECN
Updated Pin Configurations (Modified Address Expansion balls in the pinouts
for 165-ball FBGA and 209-ball BGA Packages as per JEDEC standards).
Updated Pin Definitions.
Updated Functional Overview (Updated ZZ Mode Electrical Characteristics
(Changed maximum value of IDDZZ parameter from TBD to 100 mA)).
Updated Operating Range (Added Industrial Temperature Range).
Updated Electrical Characteristics (Updated test conditions for VOL and VOH
parameters, changed maximum value of ISB2 parameter from 100 mA to
120 mA, changed maximum value of ISB4 parameter from 110 mA to 135 mA
respectively).
Updated Capacitance (Changed values of CIN, CCLK and CI/O parameters to
7 pF, 7 pF and 6 pF from 5 pF, 5 pF and 7 pF for 165-ball FBGA Package).
Updated Ordering Information (By shading and unshading MPNs as per
availability).
*E
417547
RXU
See ECN
Changed status from Preliminary to Final.
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”.
Updated Electrical Characteristics (Updated Note 16 (Changed test condition
from VIH < VDD to VIH VDD), changed “Input Load Current except ZZ and
MODE” to “Input Leakage Current except ZZ and MODE”, changed minimum
value of IX parameter (corresponding to Input current of MODE (Input = VSS))
from –5 A to –30 A, changed maximum value of IX parameter (corresponding
to Input current of MODE (Input = VDD)) from 30 A to 5 A respectively,
changed minimum value of IX parameter (corresponding to Input current of ZZ
(Input = VSS)) from –30 A to –5 A, changed maximum value of IX parameter
(corresponding to Input current of ZZ (Input = VDD)) from 5 A to 30 A
respectively).
Updated Ordering Information (Updated part numbers, replaced Package
Name column with Package Diagram in the Ordering Information table).
Updated Package Diagrams:
51-85050 – Changed revision from *A to *B.
*F
473650
VKN
See ECN
Updated Maximum Ratings (Added the Maximum Rating for Supply Voltage
on VDDQ Relative to GND).
Updated TAP AC Switching Characteristics (Changed minimum value of tTH
and tTL parameters from 25 ns to 20 ns, changed maximum value of tTDOV
parameter from 5 ns to 10 ns).
Updated Ordering Information (Updated part numbers).
*G
2447027
VKN /
AESA
See ECN
Updated Logic Block diagram – CY7C1447AV33 (Corrected typo).
Updated Ordering Information (Corrected typo in the Ordering Information
table).
*H
2898501
NJY
03/24/2010
Updated Ordering Information (Removed inactive part numbers).
Updated Package Diagrams:
51-85050 – Changed revision from *B to *C.
51-85165 – Changed revision from *A to *B.
51-85167 – Changed revision from ** to *A.
*I
3263570
OSN
05/23/2011
Added Ordering Code Definitions.
Updated Package Diagrams:
51-85050 – Changed revision from *C to *D.
Added Acronyms and Units of Measure.
Updated to new template.
Document Number: 38-05357 Rev. *N
Page 32 of 34
CY7C1441AV33
Document History Page (continued)
Document Title: CY7C1441AV33, 36-Mbit (1M × 36) Flow-Through SRAM
Document Number: 38-05357
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
*J
3592981
NJY / PRIT
04/20/2012
Updated Features (Removed CY7C1443AV33, CY7C1447AV33 related
information, removed 209-ball FBGA package related information).
Updated Functional Description (Removed CY7C1443AV33, CY7C1447AV33
related information, removed the Note “For best-practices recommendations,
please refer to the Cypress application note System Design Guidelines on
www.cypress.com.” and its reference).
Updated Selection Guide (Removed 100 MHz frequency related information).
Removed Logic Block Diagram – CY7C1443AV33.
Removed Logic Block Diagram – CY7C1447AV33.
Updated Pin Configurations (Removed CY7C1443AV33, CY7C1447AV33
related information, removed 209-ball FBGA package related information).
Updated Pin Definitions.
Updated Functional Overview (Removed CY7C1443AV33, CY7C1447AV33
related information).
Updated Truth Table (Removed CY7C1443AV33, CY7C1447AV33 related
information).
Removed Truth Table for Read/Write (Corresponding to CY7C1443AV33,
CY7C1447AV33).
Updated IEEE 1149.1 Serial Boundary Scan (JTAG) (Removed
CY7C1443AV33, CY7C1447AV33 related information).
Updated Identification Register Definitions (Removed CY7C1443AV33,
CY7C1447AV33 related information).
Updated Scan Register Sizes (Removed Bit Size (× 18), Bit Size (× 72)
columns).
Updated Boundary Scan Order (Removed CY7C1443AV33 related
information).
Updated Electrical Characteristics (Removed 100 MHz frequency related
information).
Updated Capacitance (Removed 209-ball FBGA package related information).
Updated Thermal Resistance (Removed 209-ball FBGA package related
information).
Updated Switching Characteristics (Removed 100 MHz frequency related
information).
Updated Package Diagrams (spec 51-85165 (Changed revision from *B to *D),
removed 209-ball FBGA package related information (spec 51-85167)).
Replaced all instances of IO with I/O across the document.
*K
4010294
PRIT
05/24/2013
No technical updates.
Completing Sunset Review.
*L
4409607
PRIT
06/16/2014
Updated Package Diagrams:
spec 51-85050 – Changed revision from *D to *E.
Completing Sunset Review.
*M
4571917
PRIT
12/29/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Package Diagrams:
spec 51-85165 – Changed revision from *D to *E.
*N
5859284
AJU
08/21/2017
Obsolete document.
Completing Sunset Review.
Document Number: 38-05357 Rev. *N
Page 33 of 34
CY7C1441AV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/memory
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
Wireless/RF
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2003-2017. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05357 Rev. *N
Revised August 21, 2017
Page 34 of 34
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All products and company names mentioned in this document
may be the trademarks of their respective holders.
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