CY7C1441AV33-133BZXI

CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 36-Mbit (1 M × 36/2 M × 18/512 K × 72) Flow-Through SRAM 36-Mbit (1 M × 36/2 M × 18/512 K × 72) Flow-Through SRAM Features ■ ■ ■ ■ ■ Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWx, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) input. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 operates from a +3.3 V core power supply while all outputs may operate with either a +2.5 or +3.3 V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Supports 133-MHz bus operations 1 M × 36/2 M × 18/512 K × 72 common IO 3.3 V core power supply 2.5 V or 3.3 V IO power supply Fast clock-to-output times ❐ 6.5 ns (133-MHz version) Provide high-performance 2-1-1-1 access rate User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences Separate processor and controller address strobes Synchronous self-timed write Asynchronous output enable CY7C1441AV33, CY7C1443AV33 available in JEDEC-standard Pb-free 100-pin TQFP package, Pb-free and non Pb-free 165-ball FBGA package. CY7C1447AV33 available in Pb-free and non Pb-free 209-ball FBGA package IEEE 1149.1 JTAG-Compatible Boundary Scan “ZZ” Sleep Mode option ■ ■ ■ ■ ■ ■ ■ ■ Selection Guide Description Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 133 MHz 6.5 310 120 100 MHz 8.5 290 120 Unit ns mA mA Note 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document Number: 38-05357 Rev. *I • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 23, 2011 [+] Feedback CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 Logic Block Diagram – CY7C1441AV33 (1 M × 36) A 0, A1, A ADDRESS REGISTER A [1:0] MODE ADV CLK BURST Q1 COUNTER AND LOGIC Q0 CLR ADSC ADSP DQ D , DQP D BW D BYTE WRITE REGISTER DQ C, DQP C BYTE WRITE REGISTER DQ B , DQP B BYTE WRITE REGISTER DQ A , DQP A BW A BWE GW CE1 CE2 CE3 OE DQ A , DQPA BYTE WRITE REGISTER BYTE WRITE REGISTER DQ D , DQP D BYTE WRITE REGISTER DQ C, DQP C BYTE WRITE REGISTER DQ B , DQP B BW B BYTE WRITE REGISTER BW C MEMORY ARRAY SENSE AMPS OUTPUT BUFFERS DQ s DQP A DQP B DQP C DQP D ENABLE REGISTER INPUT REGISTERS ZZ SLEEP CONTROL Logic Block Diagram – CY7C1443AV33 (2 M × 18) A 0,A1,A MODE ADDRESS REGISTER A[1:0] ADV CLK BURST Q1 COUNTER AND LOGIC CLR Q0 ADSC ADSP DQ B ,DQP B WRITE REGISTER DQ B ,DQP B WRITE DRIVER BW B MEMORY ARRAY SENSE AMPS OUTPUT BUFFERS BW A BWE GW DQ A ,DQP A WRITE REGISTER DQ A ,DQP A WRITE DRIVER INPUT REGISTERS DQs DQP A DQP B CE 1 CE 2 CE 3 OE ENABLE REGISTER ZZ SLEEP CONTROL Document Number: 38-05357 Rev. *I Page 2 of 34 [+] Feedback CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 Logic Block Diagram – CY7C1447AV33 (512 K × 72) A0, A1,A ADDRESS REGISTER A[1:0] MODE ADV CLK BURST Q1 COUNTER AND LOGIC CLR Q0 ADSC ADSP BW H DQ H , DQPH WRITE REGISTER DQ F, DQPF WRITE REGISTER DQ F, DQPF WRITE REGISTER DQ E , DQPE WRITE REGISTER DQ D , DQPD WRITE REGISTER DQ H , DQPH WRITE DRIVER DQ G , DQPG WRITE DRIVER DQ F, DQPF WRITE DRIVER DQ E , DQPE BYTE “a” WRITE DRIVER DQ D , DQPD WRITE DRIVER DQ C, DQPC WRITE DRIVER SENSE AMPS BW G BW F BW E MEMORY ARRAY BW D BW C DQ C, DQPC WRITE REGISTER OUTPUT BUFFERS BW B DQ B , DQPB WRITE REGISTER DQ B , DQPB WRITE DRIVER DQ A , DQPA WRITE DRIVER BW A BWE GW CE1 CE2 CE3 OE DQ A , DQPA WRITE REGISTER DQs DQP A DQP B DQP C DQP D DQP E DQP F DQP G DQP H ENABLE REGISTER INPUT REGISTERS ZZ SLEEP CONTROL Document Number: 38-05357 Rev. *I Page 3 of 34 [+] Feedback CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 Contents Pin Configurations ........................................................... 5 Pin Definitions .................................................................. 8 Functional Overview ...................................................... 10 Single Read Accesses .............................................. 10 Single Write Accesses Initiated by ADSP ................. 10 Single Write Accesses Initiated by ADSC ................. 10 Burst Sequences ....................................................... 10 Sleep Mode ............................................................... 10 Interleaved Burst Address Table (MODE = Floating or VDD) ............................................. 10 Linear Burst Address Table (MODE = GND) ................ 10 ZZ Mode Electrical Characteristics ............................... 11 Truth Table ...................................................................... 11 Partial Truth Table for Read/Write ................................ 12 Truth Table for Read/Write ............................................ 12 Truth Table for Read/Write ............................................ 12 IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13 Disabling the JTAG Feature ...................................... 13 TAP Controller State Diagram ....................................... 13 Test Access Port (TAP) ............................................. 13 TAP Controller Block Diagram ...................................... 13 PERFORMING A TAP RESET .................................. 13 TAP REGISTERS ...................................................... 13 TAP Instruction Set ................................................... 14 TAP Timing ...................................................................... 15 TAP AC Switching Characteristics ............................... 16 3.3 V TAP AC Test Conditions ....................................... 17 3.3 V TAP AC Output Load Equivalent ......................... 17 2.5 V TAP AC Test Conditions ....................................... 17 2.5V TAP AC Output Load Equivalent .......................... 17 TAP DC Electrical Characteristics and Operating Conditions ..................................................... 17 Identification Register Definitions ................................ 18 Scan Register Sizes ....................................................... 18 Identification Codes ....................................................... 18 165-ball FBGA Boundary Scan Order ........................... 19 Maximum Ratings ........................................................... 20 Operating Range ............................................................. 20 Electrical Characteristics ............................................... 20 DC Electrical Characteristics ..................................... 20 Capacitance .................................................................... 21 Parameter ........................................................................ 21 Thermal Resistance ........................................................ 21 Switching Characteristics .............................................. 22 Timing Diagrams ............................................................ 23 Ordering Information ...................................................... 27 Ordering Code Definitions ......................................... 27 Package Diagrams .......................................................... 28 Acronyms ........................................................................ 31 Document Conventions ................................................. 31 Units of Measure ....................................................... 31 Document History Page ................................................. 32 Sales, Solutions, and Legal Information ...................... 34 Worldwide Sales and Design Support ....................... 34 Products .................................................................... 34 PSoC Solutions ......................................................... 34 Document Number: 38-05357 Rev. *I Page 4 of 34 [+] Feedback CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 Pin Configurations Figure 1. 100-pin TQFP Pinout A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 DQPC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1441AV33 (1 M × 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA NC NC NC VDDQ VSSQ NC NC DQB DQB VSSQ VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSSQ DQB DQB DQPB NC VSSQ VDDQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 NC NC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1443AV33 (2 M × 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSSQ NC DQPA DQA DQA VSSQ VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA NC NC VSSQ VDDQ NC NC NC 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MODE A A A A A1 A0 NC/72M A VSS VDD A A A A A A A A A MODE A A A A A1 A0 NC/72M A VSS VDD Document Number: 38-05357 Rev. *I A A A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Page 5 of 34 [+] Feedback CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 Pin Configurations (continued) 165-ball FBGA (15 × 17 × 1.4 mm) Pinout CY7C1441AV33 (1 M × 36) 1 A B C D E F G H J K L M N P R NC/288M NC/144M DQPC DQC DQC DQC DQC NC DQD DQD DQD DQD DQPD NC MODE 2 A A NC DQC DQC DQC DQC NC DQD DQD DQD DQD NC NC/72M A 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWC BWD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A 5 BWB BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK 7 BWE GW 8 ADSC OE 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC/1G DQB DQB DQB DQB NC DQA DQA DQA DQA NC A A 11 NC NC/576M DQPB DQB DQB DQB DQB ZZ DQA DQA DQA DQA DQPA A A VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A1 A0 A A CY7C1443AV33 (2 M × 18) 1 A B C D E F G H J K L M N P R NC/288M NC/144M NC NC NC NC NC NC DQB DQB DQB DQB DQPB NC MODE 2 A A NC DQB DQB DQB DQB NC NC NC NC NC NC NC/72M A 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWB NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A 5 NC BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK 7 BWE GW 8 ADSC OE 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC/1G NC NC NC NC NC DQA DQA DQA DQA NC A A 11 A NC/576M DQPA DQA DQA DQA DQA ZZ NC NC NC NC NC A A VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A1 A0 A A Document Number: 38-05357 Rev. *I Page 6 of 34 [+] Feedback CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 Pin Configurations (continued) 209-ball FBGA (14 × 22 × 1.76 mm) Pinout CY7C1447AV33 (512 K × 72) 1 A B C D E F G H J K L M N P R T U V W 2 3 A BWSC BWSH VSS VDDQ VSS VDDQ VSS VDDQ CLK VDDQ VSS VDDQ VSS VDDQ VSS NC/72M A TMS 4 CE2 BWSG 5 ADSP NC288M 6 ADSC BW 7 ADV A NC/576M GW VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A A A 8 CE3 BWSB BWSE NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDO 9 A BWSF BWSA VSS VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ VSS A A TCK 10 11 DQG DQG DQG DQG DQPG DQC DQC DQC DQC NC DQG DQG DQG DQG DQPC DQC DQC DQC DQC NC DQB DQB DQB DQB DQPF DQF DQF DQF DQF NC DQB DQB DQB DQB DQPB DQF DQF DQF DQF NC BWSD NC/144M CE1 NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDI NC/1G VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A A A OE VDD NC NC NC NC VSS NC NC NC ZZ VDD MODE A A1 A0 DQH DQH DQH DQH DQPD DQD DQD DQD DQD DQH DQH DQH DQH DQPH DQD DQD DQD DQD DQA DQA DQA DQA DQPA DQE DQE DQE DQE DQA DQA DQA DQA DQPE DQE DQE DQE DQE Document Number: 38-05357 Rev. *I Page 7 of 34 [+] Feedback CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 Pin Definitions Name A0, A1, A IO InputSynchronous InputSynchronous Description Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit counter. Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. BWA, BWB, BWC, BWD, BWE, BWF, BWG, BWH GW CLK CE1 InputSynchronous InputClock InputSynchronous InputSynchronous InputSynchronous InputAsynchronous Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BWX and BWE). Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external address is loaded. Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. CE3 is assumed active throughout this document for BGA. CE3 is sampled only when a new external address is loaded. Output Enable, Asynchronous Input, Active LOW. Controls the direction of the IO pins. When LOW, the IO pins behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. Advance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it automatically increments the address in a burst cycle. Address Strobe from Processor, Sampled on the Rising Edge of CLK, Active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH Address Strobe from Controller, Sampled on the Rising Edge of CLK, Active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. ZZ “sleep” Input, Active HIGH. When asserted HIGH places the device in a non-time-critical “sleep” condition with data integrity preserved. For normal operation, this pin must be LOW or left floating. ZZ pin has an internal pull down. Bidirectional Data IO lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition.The outputs are automatically tri-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. Bidirectional Data Parity IO Lines. Functionally, these signals are identical to DQs. During write sequences, DQPx is controlled by BW[A:H] correspondingly. Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull up. CE2 CE3 OE ADV ADSP InputSynchronous InputSynchronous ADSC InputSynchronous BWE ZZ InputSynchronous InputAsynchronous IOSynchronous DQs DQPX MODE IOSynchronous Input-Static Document Number: 38-05357 Rev. *I Page 8 of 34 [+] Feedback CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 Pin Definitions (continued) Name VDD VDDQ VSS VSSQ TDO IO Power Supply Ground IO Ground IO Power Supply Power Supply for the IO Circuitry. Ground for the Core of the Device. Ground for the IO Circuitry. Description Power Supply Inputs to the Core of the Device. JTAG serial output Serial Data-Out to the JTAG Circuit. Delivers data on the negative edge of TCK. If the JTAG Synchronous feature is not being utilized, this pin should be left unconnected. This pin is not available on TQFP packages. JTAG serial input Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is Synchronous not being utilized, this pin can be left floating or connected to VDD through a pull up resistor. This pin is not available on TQFP packages. JTAG serial input Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is Synchronous not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. JTAG-Clock Clock Input to the JTAG Circuitry. If the JTAG feature is not being utilized, this pin must be connected to VSS. This pin is not available on TQFP packages. No Connects. Not internally connected to the die. 72M, 144M and 288M are address expansion pins are not internally connected to the die. No Connects. Not internally connected to the die. NC/72M, NC/144M, NC/288M, NC/576M and NC/1G are address expansion pins are not internally connected to the die. TDI TMS TCK NC NC/72M, NC/144M, NC/288M, NC/576M, NC/1G Document Number: 38-05357 Rev. *I Page 9 of 34 [+] Feedback CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t CDV) is 6.5 ns (133-MHz device). The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486™ processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user-selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BWx) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH. HIGH, and (4) the write input signals (GW, BWE, and BWX) indicate a write access. ADSC is ignored if ADSP is active LOW. The addresses presented are loaded into the address register and the burst counter/control logic and delivered to the memory core. The information presented to DQS is written into the specified address location. Byte writes are allowed. All IOs are tri-stated when a write is detected, even a byte write. Since this is a common IO device, the asynchronous OE input signal must be deasserted and the IOs must be tri-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are tri-stated once a write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 provides an on-chip two-bit wraparound burst counter inside the SRAM. The burst counter is fed by A[1:0], and can follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on MODE selects a linear burst sequence. A HIGH on MODE selects an interleaved burst order. Leaving MODE unconnected causes the device to default to a interleaved burst sequence. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Single Read Accesses A single read access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, and (2) ADSP or ADSC is asserted LOW (if the access is initiated by ADSC, the write inputs must be deasserted during this first cycle). The address presented to the address inputs is latched into the address register and the burst counter/control logic and presented to the memory core. If the OE input is asserted LOW, the requested data is available at the data outputs a maximum to tCDV after clock rise. ADSP is ignored if CE1 is HIGH. Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1: A0 00 01 10 11 Second Address A1: A0 01 00 11 10 Third Address A1: A0 10 11 00 01 Fourth Address A1: A0 11 10 01 00 Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted active, and (2) ADSP is asserted LOW. The addresses presented are loaded into the address register and the burst inputs (GW, BWE, and BWX)are ignored during this first clock cycle. If the write inputs are asserted active (see Write Cycle Descriptions table for appropriate states that indicate a write) on the next clock rise, the appropriate data is latched and written into the device. Byte writes are allowed. All IOs are tri-stated during a byte write.Since this is a common IO device, the asynchronous OE input signal must be deasserted and the IOs must be tri-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are tri-stated once a write cycle is detected, regardless of the state of OE. Linear Burst Address Table (MODE = GND) First Address A1: A0 00 01 10 11 Second Address A1: A0 01 10 11 00 Third Address A1: A0 10 11 00 01 Fourth Address A1: A0 11 00 01 10 Single Write Accesses Initiated by ADSC This write access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, (2) ADSC is asserted LOW, (3) ADSP is deasserted Document Number: 38-05357 Rev. *I Page 10 of 34 [+] Feedback CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 ZZ Mode Electrical Characteristics Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Sleep mode standby current Device operation to ZZ ZZ recovery time ZZ active to sleep current ZZ Inactive to exit sleep current Test Conditions ZZ > VDD– 0.2 V ZZ > VDD – 0.2 V ZZ < 0.2 V This parameter is sampled This parameter is sampled Min – – 2tCYC – 0 Max 100 2tCYC – 2tCYC – Unit mA ns ns ns ns Truth Table tThe truth table for CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 follows.[2, 3, 4, 5, 6] Cycle Description Deselected Cycle, Power down Deselected Cycle, Power down Deselected Cycle, Power down Deselected Cycle, Power down Deselected Cycle, Power down Sleep Mode, Power down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Address Used None None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current CE1 CE2 CE3 H L L L X X L L L L L X X H H X H X X H H X H X L X L X X H H H H H X X X X X X X X X X X X X X H X X X L L L L L X X X X X X X X X X X X ZZ L L L L L H L L L L L L L L L L L L L L L L L ADSP X L L H H X L L H H H H H X X H X H H X X H X ADSC L X X L L X X X L L L H H H H H H H H H H H H ADV X X X X X X X X X X X L L L L L L H H H H H H WRITE X X X X X X X X L H H H H H H L L H H H H L L OE X X X X X X L H X L H L H L H X X L H L H X X CLK L–H L–H L–H L–H L–H X L–H L–H L–H L–H L–H L–H L–H L–H L–H L–H L–H L–H L–H L–H L–H L–H L–H DQ Tri-State Tri-State Tri-State Tri-State Tri-State Tri-State Q Tri-State D Q Tri-State Q Tri-State Q Tri-State D D Q Tri-State Q Tri-State D D Notes 2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. 3. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H. 4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the write cycle. 6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). Document Number: 38-05357 Rev. *I Page 11 of 34 [+] Feedback CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 Partial Truth Table for Read/Write Function (CY7C1441AV33)[7, 8] Read Read Write Byte A (DQA, DQPA) Write Byte B(DQB, DQPB) Write Bytes A, B (DQA, DQB, DQPA, DQPB) Write Byte C (DQC, DQPC) Write Bytes C, A (DQC, DQA, DQPC, DQPA) Write Bytes C, B (DQC, DQB, DQPC, DQPB) Write Bytes C, B, A (DQC, DQB, DQA, DQPC, DQPB, DQPA) Write Byte D (DQD, DQPD) Write Bytes D, A (DQD, DQA, DQPD, DQPA) Write Bytes D, B (DQD, DQA, DQPD, DQPA) Write Bytes D, B, A (DQD, DQB, DQA, DQPD, DQPB, DQPA) Write Bytes D, B (DQD, DQB, DQPD, DQPB) Write Bytes D, B, A (DQD, DQC, DQA, DQPD, DQPC, DQPA) Write Bytes D, C, A (DQD, DQB, DQA, DQPD, DQPB, DQPA) Write All Bytes Write All Bytes GW H H H H H H H H H H H H H H H H H L BWE H L L L L L L L L L L L L L L L L X BWD X H H H H H H H H L L L L L L L L X BWC X H H H H L L L L H H H H L L L L X BWB X H H L L H H L L H H L L H H L L X BWA X H L H L H L H L H L H L H L H L X Truth Table for Read/Write Function (CY7C1443AV33)[7] Read Read Write Byte A - (DQA and DQPA) Write Byte B - (DQB and DQPB) Write All Bytes Write All Bytes GW H H H H H L BWE H L L L L X BWB X H H L L X BWA X H L H L X Truth Table for Read/Write Function (CY7C1447AV33)[7, 9] Read Read Write Byte x – (DQx and DQPx) Write All Bytes Write All Bytes GW H H H H L BWE H L L L X BWX X All BW = H L All BW = L X Notes 7. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. 8. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write is done based on which byte write is active. 9. BWx represents any byte write signal BW[A..H].To enable any byte write BWx, a Logic LOW signal should be applied at clock rise.Any number of bye writes can be enabled at the same time for any given write. Document Number: 38-05357 Rev. *I Page 12 of 34 [+] Feedback CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 incorporates a serial boundary scan test access port (TAP). This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 3.3 V or 2.5 V IO logic levels. The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Test MODE SELECT (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See TAP Controller Block Diagram.) Test Data-Out (TDO) The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See TAP Controller State Diagram.) Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull up resistor. TDO should be left unconnected. Upon power up, the device comes up in a reset state which does not interfere with the operation of the device. TAP Controller State Diagram 1 TEST-LOGIC RESET 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 0 0 1 0 1 1 SELECT IR-SCAN 0 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 EXIT2-IR 1 UPDATE-IR 1 0 0 1 0 1 TAP Controller Block Diagram 0 Bypass Register 210 TDI Selection Circuitry Instruction Register 31 30 29 . . . 2 1 0 Selection Circuitry TDO Identification Register x. . . . .210 Boundary Scan Register TCK TM S TAP CONTROLLER Performing a TAP Reset The 0/1 next to each state represents the value of TMS at the rising edge of TCK. A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power up, the TAP is reset internally to ensure that TDO comes up in a High Z state. Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. TAP Registers Registers are connected between the TDI and TDO balls and scan data into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. Document Number: 38-05357 Rev. *I Page 13 of 34 [+] Feedback CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the TAP Controller Block Diagram on page 13. Upon power up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This shifts data through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The boundary scan register is loaded with the contents of the RAM IO ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the IO ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. IDCODE The IDCODE instruction loads a vendor-specific, 32-bit code into the instruction register. It also places the instruction register between the TDI and TDO balls and shifts the IDCODE out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction connects the boundary scan register between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High Z state until the next command is given during the “Update IR” state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output undergoes a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that is captured. Repeatable results may not be possible. To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required—that is, while data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. TAP Instruction Set Overview Eight different instructions are possible with the three bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in this section in detail. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller must be moved into the Update-IR state. Document Number: 38-05357 Rev. *I Page 14 of 34 [+] Feedback CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 EXTEST The EXTEST instruction drives the preloaded data out through the system output pins. This instruction also connects the boundary scan register for serial access between the TDI and TDO in the shift-DR controller state. EXTEST OUTPUT BUS TRI-STATE IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode. The boundary scan register has a special bit located at bit #89 (for 165-ball FBGA package) or bit #138 (for 209-ball FBGA package). When this scan cell, called the “extest output bus tri-state”, is latched into the preload register during the “Update-DR” state in the TAP controller, it directly controls the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it enables the output buffers to drive the output bus. When LOW, this bit places the output bus into a High Z condition. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the “Shift-DR” state. During “Update-DR”, the value loaded into that shift-register cell latches into the preload register. When the EXTEST instruction is entered, this bit directly controls the output Q-bus pins. Note that this bit is pre-set HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the “Test-Logic-Reset” state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. TAP Timing 1 Test Clock (TCK) t TMSS 2 3 4 5 6 t TH t TMSH t TL t CYC T est Mode Select (TMS) t TDIS t TDIH Test Data-In (TDI) t TDOV t TDOX Test Data-Out (TDO) DON’T CARE UNDEFINED Document Number: 38-05357 Rev. *I Page 15 of 34 [+] Feedback CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 TAP AC Switching Characteristics Over the Operating Range[9, 10] Parameter Clock tTCYC tTF tTH tTL Output Times tTDOV tTDOX Setup Times tTMSS tTDIS tCS Hold Times tTMSH tTDIH tCH TMS Hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise 5 5 5 – – – ns ns ns TMS Setup to TCK Clock Rise TDI Setup to TCK Clock Rise Capture Setup to TCK Rise 5 5 5 – – – ns ns ns TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid – 0 10 – ns ns TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH time TCK Clock LOW time 50 – 20 20 – 20 – – ns MHz ns ns Description Min Max Unit Notes 9. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 10. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns. Document Number: 38-05357 Rev. *I Page 16 of 34 [+] Feedback CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 3.3 V TAP AC Test Conditions Input pulse levels ...............................................VSS to 3.3 V Input rise and fall times ...................................................1 ns Input timing reference levels ......................................... 1.5 V Output reference levels ................................................ 1.5 V Test load termination supply voltage ............................. 1.5 V 2.5 V TAP AC Test Conditions Input pulse levels ............................................... VSS to 2.5 V Input rise and fall time ....................................................1 ns Input timing reference levels ....................................... 1.25 V Output reference levels .............................................. 1.25 V Test load termination supply voltage .......................... 1.25 V 3.3 V TAP AC Output Load Equivalent 1.5V 50 Ω T DO Z O = 50 Ω 20p F 2.5V TAP AC Output Load Equivalent 1.25V 50 Ω T DO Z O = 50 Ω 20p F TAP DC Electrical Characteristics and Operating Conditions (0 °C < TA < +70 °C; VDD = 3.135 V to 3.6 V unless otherwise noted)[11] Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current GND < VIN < VDDQ IOH = –4.0 mA IOH = –1.0 mA IOH = –100 µA IOL = 8.0 mA IOL = 1.0 mA IOL = 100 µA Conditions VDDQ = 3.3 V VDDQ = 2.5 V VDDQ = 3.3 V VDDQ = 2.5 V VDDQ = 3.3 V VDDQ = 2.5 V VDDQ = 3.3 V VDDQ = 2.5 V VDDQ = 3.3 V VDDQ = 2.5 V VDDQ = 3.3 V VDDQ = 2.5 V Min 2.4 2.0 2.9 2.1 – – – – 2.0 1.7 –0.3 –0.3 –5 Max – – – – 0.4 0.4 0.2 0.2 VDD + 0.3 VDD + 0.3 0.8 0.7 5 Unit V V V V V V V V V V V V µA Note 11. All voltages referenced to VSS (GND). Document Number: 38-05357 Rev. *I Page 17 of 34 [+] Feedback CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 Identification Register Definitions Instruction Field Revision Number (31:29) Device Depth (28:24) Architecture/Memory Type(23:18)[12] Bus Width/Density(17:12) Cypress JEDEC ID Code (11:1) ID Register Presence Indicator (0) CY7C1441AV33 CY7C1443AV33 CY7C1447AV33 (1 M × 36) (2 M × 18) (512 K × 72) 000 01011 000001 100111 00000110100 1 000 01011 000001 010111 00000110100 1 000 01011 000001 110111 00000110100 1 Description Describes the version number. Reserved for Internal Use Defines memory type and architecture Defines width and density Allows unique identification of SRAM vendor. Indicates the presence of an ID register. Scan Register Sizes Register Name Instruction Bypass Bypass ID Boundary Scan Order (165-ball FBGA package) Boundary Scan Order (209-ball FBGA package) Bit Size (× 36) 3 1 32 89 – Bit Size (× 18) 3 1 32 89 – Bit Size (× 18) 3 1 32 – 138 Identification Codes Instruction EXTEST IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD RESERVED RESERVED BYPASS Code 000 001 010 011 100 101 110 111 Captures IO ring contents. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. Captures IO ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High Z state. Do Not Use: This instruction is reserved for future use. Captures IO ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Description Note 12. Bit #24 is “1” in the ID Register Definitions for both 2.5 V and 3.3 V versions of this device. Document Number: 38-05357 Rev. *I Page 18 of 34 [+] Feedback CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 165-ball FBGA Boundary Scan Order[13, 14] CY7C1441AV33 (1 M × 36), CY7C1443AV33 (2 M × 18) Bit # Ball ID Bit # Ball ID 1 26 E11 N6 2 27 D11 N7 3 N10 28 G10 4 P11 29 F10 5 P8 30 E10 6 R8 31 D10 7 R9 32 C11 8 P9 33 A11 9 P10 34 B11 10 R10 35 A10 11 R11 36 B10 12 H11 37 A9 13 N11 38 B9 14 M11 39 C10 15 L11 40 A8 16 K11 41 B8 17 J11 42 A7 18 M10 43 B7 19 L10 44 B6 20 K10 45 A6 21 J10 46 B5 22 H9 47 A5 23 H10 48 A4 24 G11 49 B4 25 F11 50 B3 Bit # 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Ball ID A3 A2 B2 C2 B1 A1 C1 D1 E1 F1 G1 D2 E2 F2 G2 H1 H3 J1 K1 L1 M1 J2 K2 L2 M2 Bit # 76 77 78 79 80 81 82 83 84 85 86 87 88 89 Ball ID N1 N2 P1 R1 R2 P3 R3 P2 R4 P4 N5 P6 R6 Internal Notes 13. Balls which are NC (No Connect) are preset LOW. 14. Bit# 89 is preset HIGH. Document Number: 38-05357 Rev. *I Page 19 of 34 [+] Feedback CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage Temperature ............................... –65 C to +150 C Ambient Temperature with Power Applied ......................................... –55C to +125 C Supply Voltage on VDD Relative to GND .....–0.3 V to +4.6 V Supply Voltage on VDDQ Relative to GND .... –0.3 V to +VDD DC Voltage Applied to Outputs in Tri-State ........................................–0.5 V to VDDQ + 0.5 V DC Input Voltage ................................ –0.5 V to VDD + 0.5 V Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage ........................................ > 2001 V (per MIL-STD-883, Method 3015) Latch-up Current ................................................... > 200 mA Operating Range Range Commercial Industrial Ambient Temperature 0 °C to +70 °C –40 °C to +85 °C VDD 3.3 V– 5% / + 10% VDDQ 2.5 V – 5% to VDD Electrical Characteristics Over the Operating Range[15, 16] Over the Operating Range Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power Supply Voltage IO Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Input LOW Voltage[15] Voltage[15] for 3.3 V IO for 2.5 V IO for 3.3 V IO, IOH = –4.0 mA for 2.5 V IO, IOH = –1.0 mA for 3.3 V IO, IOL = 8.0 mA for 2.5 V IO, IOL = 1.0 mA for 3.3 V IO for 2.5 V IO for 3.3 V IO for 2.5 V IO Input Leakage Current except ZZ and MODE Input Current of MODE Input Current of ZZ IOZ IDD ISB1 Output Leakage Current VDD Operating Supply Current GND  VI  VDDQ Input = VSS Input = VDD Input = VSS Input = VDD GND  VI  VDDQ, Output Disabled VDD = Max, IOUT = 0 mA, f = fMAX = 1/tCYC 7.5-ns cycle, 133 MHz 10-ns cycle, 100 MHz All Speeds Test Conditions Min 3.135 3.135 2.375 2.4 2.0 – – 2.0 1.7 –0.3 –0.3 –5 –30 – –5 – –5 – – – Max 3.6 VDD 2.625 – – 0.4 0.4 VDD + 0.3 V VDD + 0.3 V 0.8 0.7 5 – 5 – 30 5 310 290 180 Unit V V V V V V V V V V V A A A A A A mA mA mA DC Electrical Characteristics Automatic CE Power down Max VDD, Device Deselected, Current—TTL Inputs VIN  VIH or VIN  VIL, f = fMAX, inputs switching ISB2 All speeds Automatic CE Power down Max VDD, Device Deselected, Current—CMOS Inputs VIN  VDD – 0.3 V or VIN  0.3 V, f = 0, inputs static – 120 mA Notes 15. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2). 16. TPower-up: Assumes a linear ramp from 0 V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD. Document Number: 38-05357 Rev. *I Page 20 of 34 [+] Feedback CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 Electrical Characteristics (continued) Over the Operating Range[15, 16] Over the Operating Range Parameter ISB3 Description Test Conditions Min – Max 180 DC Electrical Characteristics (continued) Unit mA Automatic CE Power down Max VDD, Device Deselected, All Speeds Current—CMOS Inputs VIN  VDDQ – 0.3 V or VIN  0.3 V, f = fMAX, inputs switching Automatic CE Power down Max VDD, Device Deselected, Current—TTL Inputs VIN  VDD – 0.3 V or VIN  0.3 V, f = 0, inputs static All Speeds ISB4 – 135 mA Capacitance Parameter[17] CIN CCLK CIO Description Input Capacitance Clock Input Capacitance Input/Output Capacitance Test Conditions TA = 25 C, f = 1 MHz, VDD = 3.3 V, VDDQ = 2.5 V 100-pin TQFP 165-ball FBGA 209-ball FBGA Unit Max Max Max 6.5 3 5.5 7 7 6 5 5 7 pF pF pF Thermal Resistance Parameter[17] JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 100-pin TQFP 165-ball FBGA 209-ball FBGA Unit Package Package Package 25.21 2.28 20.8 3.2 25.31 4.48 C/W C/W Figure 2. AC Test Loads and Waveforms 3.3 V IO Test Load OUTPUT Z0 = 50  3.3 V OUTPUT RL = 50  R = 317  VDDQ 5 pF GND R = 351  10% ALL INPUT PULSES 90% 90% 10%  1 ns VT = 1.5 V  1 ns (a) 2.5 V IO Test Load OUTPUT Z0 = 50  INCLUDING JIG AND SCOPE (b) (c) 2.5 V OUTPUT RL = 50  VT = 1.25 V R = 1667  VDDQ 5 pF GND R = 1538  10% ALL INPUT PULSES 90% 90% 10%  1 ns  1 ns (a) INCLUDING JIG AND SCOPE (b) (c) Note 17. Tested initially and after any design or process change that may affect these parameters. Document Number: 38-05357 Rev. *I Page 21 of 34 [+] Feedback CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 Switching Characteristics Over the Operating Range[18, 19] Parameter tPOWER Clock tCYC tCH tCL Output Times tCDV tDOH tCLZ tCHZ tOEV tOELZ tOEHZ Setup Times tAS tADS tADVS tWES tDS tCES Hold Times tAH tADH tWEH tADVH tDH tCEH Address Hold After CLK Rise ADSP, ADSC Hold After CLK Rise GW, BWE, BWX Hold After CLK Rise ADV Hold After CLK Rise Data Input Hold After CLK Rise Chip Enable Hold After CLK Rise 0.5 0.5 0.5 0.5 0.5 0.5 – – – – – – 0.5 0.5 0.5 0.5 0.5 0.5 – – – – – – ns ns ns ns ns ns Address Setup Before CLK Rise ADSP, ADSC Setup Before CLK Rise ADV Setup Before CLK Rise GW, BWE, BWX Setup Before CLK Rise Data Input Setup Before CLK Rise Chip Enable Setup 1.5 1.5 1.5 1.5 1.5 1.5 – – – – – – 1.5 1.5 1.5 1.5 1.5 1.5 – – – – – – ns ns ns ns ns ns Data Output Valid After CLK Rise Data Output Hold After CLK Rise Clock to Low Z[21, 22, 23] Clock to High Z[21, 22, 23] Z[21, 22, 23] OE LOW to Output Valid OE LOW to Output Low OE HIGH to Output High Z[21, 22, 23] – 2.5 2.5 – – 0 – 6.5 – – 3.8 3.0 – 3.0 – 2.5 2.5 0 – 0 – 8.5 – – 4.5 3.8 – 4.0 ns ns ns ns ns ns ns Clock Cycle Time Clock HIGH Clock LOW 7.5 2.5 2.5 – – – 10 3.0 3.0 – – – ns ns ns Description VDD (Typical) to the first Access[20] -133 Min 1 Max – Min 1 -100 Max – Unit ms Notes 18. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V. 19. Test conditions shown in (a) of Figure 2 on page 21 unless otherwise noted. 20. This part has a voltage regulator internally; tPOWER is the time that the power must be supplied above VDD(minimum) initially, before a read or write operation can be initiated. 21. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 2 on page 21. Transition is measured ± 200 mV from steady-state voltage. 22. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High Z prior to Low Z under the same system conditions. 23. This parameter is sampled and not 100% tested. Document Number: 38-05357 Rev. *I Page 22 of 34 [+] Feedback CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 Timing Diagrams Figure 3. Read Cycle Timing[24] tCYC CLK t CH t CL t ADS tADH ADSP t ADS tADH ADSC t AS tAH ADDRESS A1 t WES t WEH A2 G W, BWE,BW X t CES t CEH Deselect Cycle CE t ADVS t ADVH ADV ADV suspends burst OE t OEV t CLZ t OEHZ t OELZ t CDV t DOH t CHZ Data Out (Q) High-Z Q(A1) t CDV Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A2 + 2) Burst wraps around to its initial state Single READ DON’T CARE BURST READ UNDEFINED . Note 24. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. Document Number: 38-05357 Rev. *I Page 23 of 34 [+] Feedback CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 Timing Diagrams (continued) Figure 4. Write Cycle Timing[25, 26] t CYC CLK t CH t CL t ADS tADH ADSP t ADS tADH ADSC extends burst t ADS tADH ADSC t AS tAH ADDRESS A1 A2 Byte write signals are ignored for first cycle when ADSP initiates burst A3 t WES tWEH BWE, BW X t WES t WEH GW t CES tCEH CE t ADVS tADVH ADV ADV suspends burst OE t DS t DH D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) Data in (D) High-Z t D(A1) OEHZ D ata Out (Q) BURST READ Single WRITE BURST WRITE Extended BURST WRITE DON’T CARE . UNDEFINED Notes 25. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 26. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW Document Number: 38-05357 Rev. *I Page 24 of 34 [+] Feedback CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 Timing Diagrams (continued) Figure 5. Read/Write Cycle Timing[27, 28, 29] tCYC CLK t CH t CL t ADS tADH ADSP ADSC t AS tAH ADDRESS A1 A2 A3 t WES t WEH A4 A5 A6 BWE, BW X t CES tCEH CE ADV OE t DS tDH t OELZ Data In (D) D ata Out (Q) High-Z t OEHZ D(A3) t CDV D(A5) D(A6) Q(A1) Q(A2) Single WRITE DON’T CARE Q(A4) Q(A4+1) BURST READ UNDEFINED Q(A4+2) Q(A4+3) Back-to-Back WRITEs Back-to-Back READs . Note 27. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 28. The data bus (Q) remains in high Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 29. GW is HIGH. Document Number: 38-05357 Rev. *I Page 25 of 34 [+] Feedback CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 Timing Diagrams (continued) Figure 6. ZZ Mode Timing[30, 31] CLK t ZZ t ZZREC ZZ t ZZI I SUPPLY I DDZZ t RZZI DESELECT or READ Only A LL INPUTS (except ZZ) Outputs (Q) High-Z DON’T CARE Notes 30. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 31. DQs are in high Z when exiting ZZ sleep mode. Document Number: 38-05357 Rev. *I Page 26 of 34 [+] Feedback CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 Ordering Information Cypress offers other versions of this type of product in different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products, or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Speed (MHz) 133 Ordering Code CY7C1441AV33-133AXC CY7C1441AV33-133AXI CY7C1441AV33-133BZI CY7C1441AV33-133BZXI Package Diagram Part and Package Type 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free 51-85165 165-ball Fine-Pitch Ball Grid Array (15 × 17 × 1.4 mm) 51-85165 165-ball Fine-Pitch Ball Grid Array (15 × 17 × 1.4 mm) Pb-free Ordering Code Definitions CY 7C 1441 A V33 - 133 XX X X Temperature Range: X = C or I C = Commercial; I = Industrial Pb-free Package Type: XX = A or BZ A = 100-pin TQFP BZ = 165-ball FBGA Frequency Range: 133 MHz VDD = 3.3 V Process Technology:  90 nm 1441 = FT, 1 Mb × 36 (36 Mb) Marketing Code: 7C = SRAMs Company ID: CY = Cypress Document Number: 38-05357 Rev. *I Page 27 of 34 [+] Feedback CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 Package Diagrams Figure 7. 100-pin TQFP (14 × 20 × 1.4 mm), 51-85050 51-85050 *D Document Number: 38-05357 Rev. *I Page 28 of 34 [+] Feedback CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 Package Diagrams (continued) Figure 8. 165-ball FBGA (15 × 17 × 1.4 mm), 51-85165 51-85165 *B Document Number: 38-05357 Rev. *I Page 29 of 34 [+] Feedback CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 Package Diagrams (continued) Figure 9. 209-ball FBGA (14 × 22 × 1.76 mm), 51-85167 51-85167 *A Document Number: 38-05357 Rev. *I Page 30 of 34 [+] Feedback CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 Acronyms Acronym CMOS FBGA I/O JTAG LSB MSB OE SRAM TAP TCK TDI TDO TMS TQFP Description complementary metal oxide semiconductor fine-pitch ball grid array input/output Joint Test Action Group least significant bit most significant bit output enable static random access memory test access port test clock test data-in test data-out test mode select thin quad flat pack Document Conventions Units of Measure Symbol °C µA mA mm ms MHz ns  % pF V W degree Celcius micro Amperes milli Amperes milli meter milli seconds Mega Hertz nano seconds ohms percent pico Farad Volts Watts Unit of Measure Document Number: 38-05357 Rev. *I Page 31 of 34 [+] Feedback CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 Document History Page Document Title: CY7C1441AV33/CY7C1443AV33/CY7C1447AV33, 36-Mbit (1 M × 36/2 M × 18/512 K × 72) Flow-Through SRAM Document Number: 38-05357 REV. ** *A ECN NO. 124459 254910 Issue Date 03/06/03 See ECN Orig. of Change CJM SYT New Data Sheet Part number changed from previous revision. New and old part number differ by the letter “A” Modified Functional Block diagrams Modified switching waveforms Added Footnote #13 (32-Bit Vendor I.D Code changed) Added Boundary scan information Added IDD, IX and ISB values in the DC Electrical Characteristics Added tPOWER specifications in Switching Characteristics table Removed 119 PBGA Package Changed 165 FBGA Package from BB165C (15 x 17 x 1.20 mm) to BB165 (15 x 17 x 1.40 mm) Changed 209-Lead PBGA BG209 (14 x 22 x 2.20 mm) to BB209A (14 x 22 x 1.76 mm) Removed 150 and 117 MHz Speed Bins Changed JA and JC from TBD to 25.21 and 2.58 C/W respectively for TQFP Package on Pg # 21 Added lead-free information for 100-pin TQFP, 165 FBGA and 209 BGA Packages. Added comment of ‘Lead-free BG and BZ packages availability’ below the Ordering Information Changed H9 pin from VSSQ to VSS on the Pin Configuration table for 209 FBGA Changed the test condition from VDD = Min. to VDD = Max for VOL in the Electrical Characteristics table. Replaced the TBD’s for IDD, ISB1, ISB2, ISB3 and ISB4 to their respective values. Replaced TBD’s for JA and JC to their respective values for 165 fBGA and 209 fBGA packages on the Thermal Resistance table. Changed CIN,CCLK and CIO to 6.5, 3 and 5.5 pF from 5, 5 and 7 pF for TQFP Package. Removed “Lead-free BG and BZ packages availability” comment below the Ordering Information Modified Address Expansion balls in the pinouts for 165 FBGA and 209 BGA Packages as per JEDEC standards and updated the Pin Definitions accordingly Modified VOL, VOH test conditions Replaced TBD to 100 mA for IDDZZ Changed CIN, CCLK and CIO to 7, 7and 6 pF from 5, 5 and 7 pF for 165 FBGA Package. Added Industrial Temperature Grade Changed ISB2 and ISB4 from 100 and 110 mA to 120 and 135 mA respectively Updated the Ordering Information by shading and unshading MPNs as per availability Description of Change *B 300131 See ECN SYT *C 320813 See ECN SYT *D 331551 See ECN SYT Document Number: 38-05357 Rev. *I Page 32 of 34 [+] Feedback CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 Document History Page (continued) Document Title: CY7C1441AV33/CY7C1443AV33/CY7C1447AV33, 36-Mbit (1 M × 36/2 M × 18/512 K × 72) Flow-Through SRAM Document Number: 38-05357 REV. *E ECN NO. 417547 Issue Date See ECN Orig. of Change RXU Description of Change Converted from Preliminary to Final. Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court”. Changed IX current value in MODE from –5 & 30 A to –30 & 5 A respectively and also Changed IX current value in ZZ from –30 & 5 A to –5 & 30 A respectively on page# 19. Modified test condition in note# 8 from VIH < VDD to VIH VDD. Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the Electrical Characteristics Table. Replaced Package Name column with Package Diagram in the Ordering Information table. Replaced Package Diagram of 51-85050 from *A to *B Updated the Ordering Information. Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND. Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table. Updated the Ordering Information table. *F 473650 See ECN VKN *G 2447027 See ECN VKN/AESA Corrected typo in the Ordering Information table Corrected typo in the CY7C1447AV33 ‘s Logic Block diagram Updated the x72 block diagram NJY OSN Removed inactive part numbers from Ordering Information table; Updated package diagrams. Adeed Ordering Code Definitions. Updated Package Diagrams. Added Acronyms and Units of Measure. Updated in new template. *H *I 2898501 3263570 03/24/2010 05/23/2011 Document Number: 38-05357 Rev. *I Page 33 of 34 [+] Feedback CY7C1441AV33 CY7C1443AV33, CY7C1447AV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2003-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05357 Rev. *I Revised May 23, 2011 Page 34 of 34 i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback