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The fact that Infineon offers the following product as part of the Infineon product
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Infineon continues to support existing part numbers. Please continue to use the
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CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
36-Mbit (1M × 36/2M × 18)
Flow-Through SRAM (With ECC)
36-Mbit (1M × 36/2M × 18) Flow-Through SRAM (With ECC)
Features
Functional Description
■
Supports 133-MHz bus operations
■
1M × 36/2M × 18 common I/O
■
3.3 V core power supply
■
2.5 V or 3.3 V I/O power supply
■
Fast clock-to-output times
❐ 6.5 ns (133 MHz version)
■
Provide high-performance 2-1-1-1 access rate
■
User-selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■
Separate processor and controller address strobes
■
Synchronous self-timed write
■
Asynchronous output enable
■
CY7C1441KV33, CY7C1443KV33, and CY7C1441KVE33 are
available in JEDEC-standard 100-pin TQFP and 165-ball
FBGA Pb-free packages.
■
IEEE 1149.1 JTAG-Compatible Boundary Scan
■
“ZZ” Sleep Mode option
■
On-chip error correction code (ECC) to reduce soft error rate
(SER)
The CY7C1441KV33/CY7C1443KV33/CY7C1441KVE33 are
3.3 V, 1M × 36/2M × 18/1M × 36 synchronous flow-through
SRAMs, respectively designed to interface with high-speed
microprocessors with minimum glue logic. Maximum access
delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip
counter captures the first address in a burst and increments the
address automatically for the rest of the burst access. All
synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock (CLK) input. The synchronous
inputs include all addresses, all data inputs, address-pipelining
Chip Enable (CE1), depth-expansion Chip Enables (CE2 and
CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write
Enables (BWx, and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and the ZZ
pin.
The CY7C1441KV33/CY7C1443KV33/CY7C1441KVE33 allow
either interleaved or linear burst sequences, selected by the
MODE input pin. A HIGH selects an interleaved burst sequence,
while a LOW selects a linear burst sequence. Burst accesses
can be initiated with the Processor Address Strobe (ADSP) or the
cache Controller Address Strobe (ADSC) inputs. Address
advancement is controlled by the Address Advancement (ADV)
input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV).
The
CY7C1441KV33/CY7C1443KV33/CY7C1441KVE33
operate from a +3.3 V core power supply while all outputs may
operate with either a +2.5 V or +3.3 V supply. All inputs and
outputs are JEDEC-standard JESD8-5-compatible.
Selection Guide
Description
133 MHz
Unit
6.5
ns
× 18
150
mA
× 36
170
Maximum access time
Maximum operating current
Cypress Semiconductor Corporation
Document Number: 001-66677 Rev. *J
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 5, 2019
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Logic Block Diagram – CY7C1441KV33
ADDRESS
REGISTER
A 0, A1, A
A [1:0]
MODE
Q1
ADV
BURST
COUNTER
AND LOGIC
Q0
CLR
CLK
ADSC
ADSP
DQ D , DQP D
DQ D , DQP D
BW D
BYTE
BYTE
WRITE REGISTER
WRITE REGISTER
DQ C, DQP C
DQ C, DQP C
BW C
BYTE
BYTE
WRITE REGISTER
WRITE REGISTER
DQ B , DQP B
BW B
DQ B , DQP B
BYTE
BYTE
WRITE REGISTER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQ s
DQP A
DQP B
DQP C
DQP D
WRITE REGISTER
DQ A , DQP A
BW A
BWE
DQ A , DQPA
BYTE
BYTE
WRITE REGISTER
WRITE REGISTER
INPUT
REGISTERS
GW
ENABLE
REGISTER
CE1
CE2
CE3
OE
ZZ
SLEEP
CONTROL
Logic Block Diagram – CY7C1443KV33
A0,A1,A
ADDRESS
REGISTER
A[1:0]
MODE
BURST Q1
COUNTER AND
LOGIC
CLR
Q0
ADV
CLK
ADSC
ADSP
BW B
BW A
DQ B ,DQP B
WRITE REGISTER
DQ A ,DQP A
WRITE REGISTER
DQ B ,DQP B
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQs
DQP A
DQP B
DQ A ,DQP A
WRITE DRIVER
BWE
GW
CE 1
CE 2
CE 3
ENABLE
REGISTER
INPUT
REGISTERS
OE
ZZ
SLEEP
CONTROL
Document Number: 001-66677 Rev. *J
Page 2 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Logic Block Diagram – CY7C1441KVE33
ADDRESS
REGISTER
A0, A1, A
A[1:0]
MODE
BURST Q1
COUNTER
AND LOGIC
Q0
CLR
ADV
CLK
ADSC
ADSP
DQD, DQPD
BWD
BYTE
WRITE REGISTER
DQC, DQPC
BWC
BYTE
WRITE REGISTER
DQD, DQPD
BYTE
WRITE REGISTER
DQC, DQPC
BYTE
WRITE REGISTER
DQB, DQPB
BWB
DQB, DQPB
BYTE
BYTE
WRITE REGISTER
MEMORY
ARRAY
SENSE
AMPS
ECC
DECODER
OUTPUT
BUFFERS
DQs
DQPA
DQPB
DQPC
DQPD
WRITE REGISTER
DQA, DQPA
BWA
BWE
DQA, DQPA
BYTE
BYTE
WRITE REGISTER
WRITE REGISTER
GW
ENABLE
REGISTER
CE1
CE2
ECC
ENCODER
INPUT
REGISTERS
CE3
OE
ZZ
SLEEP
CONTROL
Document Number: 001-66677 Rev. *J
Page 3 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Contents
Pin Configurations ........................................................... 5
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 8
Single Read Accesses ................................................ 8
Single Write Accesses Initiated by ADSP ................... 8
Single Write Accesses Initiated by ADSC ................... 9
Burst Sequences ......................................................... 9
Sleep Mode ................................................................. 9
On-Chip ECC .............................................................. 9
Interleaved Burst Address Table ................................. 9
Linear Burst Address Table ......................................... 9
ZZ Mode Electrical Characteristics .............................. 9
Truth Table ...................................................................... 10
Partial Truth Table for Read/Write ................................ 11
Partial Truth Table for Read/Write ................................ 11
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 12
Disabling the JTAG Feature ...................................... 12
Test Access Port (TAP) ............................................. 12
PERFORMING A TAP RESET .................................. 12
TAP REGISTERS ...................................................... 12
TAP Instruction Set ................................................... 13
TAP Controller State Diagram ....................................... 14
TAP Controller Block Diagram ...................................... 14
TAP Timing ...................................................................... 14
TAP AC Switching Characteristics ............................... 15
3.3 V TAP AC Test Conditions ....................................... 15
3.3 V TAP AC Output Load Equivalent ......................... 15
2.5 V TAP AC Test Conditions ....................................... 15
2.5 V TAP AC Output Load Equivalent ......................... 15
Document Number: 001-66677 Rev. *J
TAP DC Electrical Characteristics
and Operating Conditions ............................................. 16
Identification Register Definitions ................................ 17
Scan Register Sizes ....................................................... 17
Identification Codes ....................................................... 17
Boundary Scan Order .................................................... 18
Maximum Ratings ........................................................... 19
Operating Range ............................................................. 19
Neutron Soft Error Immunity ......................................... 19
Electrical Characteristics ............................................... 19
DC Characteristics .................................................... 19
Capacitance .................................................................... 21
Thermal Resistance ........................................................ 21
AC Test Loads and Waveforms ..................................... 21
Switching Characteristics .............................................. 22
Timing Diagrams ............................................................ 23
Ordering Information ...................................................... 27
Ordering Code Definitions ......................................... 27
Package Diagrams .......................................................... 28
Acronyms ........................................................................ 30
Document Conventions ................................................. 30
Units of Measure ....................................................... 30
Document History Page ................................................. 31
Sales, Solutions, and Legal Information ...................... 32
Worldwide Sales and Design Support ....................... 32
Products .................................................................... 32
PSoC® Solutions ...................................................... 32
Cypress Developer Community ................................. 32
Technical Support ..................................................... 32
Page 4 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Pin Configurations
NC
NC
NC
CY7C1443KV33
(2M × 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Document Number: 001-66677 Rev. *J
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
NC
VSSQ
VDDQ
NC
NC
NC
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDDQ
VSSQ
NC
NC
DQB
DQB
VSSQ
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
VSSQ
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
NC/72M
A
VSS
VDD
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
CY7C1441KV33/CY7C1441KVE33 66
65
64
(1M × 36)
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
NC/72M
A
VSS
VDD
DQPC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
A
A
CE1
CE2
NC
NC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
A
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
Figure 1. 100-pin TQFP Pinout
Page 5 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Pin Configurations (continued)
Figure 2. 165-ball FBGA Pinout
CY7C1441KV33 (1M × 36)
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/288M
1
A
CE1
BWC
BWB
CE3
BWE
ADSC
ADV
A
NC
NC/144M
A
CE2
BWD
BWA
CLK
GW
OE
ADSP
A
NC/576M
DQPC
DQC
NC
DQC
VDDQ
VDDQ
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VSS
VDDQ
NC/1G
DQB
DQPB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
NC
DQD
DQC
NC
DQD
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
NC
VDDQ
DQB
NC
DQA
DQB
ZZ
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQPD
DQD
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
A
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
DQA
DQPA
NC
NC/72M
A
A
TDI
A1
TDO
A
A
A
A
R
MODE
A
A
A
TMS
A0
TCK
A
A
A
A
Document Number: 001-66677 Rev. *J
Page 6 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Pin Definitions
Name
A0, A1, A
I/O
Description
Input-Synchronous Address Inputs Used to Select One of the Address Locations. Sampled at the
rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are
sampled active. A[1:0] feed the 2-bit counter.
BWA, BWB, BWC, BWD Input-Synchronous Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to
the SRAM. Sampled on the rising edge of CLK.
GW
CLK
Input-Synchronous Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of
CLK, a global write is conducted (ALL bytes are written, regardless of the values on
BWX and BWE).
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
CE1
Input-Synchronous Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1
is HIGH. CE1 is sampled only when a new external address is loaded.
CE2
Input-Synchronous Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3 to select/deselect the device. CE2 is sampled only when
a new external address is loaded.
CE3
Input-Synchronous Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to select/deselect the device. CE3 is assumed active
throughout this document for BGA. CE3 is sampled only when a new external address
is loaded.
OE
Input-Asynchronous Output Enable, Asynchronous Input, Active LOW. Controls the direction of the I/O
pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins
are tristated, and act as input data pins. OE is masked during the first clock of a read
cycle when emerging from a deselected state.
ADV
Input-Synchronous Advance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it
automatically increments the address in a burst cycle.
ADSP
Input-Synchronous Address Strobe from Processor, Sampled on the Rising Edge of CLK, Active
LOW. When asserted LOW, addresses presented to the device are captured in the
address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC
are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted
HIGH.
ADSC
Input-Synchronous Address Strobe from Controller, Sampled on the Rising Edge of CLK, Active
LOW. When asserted LOW, addresses presented to the device are captured in the
address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC
are both asserted, only ADSP is recognized.
BWE
Input-Synchronous Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
ZZ
Input-Asynchronous ZZ “sleep” Input, Active HIGH. When asserted HIGH places the device in a
non-time-critical “sleep” condition with data integrity preserved. For normal operation,
this pin must be LOW or left floating. ZZ pin has an internal pull down.
DQs
I/O-Synchronous
Document Number: 001-66677 Rev. *J
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the read cycle. The
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave
as outputs. When HIGH, DQs and DQPX are placed in a tristate condition.The outputs
are automatically tristated during the data portion of a write sequence, during the first
clock when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE.
Page 7 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Pin Definitions (continued)
Name
I/O
Description
DQPX
I/O-Synchronous
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs.
During write sequences, DQPx is controlled by BW[A:H] correspondingly.
MODE
Input-Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to
VDD or left floating selects interleaved burst sequence. This is a strap pin and should
remain static during device operation. Mode Pin has an internal pull up.
VDD
VDDQ
Power Supply
I/O Power Supply
Power Supply for the I/O Circuitry.
Ground
Ground for the Core of the Device.
VSS
VSSQ
TDO
Power Supply Inputs to the Core of the Device.
I/O Ground
Ground for the I/O Circuitry.
JTAG serial output Serial Data-Out to the JTAG Circuit. Delivers data on the negative edge of TCK. If
Synchronous
the JTAG feature is not being utilized, this pin should be left unconnected. This pin is
not available on TQFP packages.
TDI
JTAG serial input
Synchronous
Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG
feature is not being utilized, this pin can be left floating or connected to VDD through a
pull up resistor. This pin is not available on TQFP packages.
TMS
JTAG serial input
Synchronous
Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG
feature is not being utilized, this pin can be disconnected or connected to VDD. This
pin is not available on TQFP packages.
TCK
JTAG-Clock
Clock Input to the JTAG Circuitry. If the JTAG feature is not being utilized, this pin
must be connected to VSS. This pin is not available on TQFP packages.
NC
–
No Connects. Not internally connected to the die. 72M, 144M and 288M are address
expansion pins are not internally connected to the die.
NC/72M, NC/144M,
NC/288M, NC/576M,
NC/1G
–
No Connects. Not internally connected to the die. NC/72M, NC/144M, NC/288M,
NC/576M and NC/1G are address expansion pins are not internally connected to the
die.
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (t CDV) is 6.5 ns (133-MHz device).
The
CY7C1441KV33/CY7C1443KV33/CY7C1441KVE33
support secondary cache in systems utilizing either a linear or
interleaved burst sequence. The interleaved burst order
supports Pentium processors. The burst order is
user-selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is controlled
by the ADV input. A two-bit on-chip wraparound burst counter
captures the first address in a burst sequence and automatically
increments the address for the rest of the burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWx) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to all
four bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tristate control. ADSP is ignored if CE1 is
HIGH.
Document Number: 001-66677 Rev. *J
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, and (2) ADSP or ADSC is asserted LOW (if the access is
initiated by ADSC, the write inputs must be deasserted during
this first cycle). The address presented to the address inputs is
latched into the address register and the burst counter/control
logic and presented to the memory core. If the OE input is
asserted LOW, the requested data is available at the data
outputs a maximum to tCDV after clock rise. ADSP is ignored if
CE1 is HIGH.
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted active,
and (2) ADSP is asserted LOW. The addresses presented are
loaded into the address register and the burst inputs (GW, BWE,
and BWX)are ignored during this first clock cycle. If the write
inputs are asserted active (see Write Cycle Descriptions table for
appropriate states that indicate a write) on the next clock rise, the
appropriate data is latched and written into the device. Byte
writes are allowed. All I/Os are tristated during a byte write.Since
this is a common I/O device, the asynchronous OE input signal
must be deasserted and the I/Os must be tristated prior to the
presentation of data to DQs. As a safety precaution, the data
Page 8 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
lines are tristated once a write cycle is detected, regardless of
the state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BWX)
indicate a write access. ADSC is ignored if ADSP is active LOW.
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the memory
core. The information presented to DQS is written into the
specified address location. Byte writes are allowed. All I/Os are
tristated when a write is detected, even a byte write. Since this
is a common I/O device, the asynchronous OE input signal must
be deasserted and the I/Os must be tristated prior to the
presentation of data to DQs. As a safety precaution, the data
lines are tristated once a write cycle is detected, regardless of
the state of OE.
On-Chip ECC
CY7C1441KVE33 SRAMs include an on-chip ECC algorithm
that detects and corrects all single-bit memory errors, including
Soft Error Upset (SEU) events induced by cosmic rays, alpha
particles etc. The resulting Soft Error Rate (SER) of these
devices is
anticipated to be
VDD – 0.2 V
tZZREC
ZZ recovery time
ZZ < 0.2 V
tZZI
ZZ active to sleep current
tRZZI
ZZ Inactive to exit sleep current
Document Number: 001-66677 Rev. *J
Min
Max
Unit
–
75
mA
–
2tCYC
ns
2tCYC
–
ns
This parameter is sampled
–
2tCYC
ns
This parameter is sampled
0
–
ns
Page 9 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Truth Table
The truth table for CY7C1441KV33/CY7C1443KV33/CY7C1441KVE33 is as follows. [1, 2, 3, 4, 5]
Cycle Description
Address Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE
OE
CLK
DQ
Deselected Cycle, Power down
None
H
X
X
L
X
L
X
X
X
L–H
Tristate
Deselected Cycle, Power down
None
L
L
X
L
L
X
X
X
X
L–H
Tristate
Deselected Cycle, Power down
None
L
X
H
L
L
X
X
X
X
L–H
Tristate
Deselected Cycle, Power down
None
L
L
X
L
H
L
X
X
X
L–H
Tristate
Deselected Cycle, Power down
None
X
X
H
L
H
L
X
X
X
L–H
Tristate
Sleep Mode, Power down
None
X
X
X
H
X
X
X
X
X
X
Tristate
Read Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
L
L–H
Q
Read Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
H
L–H
Tristate
Write Cycle, Begin Burst
External
L
H
L
L
H
L
X
L
X
L–H
D
Read Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
L
L–H
Q
Read Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
H
L–H
Tristate
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
L
L–H
Q
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L–H
Tristate
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L–H
Q
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L–H
Tristate
Write Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L–H
D
Write Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L–H
D
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L–H
Q
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L–H
Tristate
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L–H
Q
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L–H
Tristate
Write Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L–H
D
Write Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L–H
D
Notes
1. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
2. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
4. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tristate. OE is a don't care
for the remainder of the write cycle.
5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when OE is inactive
or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 001-66677 Rev. *J
Page 10 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Partial Truth Table for Read/Write
The partial truth table for read/write for CY7C1441KV33/CY7C1441KVE33 is as follows. [6, 7, 8]
Function (CY7C1441KV33/CY7C1441KVE33)
GW
BWE
BWD
BWC
BWB
BWA
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write Byte A (DQA, DQPA)
H
L
H
H
H
L
Write Byte B (DQB, DQPB)
H
L
H
H
L
H
Write Bytes A, B (DQA, DQB, DQPA, DQPB)
H
L
H
H
L
L
Write Byte C (DQC, DQPC)
H
L
H
L
H
H
Write Bytes C, A (DQC, DQA, DQPC, DQPA)
H
L
H
L
H
L
Write Bytes C, B (DQC, DQB, DQPC, DQPB)
H
L
H
L
L
H
Write Bytes C, B, A (DQC, DQB, DQA, DQPC, DQPB,
DQPA)
H
L
H
L
L
L
Write Byte D (DQD, DQPD)
H
L
L
H
H
H
Write Bytes D, A (DQD, DQA, DQPD, DQPA)
H
L
L
H
H
L
Write Bytes D, B (DQD, DQA, DQPD, DQPA)
H
L
L
H
L
H
Write Bytes D, B, A (DQD, DQB, DQA, DQPD, DQPB,
DQPA)
H
L
L
H
L
L
Write Bytes D, B (DQD, DQB, DQPD, DQPB)
H
L
L
L
H
H
Write Bytes D, B, A (DQD, DQC, DQA, DQPD, DQPC,
DQPA)
H
L
L
L
H
L
Write Bytes D, C, A (DQD, DQB, DQA, DQPD, DQPB,
DQPA)
H
L
L
L
L
H
Write All Bytes
H
L
L
L
L
L
Write All Bytes
L
X
X
X
X
X
Partial Truth Table for Read/Write
The partial truth table for read/write for CY7C1443KV33 is as follows. [6, 7, 8]
Function (CY7C1443KV33)
GW
BWE
BWB
BWA
Read
H
H
X
X
Read
H
L
H
H
Write Byte A – (DQA and DQPA)
H
L
H
L
Write Byte B – (DQB and DQPB)
H
L
L
H
Write All Bytes
H
L
L
L
Write All Bytes
L
X
X
X
Notes
6. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
7. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write is done based on which byte write is active.
8. BWx represents any byte write signal BW[A..H].To enable any byte write BWx, a Logic LOW signal should be applied at clock rise.Any number of bye writes can be
enabled at the same time for any given write.
Document Number: 001-66677 Rev. *J
Page 11 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
IEEE 1149.1 Serial Boundary Scan (JTAG)
TAP Registers
The CY7C1441KV33 incorporates a serial boundary scan test
access port (TAP). This part is fully compliant with 1149.1. The
TAP operates using JEDEC-standard 3.3 V or 2.5 V I/O logic
levels.
Registers are connected between the TDI and TDO balls and
scan data into and out of the SRAM test circuitry. Only one
register can be selected at a time through the instruction register.
Data is serially loaded into the TDI ball on the rising edge of TCK.
Data is output on the TDO ball on the falling edge of TCK.
The CY7C1441KV33 contains a TAP controller, instruction
register, boundary scan register, bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull up resistor. TDO
should be left unconnected. Upon power up, the device comes
up in a reset state which does not interfere with the operation of
the device.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 14. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board-level serial test data path.
Test Access Port (TAP)
Bypass Register
Test Clock (TCK)
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This shifts data through the SRAM with
minimal delay. The bypass register is set LOW (VSS) when the
BYPASS instruction is executed.
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. TDI is internally pulled
up and can be unconnected if the TAP is unused in an
application. TDI is connected to the most significant bit (MSB) of
any register (see TAP Controller Block Diagram on page 14).
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine. The output changes on the falling edge
of TCK. TDO is connected to the least significant bit (LSB) of any
register (see TAP Controller State Diagram on page 14).
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the I/O ring.
The Boundary Scan Order on page 18 show the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions on
page 17.
At power up, the TAP is reset internally to ensure that TDO
comes up in a High Z state.
Document Number: 001-66677 Rev. *J
Page 12 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the Instruction
Codes table. Three of these instructions are listed as
RESERVED and should not be used. The other five instructions
are described in this section in detail.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction once it is shifted in, the TAP controller must be
moved into the Update-IR state.
IDCODE
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO balls and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a High Z state until the next command is given during the
“Update IR” state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
Document Number: 001-66677 Rev. *J
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the clock captured in the boundary scan register.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells prior to the selection
of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required – that is, while data captured
is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the shift-DR controller state.
EXTEST OUTPUT BUS TRISTATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tristate mode.
The boundary scan register has a special bit located at bit #89
(for 165-FBGA package). When this scan cell, called the “extest
output bus tristate”, is latched into the preload register during the
“Update-DR” state in the TAP controller, it directly controls the
state of the output (Q-bus) pins, when the EXTEST is entered as
the current instruction. When HIGH, it enables the output buffers
to drive the output bus. When LOW, this bit places the output bus
into a High-Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell latches into the preload
register. When the EXTEST instruction is entered, this bit directly
controls the output Q-bus pins. Note that this bit is pre-set HIGH
to enable the output when the device is powered-up, and also
when the TAP controller is in the “Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Page 13 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
TAP Controller State Diagram
1
TEST-LOGIC
RESET
0
RUN-TEST/
IDLE
TAP Controller Block Diagram
0
1
SELECT
DR-SCAN
1
0
1
0
1
SELECT
IR-SCAN
Bypass Register
0
1
CAPTURE-DR
2 1 0
Selection
Circuitry
CAPTURE-IR
TDI
0
Instruction Register
0
SHIFT-DR
0
31 30 29 .
SHIFT-IR
1
EXIT1-DR
Identification Register
1
Boundary Scan Register
x .
EXIT1-IR
0
0
PAUSE-IR
.
.
TDO
. 2 1 0
TCK
0
TMS
1
TAP CONTROLLER
1
0
EXIT2-DR
EXIT2-IR
1
1
UPDATE-DR
UPDATE-IR
1
.
Selection
Circuitry
0
PAUSE-DR
0
. 2 1 0
0
1
1
.
1
0
0
TAP Timing
1
2
Test Clock
(TCK)
3
t
t TH
t TMSS
t TMSH
t TDIS
t TDIH
TL
4
5
6
t CYC
Test Mode Select
(TMS)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CARE
Document Number: 001-66677 Rev. *J
UNDEFINED
Page 14 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
TAP AC Switching Characteristics
Over the Operating Range
Parameter [9, 10]
Description
Min
Max
Unit
Clock
tTCYC
TCK Clock Cycle Time
50
–
ns
tTF
TCK Clock Frequency
–
20
MHz
tTH
TCK Clock HIGH time
20
–
ns
tTL
TCK Clock LOW time
20
–
ns
tTDOV
TCK Clock LOW to TDO Valid
–
10
ns
tTDOX
TCK Clock LOW to TDO Invalid
0
–
ns
tTMSS
TMS Setup to TCK Clock Rise
5
–
ns
tTDIS
TDI Setup to TCK Clock Rise
5
–
ns
tCS
Capture Setup to TCK Rise
5
–
ns
tTMSH
TMS Hold after TCK Clock Rise
5
–
ns
tTDIH
TDI Hold after Clock Rise
5
–
ns
tCH
Capture Hold after Clock Rise
5
–
ns
Output Times
Setup Times
Hold Times
3.3 V TAP AC Test Conditions
2.5 V TAP AC Test Conditions
Input pulse levels ...............................................VSS to 3.3 V
Input pulse levels .............................................. .VSS to 2.5 V
Input rise and fall times (Slew Rate) ........................... 2 V/ns
Input rise and fall times (Slew Rate) ........................... 2 V/ns
Input timing reference levels ......................................... 1.5 V
Input timing reference levels ................. ......................1.25 V
Output reference levels ................................................ 1.5 V
Output reference levels ................ ..............................1.25 V
Test load termination supply voltage ............................ 1.5 V
Test load termination supply voltage .................. ........1.25 V
3.3 V TAP AC Output Load Equivalent
2.5 V TAP AC Output Load Equivalent
1.5V
1.25V
50Ω
TDO
50Ω
TDO
Z O = 50 Ω
20p F
Z O= 50Ω
20pF
Notes
9. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
10. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 2 V/ns (Slew Rate).
Document Number: 001-66677 Rev. *J
Page 15 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 3.135 V to 3.6 V unless otherwise noted)
Parameter [11]
VOH1
Description
Output HIGH Voltage
Min
Max
Unit
IOH = –4.0 mA
Description
VDDQ = 3.3 V
Conditions
2.4
–
V
IOH = –1.0 mA
VDDQ = 2.5 V
2.0
–
V
–
V
VOH2
Output HIGH Voltage
IOH = –100 µA
VDDQ = 3.3 V
2.9
VDDQ = 2.5 V
2.1
–
V
VOL1
Output LOW Voltage
IOL = 8.0 mA
VDDQ = 3.3 V
–
0.4
V
IOL = 1.0 mA
VDDQ = 2.5 V
–
0.4
V
IOL = 100 µA
VDDQ = 3.3 V
–
0.2
V
VOL2
Output LOW Voltage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IX
Input Load Current
GND < VIN < VDDQ
VDDQ = 2.5 V
–
0.2
V
VDDQ = 3.3 V
2.0
VDD + 0.3
V
VDDQ = 2.5 V
1.7
VDD + 0.3
V
VDDQ = 3.3 V
–0.3
0.8
V
VDDQ = 2.5 V
–0.3
0.7
V
–5
5
µA
Note
11. All voltages referenced to VSS (GND).
Document Number: 001-66677 Rev. *J
Page 16 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Identification Register Definitions
CY7C1441KV33
(1M × 36)
Instruction Field
Revision Number (31:29)
000
Device Depth (28:24)
Architecture/Memory
01011
Type(23:18)[12]
Bus Width/Density(17:12)
Cypress JEDEC ID Code (11:1)
Describes the version number.
Reserved for Internal Use
000001
Defines memory type and architecture
100111
Defines width and density
00000110100
ID Register Presence Indicator (0)
Description
1
Allows unique identification of SRAM vendor.
Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size (× 36)
Instruction Bypass
3
Bypass
1
ID
32
Boundary Scan Order (165-ball FBGA package)
89
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM output drivers to a High Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does
not affect SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
BYPASS
Note
12. Bit #24 is “1” in the ID Register Definitions for both 2.5 V and 3.3 V versions of this device.
Document Number: 001-66677 Rev. *J
Page 17 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Boundary Scan Order
165-ball FBGA [13, 14]
CY7C1441KV33 (1M × 36)
Bit #
Ball ID
Bit #
Ball ID
Bit #
Ball ID
Bit #
Ball ID
1
N6
26
E11
51
A3
76
N1
2
N7
N10
27
D11
52
A2
77
N2
3
28
G10
53
B2
78
P1
4
P11
29
F10
54
C2
79
R1
5
P8
30
E10
55
B1
80
R2
6
R8
31
D10
56
A1
81
P3
7
R9
32
C11
57
C1
82
R3
8
P9
33
A11
58
D1
83
P2
9
P10
34
B11
59
E1
84
R4
10
R10
35
A10
60
F1
85
P4
11
R11
36
B10
61
G1
86
N5
12
H11
37
A9
62
D2
87
P6
13
N11
38
B9
63
E2
88
R6
14
M11
39
C10
64
F2
89
Internal
15
L11
40
A8
65
G2
16
K11
41
B8
66
H1
17
J11
42
A7
67
H3
18
M10
43
B7
68
J1
19
L10
44
B6
69
K1
20
K10
45
A6
70
L1
21
J10
46
B5
71
M1
22
H9
47
J2
H10
48
A5
A4
72
23
73
K2
24
G11
49
B4
74
L2
25
F11
50
B3
75
M2
Notes
13. Balls which are NC (No Connect) are preset LOW.
14. Bit# 89 is preset HIGH.
Document Number: 001-66677 Rev. *J
Page 18 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Maximum Ratings
Operating Range
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Range
Ambient
Temperature
Storage Temperature ............................... –65 C to +150C
Commercial
0 °C to +70 °C
Ambient Temperature
with Power Applied .................................. –55C to +125 C
Industrial
Supply Voltage on VDD Relative to GND .....–0.3 V to +4.6 V
Supply Voltage on VDDQ Relative to GND .... –0.3 V to +VDD
DC Voltage Applied to Outputs
in Tristate ..........................................–0.5 V to VDDQ + 0.5 V
DC Input Voltage ................................ –0.5 V to VDD + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ......................... > 2001 V
Latch-up Current ................................................... > 200 mA
DC Input Voltage ................................ –0.5 V to VDD + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ......................... > 2001 V
Latch-up Current ................................................... > 200 mA
–40 °C to +85 °C
VDD
VDDQ
3.3 V– 5% / 2.5 V – 5% to
+ 10%
VDD
Neutron Soft Error Immunity
Parameter
LSBU
(Device
without
ECC)
Test
Description Conditions
Typ
Logical
Single-Bit
Upsets
25 °C
LSBU
(Device with
ECC)
LMBU (All
Devices)
SEL (All
Devices)
Max*
Unit
–2V (Pulse width less than tCYC/2).
16. TPower-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document Number: 001-66677 Rev. *J
Page 19 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Electrical Characteristics (continued)
Over the Operating Range
DC Characteristics (continued)
Over the Operating Range
Parameter
Min
Max
Units
Input leakage current except ZZ GND VI VDDQ
and MODE
–5
5
A
Input current of MODE
Input = VSS
–30
–
A
Input = VDD
–
5
A
Input current of ZZ
Input = VSS
–5
–
A
Input = VDD
–
30
A
IOZ
Output leakage current
GND VI VDDQ, Output Disabled
–5
5
IDD
VDD operating supply current
VDD = Max., IOUT = 0 mA, 7.5-ns cycle,
f = fMAX = 1/tCYC
133 MHz
× 18
–
150
× 36
–
170
Automatic CE power down
current – TTL inputs
Max. VDD, Device
Deselected,
VIN VIH or VIN VIL,
f = fMAX,
inputs switching
7.5-ns cycle,
133 MHz
× 18
–
85
× 36
–
90
Automatic CE power down
current – CMOS inputs
Max. VDD,
Device Deselected,
VIN VDD – 0.3 V or
VIN 0.3 V,
f = 0, inputs static
7.5-ns cycle,
133 MHz
× 18
–
75
× 36
–
80
Automatic CE power down
current – CMOS inputs
Max. VDD,
7.5-ns cycle,
Device Deselected,
133 MHz
VIN VDDQ – 0.3 V or
VIN 0.3 V,
f = fMAX, inputs switching
× 18
–
85
× 36
–
90
Automatic CE power down
current – TTL inputs
Max. VDD, Device
Deselected,
VIN VDD – 0.3 V or
VIN 0.3 V,
f = 0, inputs static
× 18
–
75
× 36
–
80
IX
ISB1
ISB2
ISB3
ISB4
Description
Document Number: 001-66677 Rev. *J
Test Conditions
7.5-ns cycle,
133 MHz
mA
mA
mA
mA
mA
Page 20 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Capacitance
Parameter [17]
Description
CIN
Input capacitance
CCLK
Clock input capacitance
CIO
Input/output capacitance
100-pin TQFP 165-ball FBGA Unit
Max.
Max.
Test Conditions
TA = 25C, f = 1 MHz,
VDD = 3.3V, VDDQ = 2.5 V
5
5
pF
5
5
pF
5
5
pF
Thermal Resistance
Parameter [17]
JA
Description
Thermal resistance Test conditions follow
(junction to ambient) standard test methods and
procedures for measuring
thermal impedance, per
EIA/JESD51.
Thermal resistance
(junction to case)
JC
JB
100-pin TQFP 165-ball FBGA
Package
Package
Test Conditions
Unit
With Still Air (0 m/s)
35.36
14.24
°C/W
With Air Flow (1 m/s)
31.30
12.47
°C/W
With Air Flow (3 m/s)
28.86
11.40
°C/W
–
7.52
3.92
°C/W
28.89
7.19
°C/W
Thermal resistance
(junction to board)
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317
3.3V
OUTPUT
OUTPUT
RL = 50
Z0 = 50
GND
5 pF
R = 351
INCLUDING
JIG AND
SCOPE
10%
90%
10%
90%
1 ns
2 V/ns
VT = 1.5V
(a)
ALL INPUT PULSES
VDDQ
(c)
(b)
2.5V I/O Test Load
R = 1667
2.5V
OUTPUT
OUTPUT
RL = 50
Z0 = 50
GND
5 pF
R = 1538
VT = 1.25V
(a)
ALL INPUT PULSES
VDDQ
INCLUDING
JIG AND
SCOPE
(b)
10%
90%
10%
90%
1 ns
2 V/ns
(c)
Note
17. Tested initially and after any design or process change that may affect these parameters.
Document Number: 001-66677 Rev. *J
Page 21 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Switching Characteristics
Over the Operating Range
Parameter [18, 19]
tPOWER
Description
VDD (Typical) to the first Access[20]
–133
Unit
Min
Max
1
–
ms
Clock
tCYC
Clock cycle time
7.5
–
ns
tCH
Clock HIGH
2.5
–
ns
tCL
Clock LOW
2.5
–
ns
Output Times
tCDV
Data Output Valid after CLK Rise
–
6.5
ns
tDOH
Data Output Hold after CLK Rise
2.5
–
ns
Z[21, 22, 23]
tCLZ
Clock to Low
2.5
–
ns
tCHZ
Clock to High Z[21, 22, 23]
–
3.8
ns
tOEV
OE LOW to Output Valid
–
3.0
ns
0
–
ns
–
3.0
ns
tOELZ
tOEHZ
OE LOW to Output Low
Z[21, 22, 23]
OE HIGH to Output High
Z[21, 22, 23]
Setup Times
tAS
Address setup before CLK Rise
1.5
–
ns
tADS
ADSP, ADSC setup before CLK Rise
1.5
–
ns
tADVS
ADV setup before CLK Rise
1.5
–
ns
tWES
GW, BWE, BWX setup before CLK Rise
1.5
–
ns
tDS
Data input setup before CLK Rise
1.5
–
ns
tCES
Chip Enable setup
1.5
–
ns
tAH
Address Hold after CLK Rise
0.5
–
ns
tADH
ADSP, ADSC Hold after CLK Rise
0.5
–
ns
tWEH
GW, BWE, BWX Hold after CLK Rise
0.5
–
ns
tADVH
ADV Hold after CLK Rise
0.5
–
ns
tDH
Data Input Hold after CLK Rise
0.5
–
ns
tCEH
Chip Enable Hold after CLK Rise
0.5
–
ns
Hold Times
Notes
18. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
19. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
20. This part has a voltage regulator internally; tPOWER is the time that the power must be supplied above VDD(minimum) initially, before a read or write operation can be
initiated.
21. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 3 on page 21. Transition is measured ± 200 mV from steady-state voltage.
22. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High Z prior to Low Z under the same system conditions.
23. This parameter is sampled and not 100% tested.
Document Number: 001-66677 Rev. *J
Page 22 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Timing Diagrams
Figure 4. Read Cycle Timing [24]
tCYC
CLK
t
t ADS
CH
t CL
tADH
ADSP
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
t
GW, BWE,BW
WES
t
WEH
X
t CES
Deselect Cycle
t CEH
CE
t
ADVS
t
ADVH
ADV
ADV suspends burst
OE
t OEV
t OEHZ
t CLZ
Data Out (Q)
High-Z
Q(A1)
t CDV
t OELZ
t CHZ
t DOH
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
t CDV
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
.
Note
24. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document Number: 001-66677 Rev. *J
Page 23 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Timing Diagrams (continued)
Figure 5. Write Cycle Timing [25, 26]
t CYC
CLK
t
t ADS
CH
t
CL
tADH
ADSP
t ADS
ADSC extends burst
tADH
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
A3
Byte write signals are ignored for first cycle when
ADSP initiates burst
t WES tWEH
BWE,
BW
X
t
WES
t
WEH
GW
t CES
tCEH
CE
t ADVS tADVH
ADV
ADV suspends burst
OE
t
Data in (D)
High-Z
t
DS
t
DH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
OEHZ
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
.
Notes
25. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
26. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.
Document Number: 001-66677 Rev. *J
Page 24 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Timing Diagrams (continued)
Figure 6. Read/Write Cycle Timing [27, 28, 29]
tCYC
CLK
t
t ADS
CH
t
CL
tADH
ADSP
ADSC
t AS
ADDRESS
A1
tAH
A2
A3
A4
t
WES
t
A5
A6
WEH
BWE, BW X
t CES
tCEH
CE
ADV
OE
t DS
Data In (D)
Data Out (Q)
High-Z
t
OEHZ
Q(A1)
tDH
t OELZ
D(A3)
D(A5)
Q(A2)
Back-to-Back READs
D(A6)
t CDV
Q(A4)
Single WRITE
Q(A4+1)
BURST READ
DON’T CARE
Q(A4+2)
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
.
Notes
27. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
28. The data bus (Q) remains in high Z following a Write cycle, unless a new read access is initiated by ADSP or ADSC.
29. GW is HIGH.
Document Number: 001-66677 Rev. *J
Page 25 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Timing Diagrams (continued)
Figure 7. ZZ Mode Timing [30, 31]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
30. Device must be deselected when entering ZZ mode. See the Cycle Descriptions table for all possible signal conditions to deselect the device.
31. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 001-66677 Rev. *J
Page 26 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Ordering Information
Table 1 lists the ordering codes. The table contains only the parts that are currently available. If you do not see what you are looking
for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the
product summary page at http://www.cypress.com/products.
Table 1. Ordering Information
Speed (MHz)
Ordering Code
CY7C1441KV33-133AXC
133
Package Diagram
Part and Package Type
Operating Range
51-85050
100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
CY7C1441KVE33-133AXC
CY7C1441KV33-133AXI
Industrial
CY7C1441KVE33-133AXI
CY7C1443KV33-133AXI
CY7C1441KV33-133BZXI
51-85195
165-ball FBGA (15 × 17 × 1.4 mm) Pb-free
Ordering Code Definitions
CY
7
C
14XX KV E 33 - XXX XX
X X
Temperature range: X = C or I
C = Commercial = 0 °C to +70 °C; I = Industrial = –40 °C to +85 °C
X = Pb-free; X Absent = Leaded
Package Type: XX = A or BZ
A = 100-pin TQFP
BZ = 165-ball FBGA
Speed Grade: XXX = 133 MHz
33 = 3.3 V VDD
E = Device with ECC; E Absent = Device without ECC
Process Technology: KV 65 nm
Part Identifier: 14XX = 1441 or 1443
1441 = FT, 1M × 36 (36-Mbit)
1443 = FT, 2M × 18 (36-Mbit)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-66677 Rev. *J
Page 27 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Package Diagrams
Figure 8. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
ș2
ș1
ș
SYMBOL
DIMENSIONS
MIN. NOM. MAX.
A
A1
1.60
0.05
0.15
NOTE:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. BODY LENGTH DIMENSION DOES NOT
INCLUDE MOLD PROTRUSION/END FLASH.
A2
1.35 1.40 1.45
D
15.80 16.00 16.20
MOLD PROTRUSION/END FLASH SHALL
D1
13.90 14.00 14.10
E
21.80 22.00 22.20
NOT EXCEED 0.0098 in (0.25 mm) PER SIDE.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC
E1
19.90 20.00 20.10
R1
0.08
0.20
R2
0.08
0.20
ș
0°
7°
ș1
0°
ș2
11°
13°
12°
0.20
c
b
0.22 0.30 0.38
L
0.45 0.60 0.75
L1
L2
L3
e
BODY SIZE INCLUDING MOLD MISMATCH.
3. JEDEC SPECIFICATION NO. REF: MS-026.
1.00 REF
0.25 BSC
0.20
0.65 TYP
51-85050 *G
Document Number: 001-66677 Rev. *J
Page 28 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Package Diagrams (continued)
Figure 9. 165-ball FBGA (15 × 17 × 1.4 mm (0.5 Ball Diameter)) Package Outline, 51-85195
51-85195 *D
Document Number: 001-66677 Rev. *J
Page 29 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Acronyms
Document Conventions
Table 2. Acronyms Used in this Document
Units of Measure
Acronym
Description
Table 3. Units of Measure
CE
Chip Enable
CMOS
Complementary Metal Oxide Semiconductor
°C
degree Celsius
FBGA
Fine-Pitch Ball Grid Array
MHz
megahertz
I/O
Input/Output
µA
microampere
JTAG
Joint Test Action Group
mA
milliampere
NoBL
No Bus Latency
ms
millisecond
OE
Output Enable
mm
millimeter
SRAM
Static Random Access Memory
ns
nanosecond
TCK
Test Clock
TDI
Test Data-In
TDO
Test Data-Out
TMS
Test Mode Select
TQFP
Thin Quad Flat Pack
WE
Write Enable
ECC
Error Correcting Code
Document Number: 001-66677 Rev. *J
Symbol
Unit of Measure
pF
picofarad
V
volt
W
watt
Page 30 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Document History Page
Document Title: CY7C1441KV33/CY7C1443KV33/CY7C1441KVE33, 36-Mbit (1M × 36/2M × 18) Flow-Through SRAM (With
ECC)
Document Number: 001-66677
Revision
ECN
Submission
Date
*E
4680535
04/10/2015
Changed status from Preliminary to Final.
*F
4757974
05/07/2015
Added Logic Block Diagram – CY7C1441KVE33.
Updated Functional Overview:
Updated ZZ Mode Electrical Characteristics:
Changed maximum value of IDDZZ parameter from 89 mA to 75 mA.
*G
4965199
10/15/2015
Updated Selection Guide:
Updated value of “Maximum Operating Current”.
*H
5338013
07/05/2016
Updated Truth Table:
Updated details in “CE3” column corresponding to fifth row of “Deselected Cycle, Power
Down”.
Updated Neutron Soft Error Immunity:
Updated values in “Typ” and “Max” columns corresponding to LSBU (Device without ECC)
parameter.
Updated to new template.
*I
6072311
02/15/2018
Updated Package Diagrams:
spec 51-85050 – Changed revision from *E to *G.
Updated to new template.
*J
6745577
12/05/2019
Updated Ordering Information:
Updated part numbers.
Updated to new template.
Document Number: 001-66677 Rev. *J
Description of Change
Page 31 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
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cypress.com/arm
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cypress.com/clocks
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cypress.com/iot
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cypress.com/mcu
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cypress.com/psoc
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Community | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
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cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2011–2019. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or
firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress
reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property
rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants
you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce
the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or
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TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
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responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk Device”
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medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk
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Cypress’s published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to
use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-66677 Rev. *J
Revised December 5, 2019
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation.
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