CY7C1460SV33
36-Mbit (1M × 36) Pipelined SRAM with
NoBL™ Architecture
36-Mbit (1M × 36) Pipelined SRAM with NoBL™ Architecture
Features
Functional Description
■
Pin compatible and functionally equivalent to ZBT™
■
Supports 200 MHz bus operations with zero wait states
❐ Available speed grade is 200 MHz
■
Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
■
Fully registered (inputs and outputs) for pipelined operation
■
Byte write capability
■
3.3 V power supply
■
3.3 V/2.5 V I/O power supply
■
Fast clock-to-output times
❐ 3.2 ns (for 200 MHz device)
■
Clock Enable (CEN) pin to suspend operation
■
Synchronous self-timed writes
■
CY7C1460SV33 available in JEDEC-standard Pb-Free
100-pin TQFP
■
Burst capability – linear or interleaved burst order
■
“ZZ” Sleep Mode option and Stop Clock option
The CY7C1460SV33 is a 3.3 V, 1M × 36 synchronous pipelined
burst SRAM with No Bus Latency™ (NoBL logic, respectively.
They are designed to support unlimited true back to back
Read/Write operations with no wait states. The CY7C1460SV33
are equipped with the advanced (NoBL) logic required to enable
consecutive Read/Write operations with data being transferred
on every clock cycle. This feature dramatically improves the
throughput of data in systems that require frequent Write/Read
transitions. CY7C1460SV33 is pin compatible and functionally
equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the Clock Enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
Write operations are controlled by the Byte Write Selects
(BWa–BWd for CY7C1460SV33) and a Write Enable (WE) input.
All writes are conducted with on-chip synchronous self-timed
write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tristate control. To avoid bus contention, the
output drivers are synchronously tristated during the data portion
of a write sequence.
Logic Block Diagram – CY7C1460SV33
ADDRESS
REGISTER 0
A0, A1, A
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
ADV/LD
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BWa
BWb
BWc
BWd
MEMORY
ARRAY
WRITE
DRIVERS
WE
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
INPUT
REGISTER 1 E
OE
CE1
CE2
CE3
S
T
E
E
R
I
N
G
INPUT
REGISTER 0
B
U
F
F
E
R
S
DQs
DQPa
DQPb
DQPc
DQPd
E
E
READ LOGIC
SLEEP
CONTROL
ZZ
Cypress Semiconductor Corporation
Document Number: 001-43803 Rev. *F
O
U
T
P
U
T
D
A
T
A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 18, 2016
CY7C1460SV33
Contents
Selection Guide ................................................................ 3
Pin Configurations ........................................................... 3
Pin Definitions .................................................................. 4
Functional Overview ........................................................ 5
Single Read Accesses ................................................ 5
Burst Read Accesses .................................................. 5
Single Write Accesses ................................................. 5
Burst Write Accesses .................................................. 6
Sleep Mode ................................................................. 6
Interleaved Burst Address Table ................................. 6
Linear Burst Address Table ......................................... 6
ZZ Mode Electrical Characteristics .............................. 6
Truth Table ........................................................................ 7
Partial Write Cycle Description ....................................... 8
Maximum Ratings ............................................................. 9
Operating Range ............................................................... 9
Electrical Characteristics ................................................. 9
Capacitance .................................................................... 10
Document Number: 001-43803 Rev. *F
Thermal Resistance ........................................................ 10
AC Test Loads and Waveforms ..................................... 10
Switching Characteristics .............................................. 11
Switching Waveforms .................................................... 12
Ordering Information ...................................................... 14
Ordering Code Definitions ......................................... 14
Package Diagrams .......................................................... 15
Acronyms ........................................................................ 16
Document Conventions ................................................. 16
Units of Measure ....................................................... 16
Document History Page ................................................. 17
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC® Solutions ...................................................... 19
Cypress Developer Community ................................. 19
Technical Support ..................................................... 19
Page 2 of 19
CY7C1460SV33
Selection Guide
Description
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
200 MHz
Unit
3.2
425
120
ns
mA
mA
Pin Configurations
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
BWd
BWc
BWb
BWa
CE3
VDD
VSS
CLK
WE
CEN
OE
ADV/LD
A
A
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
DQPc
DQc
DQc
VDDQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
CY7C1460SV33
(1M × 36)
DQPb
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
DQPa
Document Number: 001-43803 Rev. *F
A
A
A
A
A
A
A
A
NC/72M
VSS
VDD
NC/144M
NC/288M
MODE
A
A
A
A
A1
A0
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Page 3 of 19
CY7C1460SV33
Pin Definitions
Pin Name
I/O Type
Pin Description
A0, A1, A
InputAddress Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the
Synchronous CLK.
BWa, BWb,
BWc, BWd
InputByte Write Select Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled
Synchronous on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc controls
DQc and DQPc, BWd controls DQd and DQPd.
WE
InputWrite Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
Synchronous signal must be asserted LOW to initiate a write sequence.
ADV/LD
InputAdvance/Load Input Used to Advance the On Chip Address Counter or Load a New Address.
Synchronous When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new
address can be loaded into the device for an access. After being deselected, ADV/LD should be
driven LOW to load a new address.
CLK
InputClock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK
is only recognized if CEN is active LOW.
CE1
InputChip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE2 and CE3 to select/deselect the device.
CE2
InputChip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE1 and CE3 to select/deselect the device.
CE3
InputChip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE2 to select/deselect the device.
OE
InputOutput Enable, Active LOW. Combined with the synchronous logic block inside the device to control
Asynchronou the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When
s
deasserted HIGH, I/O pins are tristated, and act as input data pins. OE is masked during the data
portion of a write sequence, during the first clock when emerging from a deselected state and when
the device has been deselected.
CEN
InputClock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by the SRAM.
Synchronous When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the
device, CEN can be used to extend the previous cycle when required.
DQa, DQb,
DQc, DQd
I/OBidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by
Synchronous the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by AX during the previous clock rise of the read cycle. The direction of the pins is controlled by OE
and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When
HIGH, DQa–DQd are placed in a tristate condition. The outputs are automatically tristated during the
data portion of a write sequence, during the first clock when emerging from a deselected state, and
when the device is deselected, regardless of the state of OE.
I/OBidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQ[31:0]. During write
DQPa, DQPb,
DQPc, DQPd Synchronous sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc, and
DQPd is controlled by BWd.
MODE
VDD
VDDQ
VSS
NC
NC/72M
NC/144M
Input Strap
Pin
Power
Supply
I/O Power
Supply
Ground
N/A
N/A
N/A
Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
Pulled LOW selects the linear burst order. MODE should not change states during operation. When
left floating MODE defaults HIGH, to an interleaved burst order.
Power Supply Inputs to the Core of the Device.
Power Supply for the I/O Circuitry.
Ground for the Device. Should be connected to ground of the system.
No Connects. This pin is not connected to the die.
Not Connected to the Die. Can be tied to any voltage level.
Not Connected to the Die. Can be tied to any voltage level.
Document Number: 001-43803 Rev. *F
Page 4 of 19
CY7C1460SV33
Pin Definitions (continued)
Pin Name
I/O Type
Pin Description
NC/288M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/576M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/1G
N/A
Not Connected to the Die. Can be tied to any voltage level.
ZZ
InputZZ “sleep” Input. This active HIGH input places the device in a non time critical “sleep” condition
Asynchronou with data integrity preserved. During normal operation, this pin can be connected to VSS or left floating.
ZZ pin has an internal pull down.
s
Functional Overview
The CY7C1460SV33 are synchronous pipelined Burst NoBL
SRAMs designed specifically to eliminate wait states during
Write/Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal (CEN).
If CEN is HIGH, the clock signal is not recognized and all internal
states are maintained. All synchronous operations are qualified
with CEN. All data outputs pass through output registers
controlled by the rising edge of the clock. Maximum access delay
from the clock rise (tCO) is 3.2 ns (200 MHz device).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device is latched. The access can
either be a read or write operation, depending on the status of
the Write Enable (WE). BW[x] can be used to conduct byte write
operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion. All
operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW after the device has been
deselected to load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory core and
control logic. The control logic determines that a read access is
in progress and allows the requested data to propagate to the
input of the output register. At the rising edge of the next clock
the requested data is allowed to propagate through the output
register and onto the data bus within 3.2 ns (200 MHz device)
provided OE is active LOW. After the first clock of the read
access the output buffers are controlled by OE and the internal
control logic. OE must be driven LOW in order for the device to
drive out the requested data. During the second clock, a
subsequent operation (Read/Write/Deselect) can be initiated.
Deselecting the device is also pipelined. Therefore, when the
SRAM is deselected at clock rise by one of the chip enable
signals, its output tristates following the next clock rise.
Document Number: 001-43803 Rev. *F
Burst Read Accesses
The CY7C1460SV33 have an on-chip burst counter that allows
the user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD must
be driven LOW to load a new address into the SRAM, as
described in the Single Read Access section. The sequence of
the burst counter is determined by the MODE input signal. A
LOW input on MODE selects a linear burst mode, a HIGH selects
an interleaved burst sequence. Both burst counters use A0 and
A1 in the burst sequence, and wraps around when incremented
sufficiently. A HIGH input on ADV/LD increments the internal
burst counter regardless of the state of chip enables inputs or
WE. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (Read or Write) is maintained throughout the
burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the write signal WE is
asserted LOW. The address presented to the address inputs is
loaded into the Address Register. The write signals are latched
into the Control Logic block.
On the subsequent clock rise the data lines are automatically
tristated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1460SV33). In addition, the
address for the subsequent access (Read/Write/Deselect) is
latched into the Address Register (provided the appropriate
control signals are asserted).
On the next clock rise the data presented to DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1460SV33) (or a subset for byte
write operations; see Write Cycle Description table for details)
inputs is latched into the device and the write is complete.
The data written during the Write operation is controlled by BW
(BWa,b,c,d for CY7C1460SV33) provides byte write capability
that is described in the Write Cycle Description table. Asserting
the Write Enable input (WE) with the selected Byte Write Select
(BW) input selectively writes to only the desired bytes. Bytes not
selected during a byte write operation remains unaltered. A
synchronous self-timed write mechanism has been provided to
simplify the write operations. Byte write capability has been
included to greatly simplify Read/Modify/Write sequences, which
can be reduced to simple byte write operations.
Because the CY7C1460SV33 is a common I/O device, data
should not be driven into the device while the outputs are active.
The Output Enable (OE) can be deasserted HIGH before
presenting data to the DQ and DQP (DQa,b,c,d/DQPa,b,c,d for
Page 5 of 19
CY7C1460SV33
CY7C1460SV33) inputs. Doing so tristates the output drivers. As
a safety precaution, DQ and DQP (DQa,b,c,d/DQPa,b,c,d for
CY7C1460SV33) are automatically tristated during the data
portion of a write cycle, regardless of the state of OE.
Interleaved Burst Address Table
(MODE = Floating or VDD)
Burst Write Accesses
The CY7C1460SV33 has an on-chip burst counter that allows
the user the ability to supply a single address and conduct up to
four WRITE operations without reasserting the address inputs.
ADV/LD must be driven LOW to load the initial address, as
described in the Single Write Access section. When ADV/LD is
driven HIGH on the subsequent clock rise, the chip enables
(CE1, CE2, and CE3) and WE inputs are ignored and the burst
counter is incremented. The correct BW (BWa,b,c,d for
CY7C1460SV33) inputs must be driven in each cycle of the burst
write to write the correct bytes of data.
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Fourth
Address
A1:A0
Linear Burst Address Table
Sleep Mode
(MODE = GND)
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
IDDZZ
Sleep mode standby current
ZZ VDD 0.2 V
–
100
mA
tZZS
Device operation to ZZ
ZZVDD 0.2 V
–
2tCYC
ns
tZZREC
ZZ recovery time
ZZ 0.2 V
2tCYC
–
ns
tZZI
ZZ active to sleep current
This parameter is sampled
–
2tCYC
ns
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
0
–
ns
Document Number: 001-43803 Rev. *F
Page 6 of 19
CY7C1460SV33
Truth Table
The truth table for CY7C1460SV33 follows. [1, 2, 3, 4, 5, 6, 7]
Operation
Address Used CE ZZ ADV/LD WE BWx OE CEN CLK
DQ
Deselect Cycle
None
H
L
L
X
X
X
L
L–H
Tristate
Continue Deselect Cycle
None
X
L
H
X
X
X
L
L–H
Tristate
Read Cycle (Begin Burst)
External
L
L
L
H
X
L
L
L–H Data Out (Q)
Next
X
L
H
X
X
L
L
L–H Data Out (Q)
External
L
L
L
H
X
H
L
L–H
Tristate
Next
X
L
H
X
X
H
L
L–H
Tristate
External
L
L
L
L
L
X
L
L–H
Data In (D)
Write Cycle (Continue Burst)
Next
X
L
H
X
L
X
L
L–H
Data In (D)
NOP/WRITE ABORT (Begin Burst)
None
L
L
L
L
H
X
L
L–H
Tristate
WRITE ABORT (Continue Burst)
Next
X
L
H
X
H
X
L
L–H
Tristate
Current
X
L
X
X
X
X
H
L–H
–
None
X
H
X
X
X
X
X
X
Tristate
Read Cycle (Continue Burst)
NOP/Dummy Read (Begin Burst)
Dummy Read (Continue Burst)
Write Cycle (Begin Burst)
IGNORE CLOCK EDGE (Stall)
SLEEP MODE
Notes
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BWX. See Write Cycle Description table for details.
3. When a write cycle is detected, all I/Os are tristated, even during byte writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device powers up deselected and the I/Os in a tristate condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQs and DQPX = Tristate when OE is
inactive or when the device is deselected, and DQs=data when OE is active.
Document Number: 001-43803 Rev. *F
Page 7 of 19
CY7C1460SV33
Partial Write Cycle Description
Partial Write Cycle Description for CY7C1460SV33 follows. [8, 9, 10, 11]
Function (CY7C1460SV33)
WE
BWd
BWc
BWb
BWa
Read
H
X
X
X
X
Write – No bytes written
L
H
H
H
H
Write Byte a – (DQa and DQPa)
L
H
H
H
L
Write Byte b – (DQb and DQPb)
L
H
H
L
H
Write Bytes b, a
L
H
H
L
L
Write Byte c – (DQc and DQPc)
L
H
L
H
H
Write Bytes c, a
L
H
L
H
L
Write Bytes c, b
L
H
LL
L
H
Write Bytes c, b, a
L
H
L
L
L
Write Byte d – (DQd and DQPd)
L
L
H
H
H
Write Bytes d, a
L
L
H
H
L
Write Bytes d, b
L
L
H
L
H
Write Bytes d, b, a
L
L
H
L
L
Write Bytes d, c
L
L
L
H
H
Write Bytes d, c, a
L
L
L
H
L
Write Bytes d, c, b
L
L
L
L
H
Write All Bytes
L
L
L
L
L
Notes
8. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
9. Write is defined by WE and BWX. See Write Cycle Description table for details.
10. When a write cycle is detected, all I/Os are tristated, even during byte writes.
11. Table only lists a partial listing of the byte write combinations. Any combination of BW[a:d] is valid. Appropriate write is done based on which byte write is active.
Document Number: 001-43803 Rev. *F
Page 8 of 19
CY7C1460SV33
Maximum Ratings
Current into Outputs (LOW) ........................................ 20 mA
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature ............................... –65 °C to +150 °C
Ambient Temperature with
Power Applied ......................................... –55 °C to +125 °C
Static Discharge Voltage
(per MIL-STD-883, Method 3015) .......................... > 2001 V
Latch up current ..................................................... > 200 mA
Operating Range
Supply Voltage on VDD Relative to GND .....–0.5 V to +4.6 V
Supply Voltage on VDDQ Relative to GND .... –0.5 V to +VDD
DC to Outputs in Tristate ..................–0.5 V to VDDQ + 0.5 V
Range
Ambient
Temperature
Commercial 0 °C to +70 °C
VDD
VDDQ
3.3 V – 5% /
+ 10%
2.5 V – 5% to
VDD
DC Input Voltage ................................ –0.5 V to VDD + 0.5 V
Electrical Characteristics
Over the Operating Range
Parameter [12, 13]
Description
Min
Max
Unit
3.135
3.6
V
for 3.3 V I/O
3.135
VDD
V
for 2.5 V I/O
2.375
2.625
V
for 3.3 V I/O, IOH =4.0 mA
2.4
–
V
for 2.5 V I/O, IOH = 1.0 mA
2.0
–
V
for 3.3 V I/O, IOL =8.0 mA
–
0.4
V
for 2.5 V I/O, IOL =1.0 mA
–
0.4
V
for 3.3 V I/O
2.0
VDD + 0.3 V
V
for 2.5 V I/O
1.7
VDD + 0.3 V
V
for 3.3 V I/O
–0.3
0.8
V
for 2.5 V I/O
–0.3
0.7
V
Input Leakage Current except ZZ GND VI VDDQ
and MODE
–5
5
A
Input Current of MODE
–30
–
A
Input = VDD
–
5
A
Input = VSS
–5
–
A
Input = VDD
–
30
A
Output Leakage Current
GND VI VDDQ, Output Disabled
–5
5
A
VDD Operating Supply
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
5-ns cycle,
200 MHz
–
425
mA
ISB1
Automatic CE Power down
Current – TTL Inputs
Max. VDD, Device Deselected,
VIN VIH or VIN VIL,
f = fMAX = 1/tCYC
5-ns cycle,
200 MHz
–
225
mA
ISB2
Automatic CE Power down
Current – CMOS Inputs
Max. VDD, Device Deselected,
5-ns cycle,
VIN 0.3 V or VIN > VDDQ 0.3 V, 200 MHz
f=0
–
120
mA
VDD
Power Supply Voltage
VDDQ
I/O Supply Voltage
VOH
VOL
VIH
Output HIGH Voltage
Output LOW Voltage
[12]
Input HIGH Voltage
VIL
Input LOW Voltage
IX
[12]
Input Current of ZZ
IOZ
IDD
[14]
Test Conditions
Input = VSS
Notes
12. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).
13. TPowe up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
14. The operation current is calculated with 50% read cycle and 50% write cycle.
Document Number: 001-43803 Rev. *F
Page 9 of 19
CY7C1460SV33
Electrical Characteristics (continued)
Over the Operating Range
Parameter [12, 13]
Description
Test Conditions
Min
Max
Unit
ISB3
Automatic CE Power down
Current – CMOS Inputs
Max. VDD, Device Deselected,
5-ns cycle,
VIN 0.3 V or VIN > VDDQ 0.3 V, 200 MHz
f = fMAX = 1/tCYC
–
200
mA
ISB4
Automatic CE Power down
Current – TTL Inputs
Max. VDD, Device Deselected,
VIN VIH or VIN VIL, f = 0
–
135
mA
5-ns cycle,
200 MHz
Capacitance
Parameter [15]
Description
100-pin TQFP Unit
Max
Test Conditions
TA = 25 C, f = 1 MHz,
VDD = 2.5 V VDDQ = 2.5 V
CIN
Input capacitance
CCLK
Clock input capacitance
CIO
Input/Output capacitance
6.5
pF
3
pF
5.5
pF
Test Conditions
100-pin TQFP
Package
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51.
25.21
C/W
2.28
C/W
Thermal Resistance
Parameter [15]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317
3.3 V
OUTPUT
OUTPUT
RL = 50
Z0 = 50
VT = 1.5 V
(a)
2.5 V I/O Test Load
GND
5 pF
INCLUDING
JIG AND
SCOPE
2.5 V
OUTPUT
R = 351
VT = 1.25 V
(a)
5 pF
INCLUDING
JIG AND
SCOPE
10%
90%
10%
90%
1 ns
1 ns
(b)
(c)
R = 1667
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50
Z0 = 50
ALL INPUT PULSES
VDDQ
GND
R =1538
(b)
10%
90%
10%
90%
1 ns
1 ns
(c)
Note
15. Tested initially and after any design or process changes that may affect these parameters
Document Number: 001-43803 Rev. *F
Page 10 of 19
CY7C1460SV33
Switching Characteristics
Over the Operating Range
Parameter [16, 17]
tPower[18]
Description
VCC(typical) to the first access read or write
-200
Unit
Min
Max
1
–
ms
5.0
–
ns
–
200
MHz
Clock
tCYC
Clock Cycle Time
FMAX
Maximum Operating Frequency
tCH
Clock HIGH
2.0
–
ns
tCL
Clock LOW
2.0
–
ns
–
3.2
ns
Output Times
tCO
Data Output Valid After CLK Rise
tEOV
OE LOW to Output Valid
tDOH
Data Output Hold After CLK Rise
tCHZ
tCLZ
tEOHZ
tEOLZ
Clock to High
Z[19, 20, 21]
Clock to Low
Z[19, 20, 21]
OE HIGH to Output High
OE LOW to Output Low
Z[19, 20, 21]
Z[19, 20, 21]
–
3.0
ns
1.5
–
ns
–
3.0
ns
1.3
–
ns
–
3.0
ns
0
–
ns
Set up Times
tAS
Address Set up Before CLK Rise
1.4
–
ns
tDS
Data Input Set up Before CLK Rise
1.4
–
ns
tCENS
CEN Set up Before CLK Rise
1.4
–
ns
tWES
WE, BWx Set up Before CLK Rise
1.4
–
ns
tALS
ADV/LD Set up Before CLK Rise
1.4
–
ns
tCES
Chip Select Set up
1.4
–
ns
tAH
Address Hold After CLK Rise
0.4
–
ns
tDH
Data Input Hold After CLK Rise
0.4
–
ns
tCENH
CEN Hold After CLK Rise
0.4
–
ns
tWEH
WE, BWx Hold After CLK Rise
0.4
–
ns
tALH
ADV/LD Hold after CLK Rise
0.4
–
ns
tCEH
Chip Select Hold After CLK Rise
0.4
–
ns
Hold Times
Notes
16. Timing reference is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
17. Test conditions shown in (a) of Figure 2 on page 10 unless otherwise noted.
18. This part has a voltage regulator internally; tpower is the time power is supplied above VDD(minimum) initially, before a Read or Write operation can be initiated.
19. tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of Figure 2 on page 10. Transition is measured ±200 mV from steady state voltage.
20. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High Z prior to Low Z under the same system conditions.
21. This parameter is sampled and not 100% tested.
Document Number: 001-43803 Rev. *F
Page 11 of 19
CY7C1460SV33
Switching Waveforms
Figure 3. Read/Write/Timing [22, 23, 24]
1
2
3
t CYC
4
5
6
A3
A4
7
8
9
A5
A6
A7
10
CLK
tCENS
tCENH
tCL
tCH
CEN
tCES
tCEH
CE
ADV/LD
WE
BWx
A1
ADDRESS
A2
tCO
tAS
tDS
tAH
Data
In-Out (DQ)
tDH
D(A1)
tCLZ
D(A2)
D(A2+1)
tDOH
Q(A3)
tOEV
Q(A4)
tCHZ
Q(A4+1)
D(A5)
Q(A6)
tOEHZ
tDOH
tOELZ
OE
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
DON’T CARE
BURST
READ
Q(A4+1)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
UNDEFINED
Notes
22. For this waveform ZZ is tied low.
23. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH,CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
24. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved).Burst operations are optional.
Document Number: 001-43803 Rev. *F
Page 12 of 19
CY7C1460SV33
Switching Waveforms (continued)
Figure 4. NOP, STALL and DESELECT Cycles [25, 26, 27]
1
2
A1
A2
3
4
5
A3
A4
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BWx
ADDRESS
A5
tCHZ
D(A1)
Data
Q(A2)
D(A4)
Q(A3)
Q(A5)
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
DON’T CARE
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
UNDEFINED
Figure 5. ZZ Mode Timing [28, 29]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
25. For this waveform ZZ is tied low.
26. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH,CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
27. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.
28. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
29. I/Os are in High Z when exiting ZZ sleep mode.
Document Number: 001-43803 Rev. *F
Page 13 of 19
CY7C1460SV33
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit
www.cypress.com for actual products offered.
Speed
(MHz)
200
Package
Diagram
Ordering Code
CY7C1460SV33-200AXC
Part and Package Type
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Operating
Range
Commercial
Ordering Code Definitions
CY
7
C 1460 S V33 - 200
A
X
C
Temperature Range:
C = Commercial
Pb-free
Package Type:
A = 100-pin TQFP
Frequency Range: 200 MHz
V33 = 3.3 V
Die Revision
Part Identifier: 1460 = PL, 1Mb × 36 (36 Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-43803 Rev. *F
Page 14 of 19
CY7C1460SV33
Package Diagrams
Figure 6. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
51-85050 *E
Document Number: 001-43803 Rev. *F
Page 15 of 19
CY7C1460SV33
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CMOS
Complementary Metal Oxide Semiconductor
I/O
Input/Output
°C
degree Celsius
LSB
Least Significant Bit
MHz
megahertz
MSB
Most Significant Bit
µA
microampere
OE
Output Enable
mA
milliampere
SRAM
Static Random Access Memory
mm
millimeter
TQFP
Thin Quad Flat Pack
ms
millisecond
TTL
Transistor-Transistor Logic
mV
millivolt
WE
Write Enable
Document Number: 001-43803 Rev. *F
Symbol
Unit of Measure
ns
nanosecond
ohm
%
percent
pF
picofarad
V
volt
W
watt
Page 16 of 19
CY7C1460SV33
Document History Page
Document Title: CY7C1460SV33, 36-Mbit (1M × 36) Pipelined SRAM with NoBL™ Architecture
Document Number: 001-43803
Rev.
ECN No.
Issue Date
Orig. of
Change
**
1897686
See ECN
VKN /
AESA
Description of Change
New data sheet.
*A
2082846
See ECN
VKN
Changed status from Preliminary to Final.
*B
2950609
06/11/2010
NJY
Updated Functional Description (Removed CY7C1462SV33, and
CY7C1464SV33 related information).
Removed Logic Block Diagram – CY7C1462SV33.
Removed Logic Block Diagram – CY7C1464SV33.
Updated Pin Configurations (Removed CY7C1462SV33, and CY7C1464SV33
related information).
Updated Functional Overview (Removed CY7C1462SV33, and
CY7C1464SV33 related information).
Updated Truth Table (Removed CY7C1462SV33, and CY7C1464SV33 related
information).
Removed Partial Write Cycle Description (Corresponding to CY7C1462SV33,
and CY7C1464SV33).
Updated IEEE 1149.1 Serial Boundary Scan (JTAG) (Removed
CY7C1462SV33, and CY7C1464SV33 related information).
Updated Identification Register Definitions (Removed CY7C1462SV33, and
CY7C1464SV33 related information).
Updated Boundary Scan Order (Removed CY7C1462SV33, and
CY7C1464SV33 related information).
Updated Ordering Information (Updated part numbers).
Updated Package Diagrams.
Added Sales, Solutions, and Legal Information.
*C
3221156
04/10/2011
NJY
Added Ordering Code Definitions.
Updated Package Diagrams.
Added Acronyms and Units of Measure.
Updated to new template.
*D
3569737
04/02/2012
PRIT
Updated Features (Removed CY7C1462SV33, and CY7C1464SV33 related
information).
Updated Selection Guide (Removed 250 MHz, and 167 MHz frequencies
related information).
Updated Pin Configurations (Removed 165-ball FBGA package related
information).
Updated Pin Definitions (Removed JTAG related information).
Removed IEEE 1149.1 Serial Boundary Scan (JTAG).
Removed TAP Controller State Diagram.
Removed TAP Controller Block Diagram.
Removed TAP Timing.
Removed TAP AC Switching Characteristics.
Removed 3.3 V TAP AC Test Conditions.
Removed 3.3 V TAP AC Output Load Equivalent.
Removed 2.5 V TAP AC Test Conditions.
Removed 2.5 V TAP AC Output Load Equivalent.
Removed TAP DC Electrical Characteristics and Operating Conditions.
Removed Identification Register Definitions.
Removed Scan Register Sizes.
Removed Identification Codes.
Removed Boundary Scan Order (corresponding to 165-ball FBGA and 209-ball
BGA).
Document Number: 001-43803 Rev. *F
Page 17 of 19
CY7C1460SV33
Document History Page (continued)
Document Title: CY7C1460SV33, 36-Mbit (1M × 36) Pipelined SRAM with NoBL™ Architecture
Document Number: 001-43803
Rev.
ECN No.
Issue Date
Orig. of
Change
Description of Change
*D (cont.)
3569737
04/02/2012
PRIT
Updated Operating Range (Removed Industrial Range).
Updated Electrical Characteristics (Removed 250 MHz, and 167 MHz
frequencies related information).
Updated Capacitance (Removed 165-ball FBGA, and 209-ball FBGA package
related information).
Updated Thermal Resistance (Removed 165-ball FBGA, and 209-ball FBGA
package related information).
Updated Switching Characteristics (Removed 250 MHz, and 167 MHz
frequencies related information).
Updated Package Diagrams (Removed 165-ball FBGA, and 209-ball FBGA
package related information).
*E
3957732
04/08/2013
PRIT
No technical updates.
Completing Sunset Review.
*F
5181018
03/18/2016
PRIT
Updated Package Diagrams:
spec 51-85050 – Changed revision from *D to *E.
Updated to new template.
Completing Sunset Review.
Document Number: 001-43803 Rev. *F
Page 18 of 19
CY7C1460SV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/clocks
cypress.com/interface
cypress.com/powerpsoc
cypress.com/memory
PSoC
cypress.com/psoc
Touch Sensing
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/support
cypress.com/touch
USB Controllers
Wireless/RF
cypress.com/psoc
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation 2008-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you under its copyright rights in the Software, a personal, non-exclusive, nontransferable license (without the right to sublicense) (a) for Software provided in source code form, to modify
and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either
directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units. Cypress also grants you a personal, non-exclusive, nontransferable, license (without the right
to sublicense) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely to the minimum
extent that is necessary for you to exercise your rights under the copyright license granted in the previous sentence. Any other use, reproduction, modification, translation, or compilation of the Software
is prohibited.
CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes to this document without further notice. Cypress does not
assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or
programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application
made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of
weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or
hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any
component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole
or in part, and Company shall and hereby does release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. Company shall indemnify
and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress
products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-43803 Rev. *F
Revised March 18, 2016
ZBT is a registered trademark of Integrated Device Technology, Inc. No Bus Latency and NoBL are trademarks of Cypress Semiconductor.
Page 19 of 19