CY7C194BN_11

CY7C194BN 256 Kb (64 K × 4) Static RAM 256 Kb (64 K × 4) Static RAM Features ■ ■ ■ ■ ■ General Description The CY7C194BN is a high-performance CMOS Asynchronous SRAM organized as 64 K × 4 bits that supports an asynchronous memory interface. The device features an automatic power-down feature that significantly reduces power consumption when deselected. See the Truth Table in this data sheet for a complete description of read and write modes. The CY7C194BN is available in 24-pin DIP, 24-pin SOJ package(s). Fast access time: 15 ns Wide voltage range: 5.0 V ± 10% (4.5 V to 5.5 V) Complementary metal oxide semiconductor (CMOS) for optimum speed/power Transistor transistor logic (TTL) compatible inputs and outputs CY7C194BN is available in 24-pin DIP, 24-pin SOJ packages. Logic Block Diagram Input Buffer Row Decoder RAM Array Sense Amps I/Ox CE Column Decoder Power Down Circuit WE OE (7C195 only) X A X Cypress Semiconductor Corporation Document #: 001-06446 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 2, 2011 [+] Feedback CY7C194BN Contents Product Portfolio .............................................................. 3 Pin Layout and Specification .......................................... 4 Pin Description ................................................................. 5 CY7C194BN Truth Table .................................................. 5 Maximum Ratings ............................................................. 5 Operating Range ............................................................... 5 DC Electrical Characteristics .......................................... 6 Capacitance ...................................................................... 6 Thermal Resistance .......................................................... 6 AC Test Loads .................................................................. 7 AC Test Conditions .......................................................... 7 AC Electrical Characteristics .......................................... 8 Timing Waveforms ........................................................... 8 Ordering Information ...................................................... 11 Ordering Code Definitions ......................................... 11 Package Diagrams .......................................................... 12 Acronyms ........................................................................ 13 Document Conventions ................................................. 13 Units of Measure ....................................................... 13 Document History Page ................................................. 14 Sales, Solutions, and Legal Information ...................... 15 Worldwide Sales and Design Support ....................... 15 Products .................................................................... 15 PSoC Solutions ......................................................... 15 Document #: 001-06446 Rev. *D Page 2 of 15 [+] Feedback CY7C194BN Product Portfolio Description Maximum access time Maximum operating current Maximum CMOS standby current -15 15 80 10 Unit ns mA mA Document #: 001-06446 Rev. *D Page 3 of 15 [+] Feedback CY7C194BN Pin Layout and Specification CY7C194BN 24-pin SOJ (8 × 15 × 3.5 mm) A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 CE GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A5 A4 A3 A2 A1 A0 I/O3 I/O2 I/O1 I/O0 WE CY7C194BN 24-pin DIP (6.6 × 31.8 × 3.5 mm) A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 CE GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A5 A4 A3 A2 A1 A0 I/O3 I/O2 I/O1 I/O0 WE Document #: 001-06446 Rev. *D Page 4 of 15 [+] Feedback CY7C194BN Pin Description Pin AX CE I/OX NC VCC WE Input Control Input or output – Supply Control Type Description Address inputs Chip enable Data input/outputs No connect. pins are not internally connected to the die Power (V) Write enable CY7C194BN 24-pin DIP 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 18, 19, 20, 21, 22, 23 11 14, 15, 16, 17 – 24 13 24-pin SOJ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 18, 19, 20, 21, 22, 23 11 14, 15, 16, 17 – 24 13 CY7C194BN Truth Table CE H L L WE X H L High Z Data out Data in I/Ox Read Write Mode Power-down Power Standby (ISB) Active (ICC) Active (ICC) Maximum Ratings Above which the useful life may be impaired. For user guidelines, not tested. Parameter TSTG TAMB VCC VIN, VOUT IOUT VESD ILU Storage temperature Ambient temperature with power applied (i.e. case temperature) Core supply voltage relative to VSS DC voltage applied to any pin relative to VSS Output short-circuit current Static discharge voltage (per MIL-STD-883, Method 3015) Latch-up current Description Value –65 to +150 –55 to +125 –0.5 to +7.0 –0.5 to VCC + 0.5 20 > 2001 > 200 Unit °C °C V V mA V mA Operating Range Range Commercial Ambient Temperature (TA) 0 °C to 70 °C Voltage Range (VCC) 5.0 V ± 10% Document #: 001-06446 Rev. *D Page 5 of 15 [+] Feedback CY7C194BN DC Electrical Characteristics Parameter [1] VIH VIL VOH VOL ICC ISB1 ISB2 Description Input HIGH voltage Input LOW voltage Output HIGH voltage Output LOW voltage VCC operating supply current Automatic CE Power-down current – TTL inputs Automatic CE Power-down current – CMOS inputs Output leakage current Input load current VCC = Min, lOH = –4.0 mA VCC = Min, lOL = 8.0 mA VCC = Max, IOUT = 0 mA, f = FMAX = 1 / tRC VCC = Max, CE  VIH, VIN  VIH or VIN  VIL, f = FMAX VCC = Max, CE  VCC – 0.3 V, VIN > VCC – 0.3 V or VIN  0.3 V, f = 0, Commercial GND  VI  VCC, output disabled GND  VI  VCC Condition 15 ns Min 2.2 –0.3 2.4 – – – Max VCC + 0.3 0.8 – 0.4 80 30 Unit V V V V mA mA – –5 –5 10 +5 +5 mA A A IOZ IIX Capacitance Parameter [2] CIN COUT Description Input capacitance Output capacitance Conditions TA = 25 °C, f = 1 MHz, VCC = 5.0 V Max 7 10 Unit pF – Thermal Resistance Parameter [2, 3] JA JC Description Thermal resistance (junction to ambient) Thermal resistance (junction to case) Conditions Still Air, soldered on a 3 x 4.5 square inches, two-layer printed circuit board CY7C194BN 24-pin DIP 75.69 33.80 24-pin SOJ 84.15 37.56 Unit °C/W Notes 1. VIL(min) = –2.0 V for pulse durations of less than 20 ns. 2. Tested initially and after any design or process change that may affect these parameters 3. Test Conditions assume a transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V. Document #: 001-06446 Rev. *D Page 6 of 15 [+] Feedback CY7C194BN AC Test Loads Output Loads R1 VCC VCC Output C1 R2 Output Loads for tHZOE, tHZCE & tHZWE for R3 C2 R4 (A)* (B)* All Input Pulses VCC 90% 90% Thevenin Equivalent Output Rth VT VSS 10% 10% Rise Time 1 V/ns Fall Time 1 V/ns * including scope and jig capacitance AC Test Conditions Parameter C1 C2 R1 R2 R3 R4 RTH VTH Capacitor 1 Capacitor 2 Resistor 1 Resistor 2 Resistor 3 Resistor 4 Resistor Thevenin Voltage Thevenin Description Nom 30 5 480 255 480 255 167 1.73 V  Unit pF Document #: 001-06446 Rev. *D Page 7 of 15 [+] Feedback CY7C194BN AC Electrical Characteristics Parameter [4, 5, 6, 7] tRC tAA tOHA tACE tLZCE tHZCE tPU tPD tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Read cycle time Address to data valid Data hold from address change CE to data valid CE to Low Z CE to High Z CE to Power-up CE to Power-down Write cycle time CE to write end Address set-up to write end Address hold from write end Address set-up to write start WE pulse width Data set-up to write end Data hold from write end WE LOW to High Z WE HIGH to Low Z Description 15 ns Min 15 – 3 – 3 – 0 – 15 10 10 0 0 9 8 0 – 3 Max – 15 – 15 – 7 – 15 – – – – – – – – 7 – Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Timing Waveforms Figure 1. Read Cycle No. 1 [8, 9] tRC Address tAA tOHA Data Out Previous Data Valid Data Valid Notes 4. Tested initially and after any design or process change that may affect these parameters 5. At any given temperature and voltage condition, tHZCE is less than tLZCE, and tHZWE is less than tLZWE for any given device. 6. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 7. tHZCE, tHZWE are specified as in part (b) of the A/C Test Loads. Transitions are measured ± 200 mV from steady state voltage. 8. Device is continuously selected. CE = VIL. 9. WE is HIGH for Read Cycle. Document #: 001-06446 Rev. *D Page 8 of 15 [+] Feedback CY7C194BN Timing Waveforms (continued) Figure 2. Read Cycle No. 2 [10, 11, 12] tRC Address CE tACE OE tDOE tLZOE Data Out ICC ISB High Z tLZCE tPU 50% Data Valid tPD 50% High Z tHZOE tHZCE V CC Current Figure 3. Write Cycle No. 1 (WE Controlled) [10, 13] t WC Address tSCE CE tAW tSA WE tSD Data In/Out Undefined see footnotes tHA tPWE tHD Undefined See Footnotes Data-In Valid tHZWE tLZWE Notes 10. Tested initially and after any design or process change that may affect these parameters 11. WE is HIGH in read cycle. 12. Address valid prior to or coincident with CE transition LOW. 13. The minimum write cycle time is the sum of tHZWE and tSD. Document #: 001-06446 Rev. *D Page 9 of 15 [+] Feedback CY7C194BN Timing Waveforms (continued) Figure 4. Write Cycle No. 2 (CE Controlled) [14, 15] tWC Address tSCE CE tSA tHA tAW WE tSD Data In/Out High Z Data-In Valid tHD High Z Notes 14. This cycle is CE controlled. 15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 001-06446 Rev. *D Page 10 of 15 [+] Feedback CY7C194BN Ordering Information Speed (ns) 15 Ordering Code CY7C194BN-15PC CY7C194BN-15VC Package Diagram 51-85013 51-85030 Package Type 24-pin DIP (6.6 × 31.8 × 3.5 mm) 24-pin SOJ (8 × 15 × 3.5 mm) Power Option Standard Standard Operating Range Commercial Commercial Please contact local sales representative regarding availability of these parts. Ordering Code Definitions CY 7 C 1 94 BN - 15 X C Temperature Range: C = Commercial Package Type: X = P or V P = 24-pin DIP V = 24-pin SOJ Speed: 15 ns BN = 0.25 µm Technology 94 = 256 K bit density with datawidth × 4bits 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS 7 = SRAM CY = Cypress Document #: 001-06446 Rev. *D Page 11 of 15 [+] Feedback CY7C194BN Package Diagrams Figure 5. 24-pin (300-mil) SOJ V24.3/VZ24.3 (Molded SOJ V13), 51-85030 51-85030 *C Figure 6. 24-pin PDIP (1.260 × 0.270 × 0.140 Inches) P24.3, 51-85013 51-85013 *C Document #: 001-06446 Rev. *D Page 12 of 15 [+] Feedback CY7C194BN Acronyms Acronym CE CMOS DIP ESD I/O SOJ SRAM TTL WE chip enable complementary metal oxide semiconductor dual in-line package electrostatic discharge input/output small outline J-lead static random access memory transistor-transistor logic write enable Description Document Conventions Units of Measure Symbol °C MHz A mA mm ns  % pF V W degree Celsius Mega Hertz micro Amperes milli Amperes milli meter nano seconds ohms percent pico Farad Volts Watts Unit of Measure Document #: 001-06446 Rev. *D Page 13 of 15 [+] Feedback CY7C194BN Document History Page Document Title: CY7C194BN, 256 Kb (64 K × 4) Static RAM Document Number: 001-06446 REV. ** *A ECN No. 424111 2892510 Issue Date See ECN 03/18/2010 Orig. of Change NXR VKN New Data Sheet Removed 25ns speed bin Updated Ordering Information table Updated Package Diagram Added Sales, Solutions, and Legal Information Added Ordering Code Definitions. Updated as per template Added TOC Added Acronyms and Units of Measure. Updated General Description (Removed “For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.”). Updated in new template. Description of Change *B *C 3108898 3219087 12/13/2010 04/18/2011 AJU PRAS *D 3271782 06/02/2011 PRAS Document #: 001-06446 Rev. *D Page 14 of 15 [+] Feedback CY7C194BN Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2006-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-06446 Rev. *D Revised June 2, 2011 Page 15 of 15 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback