CY7C197N_11

CY7C197N 256 K × 1 Static RAM 256 K × 1 Static RAM Features ■ Functional Description The CY7C197N is a high-performance CMOS static RAM organized as 256 K words by 1 bit. Easy memory expansion is provided by an active LOW Chip Enable (CE) and three-state drivers. The CY7C197N has an automatic power-down feature, reducing the power consumption by 75% when deselected. Writing to the device is accomplished when the Chip Enable (CE) and Write Enable (WE) inputs are both LOW. Data on the input pin (DIN) is written into the memory location specified on the address pins (A0 through A17). Reading the device is accomplished by taking chip enable (CE) LOW while Write Enable (WE) remains HIGH. Under these conditions the contents of the memory location specified on the address pins will appear on the data output (DOUT) pin. The output pin stays in a high-impedance state when Chip Enable (CE) is HIGH or Write Enable (WE) is LOW. The CY7C197N uses a die coat to insure alpha immunity. High speed ❐ 25 ns CMOS for optimum speed/power Low active power ❐ 880 mW Low standby power ❐ 220 mW Transistor-transistor logic (TTL)-compatible inputs and outputs Automatic power-down when deselected ■ ■ ■ ■ ■ Logic Block Diagram DI INPUT BUFFER A13 A14 A15 A16 A17 A0 A1 A2 A3 A4 ROW DECODER 1024 x 256 ARRAY SENSE AMPS DO COLUMN DECODER POWER DOWN CE A5 A6 A7 A8 A9 A10 A11 A12 WE Cypress Semiconductor Corporation Document #: 001-06495 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 1, 2011 CY7C197N Contents Pin Configurations ........................................................... 3 Selection Guide ................................................................ 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 4 Switching Characteristics ................................................ 5 Switching Waveforms ...................................................... 6 Typical DC and AC Characteristics ................................ 8 CY7C197N Truth Table ..................................................... 9 Ordering Information ........................................................ 9 Ordering Code Definitions ........................................... 9 Package Diagram ............................................................ 10 Acronyms ........................................................................ 11 Document Conventions ................................................. 11 Units of Measure ....................................................... 11 Document History Page ................................................. 12 Sales, Solutions, and Legal Information ...................... 13 Worldwide Sales and Design Support ....................... 13 Products .................................................................... 13 PSoC Solutions ......................................................... 13 Document #: 001-06495 Rev. *D Page 2 of 13 CY7C197N Pin Configurations Figure 1. 24-pin DIP (Top View) Selection Guide Description Maximum access time (ns) Maximum operating current (mA) Maximum standby current (mA) -25 25 95 30 A0 A1 A2 A3 A4 A5 A6 A7 A8 DOUT WE GND 1 24 2 23 22 3 4 21 5 20 6 7C197 19 18 7 8 17 9 16 10 15 14 11 12 13 VCC A17 A16 A15 A14 A13 A12 A11 A10 A9 DIN CE Document #: 001-06495 Rev. *D Page 3 of 13 CY7C197N DC input voltage[1] ............................... –0.5 V to VCC + 0.5 V Output current into outputs (LOW) .............................. 20 mA Static discharge voltage.......................................... > 2001 V (per MIL-STD-883, Method 3015) Latch up current..................................................... > 200 mA Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –65 °C to +150 °C Ambient temperature with power applied ........................................... –55 °C to +125 °C Supply voltage to ground potential (Pin 24 to Pin 12)..........................................–0.5 V to +7.0 V DC voltage applied to outputs in High Z state[1] .................................. –0.5 V to VCC + 0.5 V Operating Range Range Commercial Ambient Temperature 0 °C to +70 °C VCC 5 V ± 10% Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ IOS ICC ISB1 ISB2 Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage[1] GND < VI < VCC GND < VO < VCC, Output Disabled VCC = Max, VOUT = GND VCC = Max, IOUT = 0 mA, f = fMAX = 1/tRC Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX Max VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V Input load current Output leakage current Output short circuit current[2] VCC operating supply current Automatic CE power-down current—TTL inputs[3] Automatic CE power-down current—CMOS inputs[3] Test Conditions VCC = Min, IOH = –4.0 mA VCC = Min, IOL =12.0 mA -25 Min 2.4 – 2.2 –0.5 –5 –5 – – – – Max – 0.4 VCC + 0.3 V 0.8 +5 +5 –300 95 30 15 Unit V V V V A A mA mA mA mA Capacitance[4] Parameter CIN COUT Description Input capacitance Output capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = 5.0 V Max 8 10 Unit pF pF Notes 1. V(min.) = -2.0 V for pulse durations of less than 20 ns. 2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 3. A pull-up resistor to VCC on the CE input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given. 4. Tested initially and after any design or process changes that may affect these parameters. Document #: 001-06495 Rev. *D Page 4 of 13 CY7C197N Figure 2. AC Test Loads and Waveforms[5] R1 329 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE 5V OUTPUT R2 5 pF 202  (255 MIL) INCLUDING JIG AND SCOPE Equivalent to: R2 255  (255 MIL) 3.0 V 10% GND < tr < tr R1 329  ALL INPUT PULSES 90% 90% 10% (a) (b) THÉVENIN EQUIVALENT 125  OUTPUT 1.90 V Commercial Switching Characteristics Over the Operating Range[6] Parameter READ CYCLE tRC tAA tOHA tACE tLZCE tHZCE tPU tPD WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE [9] Description -25 Min 25 – 3 – 3 0 0 – 25 20 20 0 0 20 15 0 3 0 Max – 25 – 25 – 11 – 20 – – – – – – – – – 11 Unit Read cycle time Address to data valid Output hold from address change CE LOW to data valid CE LOW to low Z[7] Z[7, 8] CE HIGH to high ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CE LOW to power-up CE HIGH to power-down Write cycle time CE LOW to write end Address setup to write end Address hold from write end Address setup to write start WE pulse width Data setup to write end Data hold from write end WE HIGH to low Z[7] WE LOW to high Z[7, 8] Notes 5. tr = < 5 ns for the -25 and slower speeds. 6. Test conditions assume signal transition time of 5 ns or less for -25 and slower speeds, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE for any given device. 8. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) in AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage. 9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. Document #: 001-06495 Rev. *D Page 5 of 13 CY7C197N Switching Waveforms Figure 3. Read Cycle No. 1[10, 11] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Figure 4. Read Cycle No. 2[10] CE tACE tLZCE DATA OUT HIGH IMPEDANCE tRC tHZCE DATA VALID tPD HIGH IMPEDANCE VCC SUPPLY CURRENT tPU 50% ICC 50% ISB Figure 5. Write Cycle No. 1 (WE Controlled)[12] tWC ADDRESS tSCE CE tSA WE tSD DATA IN DATA VALID tHZWE DATA OUT DATA UNDEFINED tLZWE HIGH IMPEDANCE C197-8 tAW tPWE tHA tHD Notes 10. WE is HIGH for read cycle. 11. Device is continuously selected, CE = VIL. 12. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Document #: 001-06495 Rev. *D Page 6 of 13 CY7C197N Switching Waveforms (continued) Figure 6. Write Cycle No. 2 (CE Controlled)[13, 14] tWC ADDRESS tSA CE tAW tPWE WE tSD DATA IN DATA OUT DATA VALID HIGH IMPEDANCE tHD tHA tSCE Notes 13. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Document #: 001-06495 Rev. *D Page 7 of 13 CY7C197N Typical DC and AC Characteristics OUTPUT SOURCE CURRENT (mA) NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 NORMALIZED ICC, ISB 1.2 1.0 0.8 0.6 0.4 0.2 0.0 –55 ISB 25 125 AMBIENT TEMPERATURE (°C) VIN = 5.0 V VCC = 5.0 V ICC NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE ICC OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE(V) VCC = 5.0 V TA = 25°C 1.4 NORMALIZED ICC, ISB 1.2 1.0 0.8 0.6 0.4 0.2 VIN = 5.0 V TA = 25°C ISB 4.5 5.0 5.5 6.0 0.0 4.0 SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 NORMALIZED tAA NORMALIZED tAA 1.3 1.2 1.1 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE(V) TA = 25°C 1.6 1.4 1.2 1.0 OUTPUT SINK CURRENT (mA) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE 140 120 100 80 60 40 20 OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE VCC = 5.0 V 0.8 0.6 55 25 125 AMBIENT TEMPERATURE(°C) VCC = 5.0 V TA = 25°C 0 0.0 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE(V) TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 3.0 (ns) NORMALIZED IPO 2.5 2.0 1.5 1.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 5.0 TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 NORMALIZED ICC 25.0 20.0 15.0 10.0 5.0 0.0 0 200 400 VCC = 4.5 V TA = 25°C NORMALIZED ICC vs. CYCLE TIME 1.25 VCC = 5.0 V TA = 25°C VIN = 5.0 V DELTA tAA 1.00 0.75 600 800 1000 0.50 10 20 30 40 SUPPLY VOLTAGE (V) CAPACITANCE (pF) CYCLE FREQUENCY (MHz) Document #: 001-06495 Rev. *D Page 8 of 13 CY7C197N CY7C197N Truth Table CE H L L WE X H L High Z Data Out Data In Input/Output Deselect/Power-Down Read Write Mode Ordering Information Speed (ns) 25 Ordering Code CY7C197N-25PXC Package Diagram 51-85013 Package Type 24-pin (300-Mil) Molded DIP (Pb-free) Operating Range Commercial Contact your local sales representative regarding availability of these parts. Ordering Code Definitions CY 7C 197N - 25 PX C C = Temperature range (Commercial) PX = 24-pin molded DIP (Pb-free) 25 = Speed grade 197N = 256 K × 1 architecture Family: 7C = Fast asynchronous SRAM Company ID: CY = Cypress Document #: 001-06495 Rev. *D Page 9 of 13 CY7C197N Package Diagram Figure 7. 24-pin (300-Mil) PDIP (51-85013) 51-85013 *C Document #: 001-06495 Rev. *D Page 10 of 13 CY7C197N Acronyms Acronym CE CMOS DIP I/O PDIP SRAM TTL WE chip enable complementary metal oxide semiconductor dual inline package input/output plastic dual inline package static random access memory transistor-transistor logic write enable Description Document Conventions Units of Measure Symbol % °C mA MHz mV mW ns pF V  W µA percent degree Celsius milliamperes megahertz millivolts milliwatts nanoseconds picofarads volts ohms watts microamperes Unit of Measure Document #: 001-06495 Rev. *D Page 11 of 13 CY7C197N Document History Page Document Title: CY7C197N, 256 K × 1 Static RAM Document Number: 001-06495 REV. ** *A *B ECN NO. 424111 2958594 3095450 Submission Date See ECN 06/22/10 11/25/2010 Orig. of Change NXR AJU AJU Description of Change New Data Sheet The EOL Prune part number CY7C197N-45PXC removed & Updated package diagram. Updated template. Added Acronyms, Document Conventions, and Ordering Code Definitions Removed –45 information. Changed posting to external web. Updated in new template. Fixed units in Electrical Characteristics table. *C *D 3246053 3270287 05/02/2011 07/01/2011 PRAS AJU Document #: 001-06495 Rev. *D Page 12 of 13 CY7C197N Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2006-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. 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Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-06495 Rev. *D Revised July 1, 2011 Page 13 of 13 All products and company names mentioned in this document may be the trademarks of their respective holders.