CY7C197BN_11

CY7C197BN 256-Kb (256 K × 1) Static RAM 256-Kb (256 K × 1) Static RAM Features ■ ■ ■ ■ ■ General Description [1] The CY7C197BN is a high performance CMOS Asynchronous SRAM organized as 256 K × 1 bits that supports an asynchronous memory interface. The device features an automatic power down feature that significantly reduces power consumption when deselected. See the Truth Table on page 8 for a complete description of Read and Write modes. The CY7C197BN is available in 24-pin DIP and 24-pin SOJ package(s). Fast access time: 15 ns Wide voltage range: 5.0 V ± 10% (4.5 V to 5.5 V) CMOS for optimum speed and power TTL compatible inputs and outputs Available in 24-pin DIP and 24-pin SOJ Logic Block Diagram Input Buffer Din Row Decoder RAM Array Sense Amps Dout CE Column Decoder Power Down Circuit x WE Ax Product Portfolio Description Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current -15 15 150 10 -25 25 95 10 Unit ns mA mA Note 1. For best practice recommendations, refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document #: 001-06447 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised April 6, 2011 [+] Feedback CY7C197BN Contents Pin Layout and Specification ......................................... 3 Pin Description ................................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 DC Electrical Characteristics .......................................... 4 Capacitance ...................................................................... 4 Thermal Resistance .......................................................... 4 AC Test Loads .................................................................. 5 AC Test Conditions .......................................................... 5 AC Electrical Characteristics .......................................... 6 Timing Waveforms ........................................................... 6 Read Cycle No. 1 ........................................................ 6 Read Cycle No. 2 ........................................................ 7 Write Cycle No. 1 (WE Controlled) .............................. 7 Write Cycle No. 2 (CE Controlled) ............................... 8 Truth Table ........................................................................ 8 Ordering Information ........................................................ 9 Ordering Code Definitions ........................................... 9 Package Diagrams .......................................................... 10 Acronyms ........................................................................ 11 Document Conventions ................................................. 11 Units of Measure ....................................................... 11 Document History Page ................................................. 12 Sales, Solutions, and Legal Information ...................... 13 Worldwide Sales and Design Support ....................... 13 Products .................................................................... 13 PSoC Solutions ......................................................... 13 Document #: 001-06447 Rev. *C Page 2 of 13 [+] Feedback CY7C197BN Pin Layout and Specification 24-pin DIP (6.6 × 31.8 × 3.5 mm) A0 A1 A2 A3 A4 A5 A6 A7 A8 Dout WE GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A17 A16 A15 A14 A13 A12 A11 A10 A9 Din CE 24-pin SOJ (8 × 15 × 3.5 mm) A0 A1 A2 A3 A4 A5 A6 A7 A8 Dout WE GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A17 A16 A15 A14 A13 A12 A11 A10 A9 Din CE Pin Description Pin AX CE Din Dout VCC WE Type Input Control Input Output Supply Control Description Address Inputs Chip Enable Data Input Pins Data Output Pins Power (5.0 V) Write Enable DIP SOJ 1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 17, 1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 17, 18, 19, 20, 21, 22, 23 18, 19, 20, 21, 22, 23 13 14 10 24 11 13 14 10 24 11 Document #: 001-06447 Rev. *C Page 3 of 13 [+] Feedback CY7C197BN Maximum Ratings Exceeding the maximum rating may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ............................... –65 °C to +150 °C Ambient Temperature with Power Applied ......................................... –55 °C to +125 °C Supply Voltage on VCC to Relative GND ......–0.5 V to +7.0 V DC Voltage Applied to Outputs in High Z State[2] .................................. –0.5 V to VCC + 0.5 V DC Input Voltage[2] .............................. –0.5 V to VCC + 0.5 V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage...............................................2001 V (per MIL-STD-883, Method 3015) Latch Up Current .................................................... > 200 mA Operating Range Range Commercial Ambient Temperature[3] 0 °C to 70 °C VCC 5.0 V ± 10% DC Electrical Characteristics[2] Parameter VIH VIL VOH VOL IOZ IIX ICC ISB1 ISB2 Description Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Output Leakage Current Input Leakage Current VCC Operating Supply Current Automatic CE Power Down Current TTL Inputs Automatic CE Power Down Current CMOS Inputs VCC = Min, IOH = –4.0 mA VCC = Min, lOL = 8.0 mA GND  Vi  VCC, Output Disabled GND  Vi  VCC VCC = Max, IOUT = 0 mA, f = FMAX = 1/tRC VCC = Max, CE  VIH, VIN  VIH or VIN  VIL, f = FMAX VCC = Max, CE  VCC – 0.3 V, VIN  VCC – 0.3 V or VIN < 0.3 V, f=0 Condition 15 ns Min 2.2 –0.3 2.4 – –5 –5 – – – Max VCC + 0.3 0.8 – 0.4 +5 +5 150 30 10 Min 2.2 –0.3 2.4 – –5 –5 – – – 25 ns Max VCC + 0.3 0.8 – 0.4 +5 +5 95 30 10 Unit V V V V µA µA mA mA mA Capacitance[4] Parameter CIN COUT Description Input Capacitance Output Capacitance Conditions TA = 25 °C, f = 1 MHz, VCC = 5.0 V Max (ALL – PACKAGES) 8 10 Unit pF Thermal Resistance[4] Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Conditions Still Air, soldered on a 3 × 4.5 square inches, two-layer printed circuit board 24-pin DIP 75.69 33.80 24-pin SOJ 84.15 37.56 Unit °C/W Notes 2. VIL(min) = –2.0 V for pulse durations of less than 20 ns. 3. TA is the “instant on” case temperature. 4. Tested initially and after any design or process change that may affect these parameters. Document #: 001-06447 Rev. *C Page 4 of 13 [+] Feedback CY7C197BN AC Test Loads[5] Output Loads R1 VCC VCC Output Output Loads for tHZCE & tHZWE R3 C1 R2 C2 R4 (A)* All Input Pulses VCC 90% (B)* Thevenin Equivalent 90% Output RTH VTH VSS 10% 10% Rise Time 1 V/ns * including scope and jig capacitance Fall Time 1 V/ns AC Test Conditions Parameter C1 C2 R1 R2 R3 R4 RTH VTH Description Capacitor 1 Capacitor 2 Resistor 1 Resistor 2 Resistor 3 Resistor 4 Resistor Thevenin Voltage Thevenin Nom. 30 5 480 255 480 255 167 1.73 V  Unit pF Note 5. Test Conditions assume a transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V. Document #: 001-06447 Rev. *C Page 5 of 13 [+] Feedback CY7C197BN AC Electrical Characteristics[4, 6, 7, 8] Parameter tRC tAA tOHA tACE tLZCE tHZCE tPU tPD tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CE to Data Valid CE to Low Z CE to High Z CE to Power-up CE to Power-down Write Cycle Time CE to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE LOW to High Z WE HIGH to Low Z Description 15 ns Min 15 – 3 – 3 – 0 – 15 9 10 0 0 9 9 0 – 2 Max – 15 – 15 – 5 – 15 – – – – – – – – 7 – Min 25 – 3 – 3 – 0 – 25 20 20 0 0 20 15 0 – 3 25 ns Max – 25 – 25 – 11 – 20 – – – – – – – – 11 – Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Timing Waveforms Read Cycle No. 1 [9, 10] tRC Address tAA tOHA Data Out Previous Data Valid Data Valid Notes 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, and tHZWE is less than tLZWE for any given device. 7. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the Write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write. 8. tHZCE, tHZWE are specified as in part (b) of the AC Test Loads[5] on page 5. Transitions are measured ±200 mV from steady state voltage. 9. Device is continuously selected. CE = VIL. 10. WE is HIGH for Read Cycle. Document #: 001-06447 Rev. *C Page 6 of 13 [+] Feedback CY7C197BN Timing Waveforms (continued) Read Cycle No. 2 [11, 12, 13] tRC Address CE tACE tLZCE tHZCE High Z Data Out tPU Data Valid tPD 50% 50% High Z ICC Vcc Supply Current ISB Write Cycle No. 1 (WE Controlled) [11, 14] tWC Address tSCE CE tAW tSA WE tSD Data In tHZWE Data Out Data Undefined Data Valid tLZWE High Impedance tHD tPWE tHA Notes 11. Tested initially and after any design or process change that may affect these parameters. 12. WE is HIGH in read cycle. 13. Address valid prior to or coincident with CE transition LOW. 14. The minimum write cycle time is the sum of tHZWE and tSD. Document #: 001-06447 Rev. *C Page 7 of 13 [+] Feedback CY7C197BN Timing Waveforms (continued) Write Cycle No. 2 (CE Controlled)[15, 16] tWC Address tSA CE tHA tPWE WE tSD Data In Data Valid High Z tHD tSCE tAW Data Out Truth Table CE H L L WE X H L High Z Data Out Data In I/Ox Read Write Mode Deselect/Power-Down Power Standby (ISB) Active (ICC) Active (ICC) Notes 15. This cycle is CE controlled. 16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document #: 001-06447 Rev. *C Page 8 of 13 [+] Feedback CY7C197BN Ordering Information Speed (ns) 15 25 Ordering Code CY7C197BN-15VC CY7C197BN-25PC Package Diagram 51-85030 51-85013 Package Type 24-pin SOJ (8 × 15 × 3.5 mm) 24-pin DIP (6.6 × 31.8 × 3.5 mm) Operating Range Commercial Commercial Ordering Code Definitions CY 7 C 1 97 BN - XX X C Temperature Range: C = Commercial Package Type: XX = V or P V = 24-pin SOJ P = 24-pin DIP Speed: XX = 15 ns or 25 ns BN = 0.25 µm Technology 97 = 256-Kbit density with datawidth × 1 bit 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS 7 = SRAM CY = Cypress Please contact local sales representative regarding availability of these parts. Document #: 001-06447 Rev. *C Page 9 of 13 [+] Feedback CY7C197BN Package Diagrams Figure 1. 24-pin (300-mil) SOJ, 51-85030 51-85030 *C Figure 2. 24-pin DIP (6.6 × 31.8 × 3.5 mm), 51-85013 51-85013 *C Document #: 001-06447 Rev. *C Page 10 of 13 [+] Feedback CY7C197BN Acronyms Acronym CMOS CE DIP SOJ SRAM TTL WE chip enable dual in-line package small outline J-lead static random access memory transistor-transistor logic write enable Description complementary metal oxide semiconductor  ns V µA mA mm ms MHz pF W % °C Document Conventions Units of Measure Symbol ohms nano seconds Volts micro Amperes milli Amperes milli meter milli seconds Mega Hertz pico Farad Watts percent degree Celcius Unit of Measure Document #: 001-06447 Rev. *C Page 11 of 13 [+] Feedback CY7C197BN Document History Page Document Title: CY7C197BN 256-Kb (256 K × 1) Static RAM Document Number: 001-06447 REV. ** *A ECN No. 901742 2892510 Issue Date See ECN 03/18/2010 Orig. of Change NXR VKN New Data Sheet Removed 12ns speed bin Updated Ordering Information table Updated Package Diagrams Added Sales, Solutions, and Legal Information Added Ordering Code Definitions. Added Acronyms and Units of Measure. Updated in new template. Description of Change *B *C 3108898 3217480 12/13/2010 04/06/2011 AJU PRAS Document #: 001-06447 Rev. *C Page 12 of 13 [+] Feedback CY7C197BN Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2007-2011. 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Document #: 001-06447 Rev. *C Revised April 6, 2011 Page 13 of 13 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback