CY7C197BN-12VC

CY7C197BN 256 Kb (256K x 1) Static RAM Features • • • • • Fast access time: 12 ns Wide voltage range: 5.0V ± 10% (4.5V to 5.5V) CMOS for optimum speed and power TTL compatible inputs and outputs Available in 24-lead DIP and 24-lead SOJ General Description [1] The CY7C197BN is a high performance CMOS Asynchronous SRAM organized as 256K × 1 bits that supports an asynchronous memory interface. The device features an automatic power down feature that significantly reduces power consumption when deselected. See the “Truth Table” on page 7 for a complete description of Read and Write modes. The CY7C197BN is available in 24-lead DIP and 24-lead SOJ package(s). Logic Block Diagram Din Input Buffer Row Decoder RAM Array Sense Amps Dout CE Column Decoder Power Down Circuit x WE Ax Product Portfolio -12 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 12 150 10 -15 15 150 10 -25 25 95 10 Unit ns mA mA Notes 1. For best practice recommendations, refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document #: 001-06447 Rev. ** • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 21, 2007 [+] [+] Feedback CY7C197BN Pin Layout and Specification 24-lead DIP (6.6 × 31.8 × 3.5 mm) A0 A1 A2 A3 A4 A5 A6 A7 A8 Dout WE GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A17 A16 A15 A14 A13 A12 A11 A10 A9 Din CE 24-lead SOJ (8 × 15 × 3.5 mm) A0 A1 A2 A3 A4 A5 A6 A7 A8 Dout WE GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A17 A16 A15 A14 A13 A12 A11 A10 A9 Din CE Pin Description Pin AX CE Din Dout VCC WE Type Input Control Input Output Supply Control Description Address Inputs Chip Enable Data Input Pins Data Output Pins Power (5.0V) Write Enable DIP SOJ 1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 17, 1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 17, 18, 19, 20, 21, 22, 23 18, 19, 20, 21, 22, 23 13 14 10 24 11 13 14 10 24 11 Page 2 of 9 Document #: 001-06447 Rev. ** [+] Feedback CY7C197BN Maximum Ratings Exceeding the maximum rating may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC to Relative GND........ –0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[2] .....................................–0.5V to VCC +0.5V DC Input Voltage[2] ..................................–0.5V to VCC +0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage...............................................2001V (per MIL-STD-883, Method 3015) Latch Up Current ..................................................... >200 mA Operating Range Range Commercial Ambient Temperature[3] 0°C to 70°C VCC 5.0V ± 10% DC Electrical Characteristics[2] Parameter VIH VIL VOH VOL IOZ IIX ICC ISB1 Description Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Output Leakage Current Input Leakage Current VCC Operating Supply Current VCC = Min, IOH = –4.0 mA VCC = Min, lol = 8.0 mA GND ≤ Vi ≤ VCC, Output Disabled GND ≤ Vi ≤ VCC VCC = Max, IOUT = 0 mA, f = FMAX = 1/tRC Condition 12 and 15 ns Min 2.2 –0.3 2.4 – –5 –5 – – Max VCC+0.3 0.8 – 0.4 +5 +5 150 30 Min 2.2 –0.3 2.4 – –5 –5 – – 25 ns Max VCC+0.3 0.8 – 0.4 +5 +5 95 30 Unit V V V V µA µA mA mA Automatic CE Power VCC = Max, Down Current TTL Inputs CE ≥ VIH, VIN ≥ VIH or VIN ≤ VIL, f = FMAX Automatic CE Power Down Current CMOS Inputs VCC = Max, CE ≥ VCC – 0.3V, VIN ≥ VCC – 0.3V or VIN < 0.3V, f = 0 ISB2 – 10 – 10 mA Capacitance[4] Parameter CIN COUT Description Input Capacitance Output Capacitance Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max (ALL – PACKAGES) 8 10 Unit pF Thermal Resistance[4] Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Conditions Still Air, soldered on a 3 x 4.5 square inches, two-layer printed circuit board 24 DIP 75.69 33.80 24 SOJ 84.15 37.56 Unit °C/W Notes 2. VIL(min) = –2.0V for pulse durations of less than 20 ns. 3. TA is the “instant on” case temperature 4. Tested initially and after any design or process change that may affect these parameters Document #: 001-06447 Rev. ** Page 3 of 9 [+] [+] Feedback CY7C197BN AC Test Loads[5] Output Loads R1 VCC VCC Output Output Loads for tHZCE & tHZWE R3 C1 R2 C2 R4 (A)* All Input Pulses VCC 90% (B)* Thevenin Equivalent 90% Output RTH VTH VSS 10% 10% Rise Time 1 V/ns * including scope and jig capacitance Fall Time 1 V/ns AC Test Conditions Parameter C1 C2 R1 R2 R3 R4 RTH VTH Description Capacitor 1 Capacitor 2 Resistor 1 Resistor 2 Resistor 3 Resistor 4 Resistor Thevenin Voltage Thevenin Nom. 30 5 480 255 480 255 167 1.73 V Ω Unit pF Note 5. Test Conditions assume a transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V Document #: 001-06447 Rev. ** Page 4 of 9 [+] [+] Feedback CY7C197BN AC Electrical Characteristics[4, 6, 7, 8] Parameter tRC tAA tOHA tACE tLZCE tHZCE tPU tPD tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE to Data Valid CE to Low Z CE to High Z CE to Power-up CE to Power-down Write Cycle Time CE to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE LOW to High Z WE HIGH to Low Z 12 ns Min 12 – 3 – 3 – 0 – 12 9 9 0 0 8 8 0 – 2 Max – 12 – 12 – 5 – 12 – – – – – – – – 7 – Min 15 – 3 – 3 – 0 – 15 9 10 0 0 9 9 0 – 2 15 ns Max – 15 – 15 – 5 – 15 – – – – – – – – 7 – Min 25 – 3 – 3 – 0 – 25 20 20 0 0 20 15 0 – 3 25 ns Max – 25 – 25 – 11 – 20 – – – – – – – – 11 – Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Timing Waveforms Read Cycle No. 1[9, 10] tRC Address tAA tOHA Data Out Previous Data Valid Data Valid Notes 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, and tHZWE is less than tLZWE for any given device. 7. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the Write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write. 8. tHZCE, tHZWE are specified as in part (b) of the “AC Test Loads[5]” on page 4. Transitions are measured ±200 mV from steady state voltage. 9. Device is continuously selected. CE = VIL. 10. WE is HIGH for Read Cycle. Document #: 001-06447 Rev. ** Page 5 of 9 [+] [+] Feedback CY7C197BN Timing Waveforms (continued) Read Cycle No. 2[4, 11, 12] tRC Address CE tACE tLZCE tHZCE High Z Data Out tPU Data Valid tPD 50% 50% High Z ICC Vcc Supply Current ISB Write Cycle No. 1 (WE Controlled)[4, 13] tWC Address tSCE CE tAW tSA WE tSD Data In tHZWE Data Out Data Undefined Data Valid tLZWE High Impedance tHD tPWE tHA Notes 11. WE is HIGH in read cycle. 12. Address valid prior to or coincident with CE transition LOW. 13. The minimum write cycle time is the sum of tHZWE and tSD. Document #: 001-06447 Rev. ** Page 6 of 9 [+] [+] Feedback CY7C197BN Timing Waveforms (continued) Write Cycle No. 2 (CE Controlled)[14, 15] tWC Address tSA CE tHA tPWE WE tSD Data In Data Valid High Z tHD tSCE tAW Data Out Truth Table CE H L L WE X H L High Z Data Out Data In I/Ox Read Write Mode Deselect/Power-Down Power Standby (ISB) Active (ICC) Active (ICC) Ordering Information Speed (ns) 12 15 25 Ordering Code CY7C197BN-12VC CY7C197BN-15VC CY7C197BN-25PC Package Diagram 51-85030 51-85030 51-85013 Package Type 24-lead SOJ (8 x 15 x 3.5 mm) 24-lead SOJ (8 x 15 x 3.5 mm) 24-lead DIP (6.6 x 31.8 x 3.5 mm) Operating Range Commercial Commercial Commercial Please contact local sales representative regarding availability of these parts. Notes 14. This cycle is CE controlled. 15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document #: 001-06447 Rev. ** Page 7 of 9 [+] [+] Feedback CY7C197BN Package Diagrams Figure 1. 24-lead (300-mil) SOJ (51-85030) PIN 1 ID 12 1 DIMENSIONS IN INCHES[MM] REFERENCE JEDEC MO-088 0.291[7.39] 0.300[7.62] 0.330[8.38] 0.350[8.89] MIN. MAX. PACKAGE WEIGHT 0.75gms PART # 13 24 V24.3 VZ24.3 STANDARD PKG. LEAD FREE PKG. 0.597[15.16] 0.613[15.57] SEATING PLANE 0.120[3.05] 0.140[3.55] 0.004[0.10] 0.050[1.27] TYP. 0.025[0.63] MIN. 0.013[0.33] 0.019[0.48] 0.007[0.17] 0.013[0.33] 0.262[6.65] 0.272[6.91] 51-85030-*B Figure 2. 24-lead DIP (6.6 x 31.8 x 3.5 mm) (51-85013) 51-85013-*B All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-06447 Rev. ** Page 8 of 9 © Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] [+] Feedback CY7C197BN Document History Page Document Title: CY7C197BN 256 Kb (256K x 1) Static RAM Document Number: 001-06447 REV. ** ECN No. 901742 Issue Date See ECN Orig. of Change NXR New Data Sheet Description of Change Document #: 001-06447 Rev. ** Page 9 of 9 [+] [+] Feedback