CY7C106BN_11

CY7C106BN 256K x 4 Static RAM Features ■ Functional Description The CY7C106BN is a high performance CMOS static RAMs organized as 262,144 words by 4 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tristate drivers. These devices have an automatic power down feature that reduces power consumption by more than 65% when the devices are deselected. Writing to the devices is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the four I/O pins (I/O0 through I/O3) is then written into the location specified on the address pins (A0 through A17). Reading from the devices is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the four I/O pins. The four input/output pins (I/O0 through I/O3) are placed in a high impedance state when the devices are deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE and WE LOW). The CY7C106BN is available in a standard 400-mil-wide SOJ. High speed ❐ tAA = 15 ns CMOS for optimum speed/power Low active power ❐ 495 mW Low standby power ❐ 275 mW 2.0V data retention (optional) Automatic power down when deselected TTL-compatible inputs and outputs ■ ■ ■ ■ ■ ■ Logic Block Diagram INPUT BUFFER A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER SENSE AMPS I/O3 I/O2 I/O1 I/O0 512 x 512 x 4 ARRAY COLUMN DECODER POWER DOWN CE WE 15 16 10 12 A0 13 14 11 17 OE Cypress Semiconductor Corporation Document #: 001-06429 Rev. *A • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 15, 2010 [+] Feedback CY7C106BN Pin Configuration Figure 1. 28-pin SOJ (Top View) A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 CE OE GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A17 A16 A15 A14 A13 A12 A11 NC I/O3 I/O2 I/O1 I/O0 WE Selection Guide Description Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA) 7C106BN-15 15 80 30 Document #: 001-06429 Rev. *A Page 2 of 9 [+] Feedback CY7C106BN Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................ –65×C to +150×C Ambient Temperature with Power Applied ........................................... –55×C to +125×C Supply Voltage on VCC Relative to GND[1] .....–0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] .................................... –0.5V to VCC + 0.5V DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch Up Current ..................................................... >200 mA Operating Range Range Commercial Ambient Temperature[2] 0°C to +70°C VCC 5V ± 10% Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ IOS ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Leakage Current Output Leakage Current Output Short Circuit Current[3] VCC Operating Supply Current GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max, VOUT = GND VCC = Max, IOUT = 0 mA, f = fMAX = 1/tRC Test Conditions VCC = Min, IOH = – 4.0 mA VCC = Min, IOL = 8.0 mA 2.2 –0.3 –1 –5 7C106BN-15 Min 2.4 0.4 VCC + 0.3 0.8 +1 +5 –300 80 30 10 Max Unit V V V V mA mA mA mA mA mA Automatic CE Power Down Current Max VCC, CE > VIH, VIN > VIH or VIN < —TTL Inputs VIL, f = fMAX Automatic CE Power Down Current Max VCC, —CMOS Inputs CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V, f=0 Commercial Capacitance[4] Parameter CIN: Addresses CIN: Controls COUT Output Capacitance Description Input Capacitance Test Conditions TA = 25×C, f = 1 MHz, VCC = 5.0V Max 7 10 10 Unit pF pF pF Notes 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. TA is the “instant on” case temperature. 3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 4. Tested initially and after any design or process changes that may affect these parameters. Document #: 001-06429 Rev. *A Page 3 of 9 [+] Feedback CY7C106BN Figure 2. AC Test Loads and Waveforms 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 255Ω R1 480Ω 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 GND 255Ω Rise Time < 1V/ns R1 480Ω 3.0V ALL INPUT PULSES 90% 10% 90% 10% Fall Time < 1V/ns (a) Equivalent to: OUTPUT THÉVENIN EQUIVALENT 167Ω 1.73V (b) Switching Characteristics Over the Operating Range[5] Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE [8, 9] Description 7C106B-15 Min 15 15 3 15 7 0 7 3 7 0 15 15 12 12 0 0 12 8 0 3 7 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High CE HIGH to High Z[6, 7] Z[6, 7] CE LOW to Low Z[7] CE LOW to Power Up CE HIGH to Power Down Write Cycle Time CE LOW to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE HIGH to Low Z[7] WE LOW to High Z[6, 7] Notes 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30 pF load capacitance. 6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. The internal write time of the memory is defined by the overlap of CE and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 001-06429 Rev. *A Page 4 of 9 [+] Feedback CY7C106BN Data Retention Characteristics Over the Operating Range Parameter VDR ICCDR tCDR[4] tR [4] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Conditions[10] VCC = VDR = 2.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V Min 2.0 Max 250 Unit V μA ns ms 0 200 Figure 3. Data Retention Waveform DATA RETENTION MODE VCC 4.5V tCDR CE VDR > 2V 4.5V tR Switching Waveforms 1 Figure 4. Read Cycle No.1[11, 12] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Figure 5. Read Cycle No. 2 (OE Controlled)[12, 13] ADDRESS tRC CE tACE OE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU 50% DATA VALID tPD 50% tHZOE tHZCE HIGH IMPEDANCE ICC ISB Notes 10. No input may exceed VCC +0.5V. 11. Device is continuously selected, OE and CE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. Document #: 001-06429 Rev. *A Page 5 of 9 [+] Feedback CY7C106BN Switching Waveforms (continued) Figure 6. Write Cycle No. 1 (CE Controlled)[14, 15] tWC ADDRESS tSCE CE tSA tAW tPWE WE tSD DATA I/O DATA VALID tHD tHA Figure 7. Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15] tWC ADDRESS tSCE CE tAW tSA WE OE tSD DATA I/O tHZOE DATA VALID tPWE tHA tHD Notes 14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. 15. Data I/O is high impedance if OE = VIH. Document #: 001-06429 Rev. *A Page 6 of 9 [+] Feedback CY7C106BN Switching Waveforms (continued) Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW)[9, 15] tWC ADDRESS tSCE CE tAW tSA WE tSD DATA I/O tHZWE DATA VALID tPWE tHA tHD tLZWE Truth Table CE H L L L OE X L X H WE X H L H Input/Output High Z Data Out Data In High Z Power Down Read Write Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 15 Ordering Code CY7C106BN-15VC Package Diagram 51-85032 Package Type 28-Pin (400-Mil) Molded SOJ Operating Range Commercial Contact your local sales representative regarding availability of these parts. Document #: 001-06429 Rev. *A Page 7 of 9 [+] Feedback CY7C106BN Package Diagram Figure 9. 28-Pin (400 Mil) Molded SOJ PIN 1 I.D 14 1 .395 .405 .435 .445 DIMENSIONS IN INCHES MIN. MAX. 15 .720 .730 28 SEATING PLANE NO CHAMFER .128 .148 .050 TYP. .015 .020 NOTES : 1. PACKAGE WEIGHT : 1.24g 2. JEDEC REFERENCE : MS-027 .026 .032 0.004 .025 MIN. .360 .380 .007 .013 51-85032-*B 51-85032.*D Document #: 001-06429 Rev. *A Page 8 of 9 [+] Feedback CY7C106BN Document History Page Document Title: CY7C106BN 256K x 4 Static RAM Document Number: 001-06429 REV. ** *A ECN NO. 423847 2891262 Submission Date See ECN 03/12/2010 Orig. of Change NXR VKN New Data sheet Removed CY7C1006BN part from the data sheet Removed Industrial grade Removed 20ns speed bin Removed 28-pin (300-Mil) Molded SOJ package Updated POD for 28-pin (400-Mil) Molded SOJ package Updated Ordering information table Updated URLs in Sales, Solutions, and Legal Information Description of Change Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2006-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. 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Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-06429 Rev. *A Revised March 15, 2010 Page 9 of 9 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback