CY7C199D-10ZXI

CY7C199D 256K (32K x 8) Static RAM Features • Pin- and function-compatible with CY7C199C • High speed — tAA = 10 ns • Low active power — ICC = 80 mA @ 10 ns • Low CMOS standby power — ISB2 = 3 mA • 2.0V Data Retention • Automatic power-down when deselected • CMOS for optimum speed/power • TTL-compatible inputs and outputs • Easy memory expansion with CE and OE features • Available in Pb-free 28-pin 300-Mil wide Molded SOJ and 28-pin TSOP I packages Functional Description [1] The CY7C199D is a high-performance CMOS static RAM organized as 32,768 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE) and tri-state drivers. This device has an automatic power-down feature, reducing the power consumption when deselected. The input and output pins (IO0 through IO7) are placed in a high-impedance state when: • Deselected (CE HIGH) • Outputs are disabled (OE HIGH) • When the write operation is active(CE LOW and WE LOW) Write to the device by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight IO pins (IO0 through IO7) is then written into the location specified on the address pins (A0 through A14). Read from the device by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appears on the IO pins. Logic Block Diagram INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 CE WE OE IO0 IO1 ROW DECODER 32K x 8 ARRAY SENSE AMPS IO2 IO3 IO4 IO5 IO6 COLUMN DECODER POWER DOWN IO7 A10 A12 A13 Note: 1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com. A11 A14 Cypress Semiconductor Corporation Document #: 38-05471 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 01, 2007 [+] [+] Feedback CY7C199D Pin Configurations SOJ Top View A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 IO 0 IO 1 IO 2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE IO 7 IO 6 IO 5 IO 4 IO 3 OE A1 A2 A3 A4 WE V CC A5 A6 A7 A8 A9 A 10 A 11 22 23 24 25 26 27 28 1 2 3 4 5 6 7 TSOP I Top View (not to scale) 21 20 19 18 17 16 15 14 13 12 11 10 9 8 A0 CE IO 7 IO 6 IO 5 IO 4 IO 3 GND IO 2 IO 1 IO 0 A 14 A 13 A 12 Selection Guide CY7C199D-10 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 10 80 3 Unit ns mA mA Document #: 38-05471 Rev. *D Page 2 of 10 [+] [+] Feedback CY7C199D Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC to Relative GND [2] ... –0.5V to +6.0V DC Voltage Applied to Outputs in High-Z State [2] ...................................–0.5V to VCC + 0.5V DC Input Voltage [2] ............................... –0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current ................................................... > 200 mA Operating Range Range Industrial Ambient Temperature –40°C to +85°C VCC 5V ± 0.5V Speed 10 ns Electrical Characteristics (Over the Operating Range) 7C199D-10 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage [2] Test Conditions IOH=–4.0 mA IOL=8.0 mA Min 2.4 Max Unit V 0.4 2.0 –0.5 VCC + 0.5 0.8 +1 +1 80 72 58 37 10 3 V V V µA µA mA mA mA mA mA mA Input LOW Voltage [2] Input Leakage Current Output Leakage Current VCC Operating Supply Current GND < VI < VCC GND < VO < VCC, Output Disabled VCC = Max, IOUT = 0 mA, f = fmax = 1/tRC 100 MHz 83 MHz 66 MHz 40 MHz –1 –1 ISB1 ISB2 Automatic CE Power-down Current— TTL Inputs Automatic CE Power-down Current— CMOS Inputs Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fmax Max VCC, CE > VCC – 0.3V VIN > VCC – 0.3V or VIN < 0.3V, f = 0 Note: 2. VIL(min) = –2.0V and VIH(max) = VCC + 1V for pulse durations of less than 5 ns. Document #: 38-05471 Rev. *D Page 3 of 10 [+] [+] Feedback CY7C199D Capacitance [3] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max 8 8 Unit pF pF Thermal Resistance [3] Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board SOJ 59.16 40.84 TSOP I 54.65 21.49 Unit °C/W °C/W AC Test Loads and Waveforms [4] Z = 50Ω OUTPUT 50 Ω * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 1.5V Rise Time: ≤ 3 ns ALL INPUT PULSES 3.0V 30pF* GND 10% 90% 90% 10% (a) High-Z characteristics: 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 255Ω (b) Fall Time: ≤ 3 ns R1 480Ω (c) Notes: 3. Tested initially and after any design or process changes that may affect these parameters. 4. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c). Document #: 38-05471 Rev. *D Page 4 of 10 [+] [+] Feedback CY7C199D Switching Characteristics (Over the Operating Range) [5] 7C199D-10 Parameter Read Cycle tpower [6] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tPU tPD [7] [7, 8] Description Min Max Unit VCC(typical) to the first access Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z OE HIGH to High-Z CE LOW to Low-Z CE HIGH to High-Z CE LOW to Power-up CE HIGH to Power-down [10, 11] 100 10 10 3 10 5 0 5 3 5 0 10 µs ns ns ns ns ns ns ns ns ns ns ns [7] tHZCE [7, 8] [9] [9] Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE [7] tLZWE [7, 8] Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE LOW to High-Z WE HIGH to Low-Z 10 7 7 0 0 7 5 0 6 3 ns ns ns ns ns ns ns ns ns ns Notes: 5. Test conditions assume signal transition time of 3 ns or less for all speeds, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of “AC Test Loads and Waveforms [4]” on page 4. Transition is measured ±200 mV from steady-state voltage. 9. This parameter is guaranteed by design and is not tested. 10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 11. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD . Document #: 38-05471 Rev. *D Page 5 of 10 [+] [+] Feedback CY7C199D Data Retention Characteristics (Over the Operating Range) Parameter VDR ICCDR tCDR [3] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Conditions VCC = VDR = 2.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V Min 2.0 Max Unit V 3 0 tRC mA ns ns tR [12] Data Retention Waveform DATA RETENTION MODE VCC CE 4.5V tCDR VDR > 2V 4.5V tR Switching Waveforms Read Cycle No. 1 (Address Transition Controlled) [13, 14] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Read Cycle No. 2 (OE Controlled) [14, 15] CE tACE OE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZOE tHZCE DATA VALID tPD ICC 50% ISB tRC DATA OUT HIGH IMPEDANCE Notes: 12. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 µs or stable at VCC(min) > 50 µs. 13. Device is continuously selected. OE, CE = VIL. 14. WE is HIGH for read cycle. 15. Address valid prior to or coincident with CE transition LOW. Document #: 38-05471 Rev. *D Page 6 of 10 [+] [+] Feedback CY7C199D Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled) [10, 16, 17] tWC ADDRESS CE tSA tAW tHA tSCE WE tSD DATA IO DATA IN VALID tHD Write Cycle No. 2 (WE Controlled) [10, 16, 17] tWC ADDRESS CE tAW WE tSA tPWE tHA OE tSD DATA IO NOTE 18 tHZOE DATAIN VALID tHD Write Cycle No. 3 (WE Controlled, OE LOW) [11, 17] tWC ADDRESS CE tAW tSA WE tHA tSD DATA IO NOTE 18 tHZWE Notes: 16. Data IO is high impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 18. During this period the IOs are in the output state and input signals should not be applied. tHD DATAIN VALID tLZWE Document #: 38-05471 Rev. *D Page 7 of 10 [+] [+] Feedback CY7C199D Truth Table CE H L L L WE X H L H OE X L X H Inputs/Outputs High Z Data Out Data In High Z Read Write Deselect, Output disabled Mode Deselect/Power-down Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 10 Ordering Code CY7C199D-10VXI CY7C199D-10ZXI Package Diagram 51-85031 51-85071 Package Type 28-pin (300-Mil) Molded SOJ (Pb-Free) 28-pin TSOP Type I (Pb-free) Operating Range Industrial Please contact your local Cypress sales representative for availability of these parts. Package Diagrams Figure 1. 28-pin (300-Mil) Molded SOJ, 51-85031 NOTE : 1. JEDEC STD REF MO088 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.006 in (0.152 mm) PER SIDE 3. DIMENSIONS IN INCHES MIN. MAX. PIN 1 ID 14 1 DETAIL A EXTERNAL LEAD DESIGN 0.291 0.300 0.330 0.350 0.013 0.019 OPTION 1 OPTION 2 0.026 0.032 0.014 0.020 15 28 0.697 0.713 0.120 0.140 0.050 TYP. SEATING PLANE 0.007 0.013 0.004 A 0.025 MIN. 0.262 0.272 51-85031-*C Document #: 38-05471 Rev. *D Page 8 of 10 [+] [+] Feedback CY7C199D Package Diagrams (continued) Figure 2. 28-pin Thin Small Outline Package Type 1 (8x13.4 mm), 51-85071 51-85071-*G All products and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05471 Rev. *D Page 9 of 10 © Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] [+] Feedback CY7C199D Document History Page Document Title: CY7C199D, 256K (32K x 8) Static RAM Document Number: 38-05471 REV. ** *A *B ECN NO. Issue Date 201560 233728 262950 See ECN See ECN See ECN Orig. of Change SWI RKF RKF Description of Change Advance Information data sheet for C9 IPP DC parameters modified as per EROS (Spec # 01-02165) Pb-free Offering in Ordering Information Removed 28-LCC Pinout and Package Diagrams Added Data Retention Characteristics table Added Tpower Spec in Switching Characteristics table Shaded Ordering Information Reduced Speed bins to -10, -12 and -15 ns Converted from Preliminary to Final Removed 12 ns and 15 ns speed bin Removed Commercial Operating range Removed “L” part Removed 28-pin PDIP and 28-pin SOIC package Changed Overshoot spec from VCC+2V to VCC+1V in footnote #2 Changed ICC spec from 60 mA to 80 mA for 100 MHz speed bin Added ICC specs for 83 MHz, 66 MHz and 40 MHz speed bins Updated Thermal Resistance table Updated Ordering Information Table *C *D 307594 820660 See ECN See ECN RKF VKN Document #: 38-05471 Rev. *D Page 10 of 10 [+] Feedback