Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CY7C652148
USB-SPI Single Channel Bridge Controller
CY7C652148, USB-SPI Single Channel Bridge Controller
Features
■
USB 2.0-compliant, Full-Speed (12 Mbps)
❐ Supports communication driver class (CDC), personal health
care device class (PHDC), and vendor-device class
❐ Battery charger detection (BCD) compliant with USB Battery
Charging Specification, Rev. 1.2 (Peripheral Detect only)
❐ Integrated USB termination resistors
■ Single-channel configurable SPI interface
❐ Data rate up to 3 MHz for SPI master and 1 MHz for SPI slave
❐ Data width: 4 bits to 16 bits
❐ 256 bytes for each transmit and receive buffer
❐ Supports Motorola, TI, and National SPI modes
■
Ordering part number
❐ CY7C652148-24LTXI
❐ CY7C652148-24LTXIT
Applications
■
Medical/healthcare devices
■
Point-of-Sale (POS) terminals
■
Test and measurement system
■
Gaming systems
■
Set-top box PC-USB interface
■
Industrial
■
General-purpose input/output (GPIO) pins: 6
■
Networking
■
512-byte flash for storing configuration parameters
■
Enabling USB connectivity in legacy peripherals
■
Configuration utility (Windows) to configure the following:
❐ Vendor ID (VID), Product ID (PID), and Product and
Manufacturer descriptors
❐ SPI
❐ Charger detection
❐ GPIO
Functional Description
■
Driver support for VCOM and DLL
❐ Windows 10: 32- and 64-bit versions
❐ Windows 8.1: 32- and 64-bit versions
❐ Windows 8: 32- and 64-bit versions
❐ Windows 7: 32- and 64-bit versions
❐ Windows Vista: 32- and 64-bit versions
❐ Windows XP: 32- and 64-bit versions
❐ Mac OS-X: 10.6, 10.7
❐ Linux: Kernel version 2.6.35 onwards.
■
Clocking: Integrated 48-MHz clock oscillator
■
Supports bus-/self-powered configurations
■
USB Suspend mode for low power
■
Operating voltage: 1.71 to 5.5 V
■
Operating temperature
❐ Commercial: 0 °C to 70 °C
❐ Industrial: –40 °C to 85 °C
■
ESD protection: 2.2-kV HBM
■
RoHS-compliant package
❐ 24-pin QFN (4.0 mm × 4.0 mm, 0.55 mm, 0.5 mm pitch)
For a complete list of related resources, click here.
USB-Compliant
The USB-SPI Single Channel Bridge Controller is fully compliant with the USB 2.0 Specification and Battery
Charging Specification v1.2.
Cypress Semiconductor Corporation
Document Number: 002-31601 Rev. **
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 26, 2020
CY7C652148
USB Serial Bridge Controller Family
USB Serial bridge Controllers are a family of configurable products for most common applications requiring no firmware changes.
Configuration utility is provided to Configure USB-VID, USB-PID, USB Product and Manufacturer Descriptors. The same configuration
utility can be used to configure UART, I2C, SPI, Battery Charger Detection, GPIOs, Power mode, and so on.
Figure 1. USB Serial Bridge Controller Family
CY7C65211
24-QFN 10 GPIO
Configurable as:
USB-SPI
USB-I2C
USB-UART
H/W Flow Control
CY7C65223
24-QFN 4 GPIO
RS485 Support
S/W and H/W Flow
Control
Single Channel
CY7C65213A
32-QFN 8 GPIO
RS485 Support
S/W and H/W Flow
Control
CY7C652148
24-QFN
6 GPIO
CY7C65216
24-QFN
8 GPIO
CY7C65211A
24-QFN 10 GPIO
Configurable as:
USB-SPI
USB-I2C
USB-UART
H/W Flow Control
CY7C65213
32-QFN 8 GPIO
RS485 Support
H/W Flow Control
Dual Channel
CY7C65223D
32-QFN 4 GPIOs
RS485 Support
S/W and H/W Flow
Control
CY7C65214D
32-QFN
8 GPIO
CY7C65216D
32-QFN
12 GPIO
CY7C65215
32-QFN 17 GPIO*
Configurable as:
USB-SPI
USB-I2C
USB-UART
H/W Flow Control
CY7C65215A
32-QFN 17 GPIO*
Configurable as:
USB-SPI
USB-I2C
USB-UART
RS485 Support
H/W Flow Control
USB-UART
Bridge Controller
Document Number: 002-31601 Rev. **
USB-SPI
Bridge Controller
USB-I2C
Bridge Controller
USB-Serial Configurable
Bridge Controller
Page 2 of 32
CY7C652148
Table 1. USB Serial Family Feature Comparison
USB-SPI
USB-I2C
SPI Serial SPI Master/
Data
Slave
Width (bit)
I2C Master/
Slave
USB-UART
MPN
# of
Channels
GPIO
RS485
Support
CY7C65213
1
8
N
N
Y
8
–
–
–
CY7C65213A
1
8
Y
N
Y
8
–
–
–
CY7C65223
1
4
Y
Y
Y
2/4/6
–
–
–
CY7C65223D
2
4
Y
Y
Y
2/4/6/8
–
–
–
CY7C652148
1
6
–
–
–
–
4-16 bits Master/Slave
–
CY7C65214D
2
8
–
–
–
–
4-16 bits
Master/Slave
–
CY7C65216
1
8
–
–
–
–
–
–
Master/Slave
CY7C65216D
2
12
–
–
–
–
–
–
Master/Slave
CY7C65211
1
10*
N
N
Y
2/4/6
4-16 bits
Master/Slave Master/Slave
CY7C65211A
1
10*
Y
N
Y
2/4/6
4-16 bits
Master/Slave Master/Slave
CY7C65215
2
17*
N
N
Y
2/4/6
4-16 bits
Master/Slave Master/Slave
CY7C65215A
2
17*
Y
N
Y
2/4/6/8
4-16 bits
Master/Slave Master/Slave
Software Hardware
Flow
Flow
Control
Control
UART
Pins**
Legend
* Represents the total GPIO count offered by the part. This count can dynamically change based on UART / SPI / I2C pin configuration.
** UART Pins
**UART Pins
2
UART Signal
RxD and TxD
4
RxD, TxD, RTS#, CTS#
6
RxD, TxD, RTS#, CTS#, DTR#, DSR#
8
RxD, TxD, RTS#, CTS#, DTR#, DSR#, DCD#, RI#
Document Number: 002-31601 Rev. **
Page 3 of 32
CY7C652148
Table 2. Default Serial Channel Configuration
MPN
# of
Channels
GPIO
USB
Protocol
CY7C65213
1
4
CY7C65213A
1
CY7C65223
USB- UART
USB-SPI
USB-I2C
2
Is RS485
Enabled
UART Pins
SPI Master/
Slave
I C Master/
Slave
CDC**
N
8
–
–
4
CDC**
N
8
–
–
1
4
CDC**
Y
4
–
–
CY7C65223D
2
4
CDC**
Y
4
–
–
CY7C652148
1
6
Vendor***
–
–
Master
–
CY7C65214D
2
8
Vendor***
–
–
Master
–
CY7C65216
1
8
Vendor***
–
–
–
Slave
CY7C65216D
2
12
Vendor***
–
–
–
Master
CY7C65211
1
3
CDC**
N
6
–
–
CY7C65211A
1
3
CDC**
N
6
–
–
CY7C65215
2
4
CDC**
N
6
–
–
CY7C65215A
2
4
CDC**
N
6
–
–
** USB CDC Protocol allows the USB host Operating System to detect the device as Virtual COM Port Device.
*** USB Vendor Protocol allows the USB host operating system to detect the device as general USB device. This device is accessible using Cypress Application Library.
Document Number: 002-31601 Rev. **
Page 4 of 32
CY7C652148
More Information
Cypress provides a wealth of data at www.cypress.com to help you to select the right device for your design, and to help you to quickly
and effectively integrate the device into your design. For a comprehensive list of resources, see the document USB-Serial Bridge
Controller Product Overview.
■
Overview: USB Portfolio, USB Roadmap
For complete list of knowledge base articles, click here.
■
USB 2.0 Product Selectors: USB-Serial Bridge Controller, USB
to UART Controller (Gen I)
■
Code Examples: USB Full-Speed
Knowledge Base Articles: Cypress offers a large number of
USB knowledge base articles covering a broad range of topics,
from basic to advanced level. Recommended knowledge base
articles for getting started with USB-Serial Bridge Controller
are:
®
❐ KBA85909 – Key Features of the Cypress USB-Serial
Bridge Controller
❐ KBA85920 – USB-UART and USB-Serial
❐ KBA85921 – Replacing FT232R with CY7C65213
USB-UART LP Bridge Controller
❐ KBA85913 – Voltage supply range for USB-Serial
❐ KBA89355 – USB Serial Cypress Default VID and PID
❐ KBA92641 – USB-Serial Bridge Controller Managing I/Os
using API
❐ KBA92442 – Non-Standard Baud Rates in USB-Serial Bridge
Controllers
❐ KBA91366 – Binding a USB-Serial Device to a
Microsoft® CDC Driver
❐ KBA92551 – Testing a USB-Serial Bridge Controller
Configured as USB-UART with Linux®
2
❐ KBA91299 – Interfacing an External I C Device with the
CYUSBS234/236 DVK
■
■
Development Kits:
❐ CYUSBS232, Cypress USB-UART LP Reference Design Kit
❐ CYUSBS234, Cypress USB-Serial (Single Channel) Development Kit
❐ CYUSBS236, Cypress USB-Serial (Dual Channel) Development Kit
■
Models: IBIS
Document Number: 002-31601 Rev. **
Page 5 of 32
CY7C652148
Block Diagram
nXRES
VDDD
VCCD
Voltage
Regulator
Reset
Internal
48 MHz OSC
Internal
32 KHz OSC
USB
VBUS
BCD
USBDP
USBDM
256 Bytes TX
FIFO
VBUS Regulator
SPI
SPI
256 Bytes RX
FIFO
Battery Charger
Detection
USB
Transceiver with
Integrated
Resistor
Serial Communication Block
SIE
Document Number: 002-31601 Rev. **
512 Bytes
Flash
Memory
GPIO
GPIO
Page 6 of 32
CY7C652148
Contents
Functional Overview ........................................................ 8
USB and Charger Detect ............................................. 8
Serial Communication ................................................. 8
GPIO Interface ............................................................ 8
Default Configuration ................................................... 8
Memory ....................................................................... 8
System Resources ...................................................... 8
Suspend and Resume ................................................. 8
WAKEUP ..................................................................... 8
Software ...................................................................... 9
Internal Flash Configuration ........................................ 9
Electrical Specifications ................................................ 10
Absolute Maximum Ratings ....................................... 10
Operating Conditions ................................................. 10
Device-Level Specifications ...................................... 10
GPIO ......................................................................... 11
nXRES ....................................................................... 12
SPI Specifications ..................................................... 13
Flash Memory Specifications .................................... 15
Pin Description ............................................................... 16
Document Number: 002-31601 Rev. **
USB Power Configurations ............................................ 19
USB Bus-Powered Configuration .............................. 19
Self-Powered Configuration ...................................... 20
USB Bus-Powered with Variable I/O Voltage ............ 21
Application Examples .................................................... 22
Battery-Operated, Bus-Powered USB to MCU
with Battery Charge Detection .................................. 22
USB to SPI Bridge ..................................................... 24
Ordering Information ...................................................... 28
Ordering Code Definitions ......................................... 28
Package Information ...................................................... 29
Acronyms ........................................................................ 30
Document Conventions ................................................. 30
Units of Measure ....................................................... 30
Document History Page ................................................. 31
Sales, Solutions, and Legal Information ...................... 32
Worldwide Sales and Design Support ....................... 32
Products .................................................................... 32
PSoC® Solutions ....................................................... 32
Cypress Developer Community ................................. 32
Technical Support ..................................................... 32
Page 7 of 32
CY7C652148
Functional Overview
The CY7C652148 is a Full-Speed USB controller that enables
seamless PC connectivity for peripherals with serial interface.
CY7C652148 is BCD compliant with the USB Battery Charging
Specification, Rev. 1.2. It integrates a voltage regulator, an oscillator, and flash memory for storing configuration parameters,
offering a cost-effective solution. CY7C652148 supports
bus-powered and self-powered modes and enables efficient
system power management with suspend and remote wake-up
signals. It is available in a 24-pin QFN package.
USB and Charger Detect
USB
CY7C652148 has a built-in USB 2.0 Full-Speed transceiver. The
transceiver incorporates the internal USB series termination
resistors on the USB data lines and a 1.5-k pull-up resistor on
USBDP.
Charger Detection
CY7C652148 supports BCD for Peripheral Detect only and
complies with the USB Battery Charging Specification, Rev. 1.2.
It supports the following charging ports:
■ Standard Downstream Port (SDP): Allows the system to draw
up to 500 mA current from the host
■ Charging Downstream Port (CDP): Allows the system to draw
up to 1.5 A current from the host
■ Dedicated Charging Port (DCP): Allows the system to draw up
to 1.5 A of current from the wall charger
BCD0/BCD1: Two-pin output to indicate the type of USB
charger
■ BUSDETECT: Connects the VBUS pin for USB host detection
■
Default Configuration
SPI Master is the default configuration of CY7C652148.
CY7C652148 can be configured as USB to SPI slave bridge
using configuration utility.
Memory
CY7C652148 has a 512-byte flash. Flash is used to store USB
parameters, such as VID/PID, serial number, product and
manufacturer descriptors, which can be programmed by the
configuration utility.
System Resources
Power System
CY7C652148 supports the USB Suspend mode to control power
usage. CY7C652148 operates in bus-powered or self-powered
modes over a range of 3.15 to 5.5 V.
Clock System
CY7C652148 has a fully integrated clock with no external
components required. The clock system is responsible for
providing clocks to all subsystems.
Internal 48-MHz Oscillator
The internal 48-MHz oscillator is the primary source of internal
clocking in CY7C652148.
Serial Communication
Internal 32-kHz Oscillator
CY7C652148 has a serial communication block (SCB). Each
SCB can implement SPI interface. A 256-byte buffer is available
in both the TX and RX lines.
The internal 32-kHz oscillator is primarily used to generate
clocks for peripheral operation in the USB Suspend mode.
SPI Interface
The reset block ensures reliable power-on reset and brings the
device back to the default known state. The nXRES (active low)
pin can be used by the external devices to reset the
CY7C652148.
The SPI interface supports an SPI Master and SPI Slave. This
interface supports the Motorola, TI, and National Microwire
protocols. The maximum frequency of operation is 3 MHz in SPI
master mode and 1 MHz in SPI slave mode. It can support
transaction sizes ranging from 4 bits to 16 bits in length, SPI
slave supports 4 bits to 8 bits and 12 bits to 16 bits data width at
1 MHz operation. Whereas, it supports 9 bits,10 bits and 11 bits
data width operation at 500 kHz operation. (refer to USB to SPI
Bridge on page 24 for more details).
GPIO Interface
CY7C652148 has six GPIOs. The configuration utility allows
configuration of the GPIO pins. The configurable options are as
follows:
■
■
■
■
■
■
■
TRISTATE: GPIO can be tristated through Config Utility
DRIVE 1: Output static 1
DRIVE 0: Output static 0
POWER#: Power control for bus power designs
TXLED#: Drives LED during USB transmit
RXLED#: Drives LED during USB receive
TX or RX LED#: Drives LED during USB transmit or receive
GPIO can be configured to drive LED at 8-mA drive strength.
Document Number: 002-31601 Rev. **
Reset
Suspend and Resume
The CY7C652148 device asserts the SUSPEND pin when the
USB bus enters the suspend state. This helps in meeting the
stringent suspend current requirement of the USB 2.0 specification, while using the device in bus-powered mode. The device
resumes from the suspend state under either of the two following
conditions:
1. Any activity is detected on the USB bus
2. The WAKEUP pin is asserted to generate remote wakeup to
the host
WAKEUP
The WAKEUP pin is used to generate the remote wakeup signal
on the USB bus. The remote wakeup signal is sent only if the
host enables this feature through the SET_FEATURE request.
The device communicates support for the remote wakeup to the
host through the configuration descriptor during the USB
enumeration process. The CY7C652148 device allows
enabling/disabling and polarity of the remote wakeup feature
through the configuration utility.
Page 8 of 32
CY7C652148
Software
Device Configuration Utility (Windows only)
Cypress delivers a complete set of software drivers and a configuration utility to enable configuration of the product during
system development.
A Windows-based configuration utility is available to configure
device initialization parameters. This graphical user application
provides an interactive interface to define the boot parameters
stored in the device flash.
Drivers for Linux Operating Systems
This utility allows the user to save a user-selected configuration
to text or xml formats. It also allows users to load a selected
configuration from text or xml formats. The configuration utility
allows the following operations:
Cypress provides a User Mode USB driver library
(libcyusbserial.so) that abstracts vendor commands for the SPI
interface and provides a simplified API interface for user applications. This library uses the standard open-source libUSB library
to enable USB communication. The Cypress serial library
supports the USB plug-and-play feature using the Linux 'udev'
mechanism.
CY7C652148 binds to Linux USB Inbox driver.
Drivers for Mac OSx
Cypress delivers a dynamically linked shared library
(CyUSBSerial.dylib) based on libUSB, which enables communication to the CY7C652148 device.
In addition, CY7C652148 binds to Mac OSx native driver.
Drivers for Windows Operating Systems
For Windows operating systems (XP, Vista, Win 7, Win 8, Win
8.1, and Windows 10), Cypress delivers a user-mode dynamically linked library–CyUSBSerial DLL–that abstracts a
vendor-specific interface of the CY7C652148 devices and
provides convenient APIs to the user. It provides interface APIs
for vendor-specific SPI and class-specific APIs for PHDC.
■
View current device configuration
■
Select and configure SPI, battery charging, and GPIOs
■
Configure USB VID, PID, and string descriptors
■
Save or Load configuration
You can download the free configuration utility and drivers at
www.cypress.com.
Internal Flash Configuration
The internal flash memory can be used to store the configuration
parameters shown in the following table. A free configuration
utility is provided to configure the parameters listed in the table
to meet application-specific requirements over the USB
interface. The configuration utility can be downloaded at
www.cypress.com/usbserial.
USB-SPI Bridge Controller works with Cypress provided USB
vendor class driver. The Cypress Windows drivers are MS logo
certified drivers.
These drivers are bound to device through WU (Windows
Update) services.
Cypress drivers also support Windows plug-and-play and power
management and USB Remote Wake-up.
Table 3. Internal Flash Configuration for CY7C652148
Parameter
Default Value
Description
USB Configuration
USB Vendor ID (VID)
0x04B4
Default Cypress VID. Can be configured to customer VID.
USB Product ID (PID)
0x0004
Default Cypress PID. Can be configured to customer PID.
Manufacturer string
Cypress
Can be configured with any string up-to 64 characters
Product string
USB-Serial (Single Channel) Can be configured with any string up-to 64 characters
Serial string
Power mode
Can be configured with any string up-to 64 characters
Bus powered
Can be configured to bus-powered or self-powered mode
Max current draw
100 mA
Can be configured to any value from 0 to 500 mA. The configuration
descriptor will be updated based on this.
Remote wakeup
Enabled
Can be disabled. Remote wakeup is initiated by asserting the WAKEUP pin.
USB interface protocol
Vendor
Can be configured to function in CDC, PHDC, or Cypress vendor class
BCD
Disabled
Document Number: 002-31601 Rev. **
Charger detect is disabled by default. When BCD is enabled, three of the
GPIOs must be configured for BCD.
Page 9 of 32
CY7C652148
Electrical Specifications
Absolute Maximum Ratings
Exceeding maximum ratings[1] may shorten the useful life of the
device.
Storage temperature ............................... –55 °C to +100 °C
Ambient temperature with
power supplied (Industrial) ....................... –40 °C to +85 °C
Supply voltage to ground potential
VDDD ............................................................................ 6.0 V
VBUS ............................................................................ 6.0 V
VCCD .......................................................................... 1.95 V
VGPIO .............................................................. VDDD + 0.5 V
Static discharge voltage ESD protection levels:
■
2.2-KV HBM per JESD22-A114
Latch-up current ....................................................................
140 mA
Current per GPIO ..................................................................
25 mA
Operating Conditions
TA (ambient temperature under bias)
Industrial ..........................................................–40 °C to +85 °C
VBUS supply voltage .... .......................................... 3.15 V to
5.25 V
VDDD supply voltage .... .......................................... 1.71 V to
5.50 V
VCCD supply voltage .... .......................................... 1.71 V to
1.89 V
Device-Level Specifications
All specifications are valid for –40 °C TA 85 °C, TJ 100 °C, and 1.71 V to 5.50 V, except where noted.
Table 4. DC Specifications
Parameter
VBUS
VDDD
VCCD
Description
VBUS supply voltage
VDDD supply voltage
Output voltage (for core logic)
Cefc
External regulator voltage bypass
IDD1
Operating supply current
IDD2
USB Suspend supply current
Min
Typ
Max
Units
Details/Conditions
3.15
3.30
3.45
V
4.35
5.00
5.25
V
Set and configure the correct voltage
range using a configuration utility for
VBUS. Default 5 V.
1.71
1.80
1.89
V
2.0
3.3
5.5
V
Used to set I/O and core voltage. Set
and configure the correct voltage
range using a configuration utility for
VDDD. Default 3.3 V.
V
Do not use this supply to drive the
external device.
• 1.71 V VDDD 1.89 V: Short
the VCCD pin with the VDDD pin
• VDDD > 2 V – connect a 1-µF
capacitor (Cefc) between the
VCCD pin and ground
1.60
µF
X5R ceramic or better
–
mA
USB 2.0 FS, no GPIO switching.
Does not include current through a
pull-up resistor on USBDP.
In USB suspend mode, the D+
voltage can go up to a maximum of
3.8 V.
–
1.80
–
1.00
1.30
–
20
–
5
–
µA
Min
Typ
Max
Units
Table 5. AC Specifications
Parameter
Description
Details/Conditions
Zout
USB driver output impedance
28
–
44
–
Twakeup
Wakeup from USB Suspend mode
–
25
–
µs
–
Note
1. Usage above the Absolute Maximum conditions may cause permanent damage to the device. Exposure to Absolute Maximum conditions for extended periods of
time may affect device reliability. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification.
Document Number: 002-31601 Rev. **
Page 10 of 32
CY7C652148
GPIO
Table 6. GPIO DC Specifications
Parameter
Min
Typ
Input voltage high threshold
0.7 × VDDD
–
–
V
CMOS Input
Input voltage low threshold
–
–
0.3 × VDDD
V
CMOS Input
VIH[2]
LVTTL input, VDDD< 2.7 V
0.7 × VDDD
–
–
V
–
VIH[2]
VIL
Description
Max
Units
Details/Conditions
VIL
LVTTL input, VDDD < 2.7V
–
–
0.3 × VDDD
V
–
VIH[2]
LVTTL input, VDDD > 2.7V
2
–
–
V
–
VIL
LVTTL input, VDDD > 2.7V
–
–
0.8
V
–
VOH
CMOS output voltage high level
VDDD – 0.4
–
–
V
IOH = 4 mA,
VDDD = 5 V +/- 10%
VOH
CMOS output voltage high level
VDDD – 0.6
–
–
V
IOH = 4 mA,
VDDD = 3.3 V +/- 10%
VOH
CMOS output voltage high level
VDDD – 0.5
–
–
V
IOH = 1 mA,
VDDD = 1.8 V +/- 5%
VOL
CMOS output voltage low level
–
–
0.4
V
IOL = 8 mA,
VDDD = 5 V +/- 10%
VOL
CMOS output voltage low level
–
–
0.6
V
IOL = 8 mA,
VDDD = 3.3 V +/- 10%
VOL
CMOS output voltage low level
–
–
0.6
V
IOL = 4 mA,
VDDD = 1.8 V +/- 5%
Rpullup
Pull-up resistor
3.5
5.6
8.5
kΩ
–
Rpulldown
Pull-down resistor
3.5
5.6
8.5
kΩ
–
IIL
Input leakage current (absolute value)
–
–
2
nA
25 °C, VDDD = 3.0 V
CIN
Input capacitance
–
–
7
pF
–
Vhysttl
Input hysteresis LVTTL; VDDD > 2.7 V
Vhyscmos
Input hysteresis CMOS
25
40
C
mV
–
0.05 × VDDD
–
–
mV
–
Min
Typ
Max
Units
Table 7. GPIO AC Specifications
Parameter
Description
Details/Conditions
TRiseFast1
Rise Time in Fast mode
2
–
12
ns
VDDD = 3.3 V/ 5.5 V,
Cload = 25 pF
TFallFast1
Fall Time in Fast mode
2
–
12
ns
VDDD = 3.3 V/ 5.5 V,
Cload = 25 pF
TRiseSlow1
Rise Time in Slow mode
10
–
60
ns
VDDD = 3.3 V/ 5.5 V,
Cload = 25 pF
TFallSlow1
Fall Time in Slow mode
10
–
60
ns
VDDD = 3.3 V/ 5.5 V,
Cload = 25 pF
TRiseFast2
Rise Time in Fast mode
2
–
20
ns
VDDD = 1.8 V, Cload = 25 pF
TFallFast2
Fall Time in Fast mode
20
–
100
ns
VDDD = 1.8 V, Cload = 25 pF
TRiseSlow2
Rise Time in Slow mode
2
–
20
ns
VDDD = 1.8 V, Cload = 25 pF
TFallSlow2
Fall Time in Slow mode
20
–
100
ns
VDDD = 1.8 V, Cload = 25 pF
Note
2. VIH must not exceed VDDD + 0.2 V.
Document Number: 002-31601 Rev. **
Page 11 of 32
CY7C652148
nXRES
Table 8. nXRES DC Specifications
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
VIH
Input voltage high threshold
0.7 × VDDD
–
–
V
–
VIL
Input voltage low threshold
–
–
0.3 × VDDD
V
–
Rpullup
Pull-up resistor
3.5
5.6
8.5
kΩ
–
CIN
Input capacitance
–
5
–
pF
–
Vhysxres
Input voltage hysteresis
–
100
–
mV
–
Min
Typ
Max
Units
1
–
–
µs
Table 9. nXRES AC Specifications
Parameter
Tresetwidth
Description
Reset pulse width
Document Number: 002-31601 Rev. **
Details/Conditions
–
Page 12 of 32
CY7C652148
SPI Specifications
Figure 2. SPI Master Timing
FSPI
SCK
(CPOL=0,
Output)
SCK
(CPOL=1,
Output)
TDSI
MISO
(input)
MSB
LSB
TDMO
MOSI
(output)
THMO
MSB
LSB
SPI Master Timing for CPHA = 0 (Refer to Table 10)
FSPI
SCK
(CPOL=0,
Output)
SCK
(CPOL=1,
Output)
TDSI
MISO
(input)
LSB
TDMO
MOSI
(output)
MSB
THMO
LSB
MSB
SPI Master Timing for CPHA = 1 (Refer to Table 10)
Document Number: 002-31601 Rev. **
Page 13 of 32
CY7C652148
Figure 3. SPI Slave Timing
SSN
(Input)
SCK
(CPOL=0,
Input)
FSPI
TSSELSCK
SCK
(CPOL=1,
Input)
TDSO
MISO
(Output)
THSO
LSB
MSB
LSB
MSB
TDMI
MOSI
(Input)
SPI Slave Timing for CPHA = 0 (Refer to Table 10)
SSN
(Input)
FSPI
SCK
(CPOL=0,
Input)
TSSELSCK
SCK
(CPOL=1,
Input)
TDSO
MISO
(Ouput)
THSO
LSB
MSB
LSB
MSB
TDMI
MOSI
(Input)
SPI Slave Timing for CPHA = 1 (Refer to Table 10)
Document Number: 002-31601 Rev. **
Page 14 of 32
CY7C652148
Table 10. SPI AC Specifications
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
FSPI
SPI operating frequency
(Master/Slave)
–
–
3
MHz
–
WLSPI
SPI word length
4
–
16
bits
–
SPI Master Mode
–
TDMO
MOSI valid after SClock driving
edge
–
–
15
ns
–
TDSI
MISO valid before SClock
capturing edge
20
–
–
ns
–
THMO
Previous MOSI data hold time with
respect to capturing edge at slave
0
–
–
ns
–
SPI Slave Mode
–
TDMI
MOSI valid before Sclock
Capturing edge
40
–
–
ns
–
TDSO
MISO valid after Sclock driving
edge
–
–
104.4
ns
–
THSO
Previous MISO data hold time
TSSELSCK
SSEL valid to first SCK Valid edge
0
–
–
ns
–
100
–
–
ns
–
Flash Memory Specifications
Table 11. Flash Memory Specifications
Parameter
Description
Fend
Flash endurance
Fret
Flash retention. TA 85 °C,
10 K program/erase cycles
Document Number: 002-31601 Rev. **
Min
Typ
Max
Units
100K
–
–
cycles
–
Details/Conditions
10
–
–
years
–
Page 15 of 32
CY7C652148
Pin Description
Pin[3]
Type
Name
Default
1
GPIO
GPIO_6
GPIO IN
GPIO Input Pin (see Table 13)
2
GPIO
GPIO_7
GPIO IN
GPIO Input Pin (see Table 13)
3
Power
4
GPIO
GPIO_8
GPIO IN
GPIO Input Pin (see Table 13)
5
GPIO
GPIO_9
GPIO OUT
GPIO Output Pin (see Table 13)
6
GPIO
GPIO_10
GPIO OUT
GPIO Output Pin (see Table 13)
7
Output
POWER#
Signal to external logic to indicate
USB Unconfigured state and USB Suspend
8
Output
Suspend
Asserted when the part enters Low Power mode
9
Input
Wakeup
Wakeup device from suspend mode. Can be configured as active high/low
using configuration utility.
10
USBIO
USBDP
USB D+
VSSD
Description
Digital Ground
11
USBIO
USBDM
12
Power
VCCD
VCCD (Internal LDO Output)
13
Power
VSSD
Digital Ground
14
Reset
nXRES
Chip Reset active, low. Can be left unconnected or have a pull up resistor
connected when not in use.
15
Power
VBUS
USB VBUS
16
Power
VSSD (VBUS)
Digital Ground
17
Power
VSSA
Analog Ground
18
GPIO
TX_RX_LED
19
GPIO
20
SCB/GPIO
SSEL_OUT
21
SCB/GPIO
MISO
SPI Master IN Slave OUT
GPIO_1
GPIO IN
USB D-
Notification LED for SPI Tx/Rx Data
GPIO Input Pin (see Table 13)
Slave Select
22
SCB/GPIO
MOSI
SPI Master Out Slave IN
23
SCB/GPIO
SCLK
SPI Clock
24
Power
VDDD
VDDD Core
Note
3. Any pin acting as an Input pin should not be left unconnected.
Document Number: 002-31601 Rev. **
Page 16 of 32
CY7C652148
VDDD
SCLK
MOSI
MISO
SSEL_OUT
GPIO_1
24
23
22
21
20
19
Figure 4. 24-pin QFN Pinout
GPIO_6
1
18
TX_RX_LED
GPIO_7
2
17
VSSA
VSSD
3
16
VSSD
GPIO_8
4
15
VBUS
GPIO_9
5
14
nXRES
GPIO_10
6
13
VSSD
7
8
9
10
11
12
POWER#
SUSPEND
WAKEUP
USBDP
USBDM
VCCD
CY7C652148-24QFN
Top View
Table 12. Serial Communication Block Configurations
Mode 0[4]
Mode 1
SPI Master
SPI Slave
GPIO_6
SSEL_OUT
GPIO_6
SSEL_IN
SCB_2
MISO_IN
MISO_OUT
SCB_3
MOSI_OUT
MOSI_IN
23
SCB_4
SCLK_OUT
SCLK_IN
2
SCB_5
GPIO_7
GPIO_7
Pin
Serial Port
1
SCB_0
20
SCB_1
21
22
Note
4. The device is configured in Mode 0 as the default. Other modes can be configured using the configuration utility provided by Cypress.
Legend
GPIO
SCB
Document Number: 002-31601 Rev. **
Page 17 of 32
CY7C652148
Table 13. GPIO Configuration[5]
GPIO Configuration Option
TRISTATE
Description
I/O tristated
DRIVE 1
Output static 1
DRIVE 0
Output static 0
POWER#
This output is used to control power to an external logic through a switch to cut power off during an
unconfigured USB device and USB suspend.
0 - USB device in Configured state
1 - USB device in Unconfigured state or during USB suspend mode
TXLED#
Drives LED during USB transmit
RXLED#
Drives LED during USB receive
TX or RX LED#
BCD0
BCD1
BUSDETECT
Drives LED during USB transmit or receive
Configurable battery charger detect pins to indicate the type of USB charger (SDP, CDP, or DCP)
Configuration example:
00 - Draw up to 100 mA (unconfigured state)
01 - SDP (up to 500 mA)
10 - CDP/DCP (up to 1.5 A)
11 - Suspend (up to 2.5 mA)
This truth table can be configured using a configuration utility
VBUS detection. Connect the VBUS to this pin through a resistor network for VBUS detection when
using the BCD feature (refer to Figure 9, Figure 10, and Figure 11).
Note
5. These signal options can be configured on any of the available GPIO pins using the configuration utility provided by Cypress.
Document Number: 002-31601 Rev. **
Page 18 of 32
CY7C652148
USB Power Configurations
The following section describes possible USB power configurations for the CY7C652148. Refer to the Pin Description on page
16 for signal details.
USB Bus-Powered Configuration
Figure 5 shows an example of the CY7C652148 in a
bus-powered design. The VBUS is connected directly to the
CY7C652148 because it has an internal regulator.
The USB bus-powered system must comply with the following
requirements:
1. The system should not draw more than 100 mA prior to USB
enumeration (Unconfigured state).
2. The system should not draw more than 2.5 mA during the USB
Suspend mode.
3. A high-power bus-powered system (can draw more than
100 mA when operational) must use POWER# (configured
over GPIO) to keep the current consumption below 100 mA
prior to USB enumeration, and 2.5 mA during USB Suspend
state.
4. The system should not draw more than 500 mA from the USB
host.
The configuration descriptor in the CY7C652148 flash should be
updated to indicate bus power and the maximum current
required by the system using the configuration utility.
Figure 5. Bus-Powered Configuration
CY7C652148
18 TX_RX_LED
19 GPIO_1
20 SSEL_OUT
VDDD
21 MISO
22 MOSI
VBUS
23 SCLK
USBDP
USBDM
1 GPIO_6
24
USB
CONNECTOR
15
10
VBUS
D+
DGND
11
2 GPIO_7
4.7 uF
4 GPIO_8
0.1 uF
5 GPIO_9
6 GPIO_10
XRES
7 POWER#
8 SUSPEND
VSSD
VSSD
VSSD
VSSA
9 WAKEUP
VCCD
14
12
1 uF
17 16 13 3
Document Number: 002-31601 Rev. **
Page 19 of 32
CY7C652148
Self-Powered Configuration
When reset is asserted to CY7C652148, all the I/O pins are
tristated.
The configuration descriptor in the CY7C652148 flash should be
updated to indicate self-power using the configuration utility.
Figure 6 shows an example of CY7C652148 in a self-powered
design. A self-powered system does not use the VBUS from the
host to power the system, but it has its own power supply. A
self-powered system has no restriction on current consumption
because it does not draw any current from the VBUS.
When the VBUS is present, CY7C652148 enables an internal,
1.5-k pull-up resistor on USBDP. When the VBUS is absent
(USB host is powered down), CY7C652148 removes the 1.5-k
pull-up resistor on USBDP. This ensures that no current flows
from the USBDP to the USB host through a 1.5-k pull-up
resistor, to comply with the USB 2.0 specification.
Figure 6. Self-Powered Configuration
3.3 V
3.3 V
CY7C652148
18 TX_RX_LED
19 GPIO_1
20 SSEL_OUT
VDDD
21 MISO
22 MOSI
VBUS
USBDP
USBDM
23 SCLK
1 GPIO_6
2 GPIO_7
24
USB
CONNECTOR
15
10
VBUS
D+
DGND
11
4 GPIO_8
4.7 uF
5 GPIO_9
6 GPIO_10
7 POWER#
XRES
14
0.1 uF
4.7 KΩ
10 KΩ
8 SUSPEND
VSSD
VSSD
VSSD
VCCD
VSSA
9 WAKEUP
12
1 uF
17 16 13 3
Document Number: 002-31601 Rev. **
Page 20 of 32
CY7C652148
USB Bus-Powered with Variable I/O Voltage
Figure 7 shows CY7C652148 in a bus-powered system with
variable I/O voltage. A low dropout (LDO) regulator is used to
supply 1.8 V or 3.3 V, using a jumper switch the input of which is
5 V from the VBUS. Another jumper switch is used to select
1.8/3.3 V or 5 V from the VBUS for the VDDD pin of
CY7C652148. This allows I/O voltage and supply to external
logic to be selected among 1.8 V, 3.3 V, or 5 V.
The USB bus-powered system must comply with the following
conditions:
■
The system should not draw more than 100 mA prior to USB
enumeration (unconfigured state)
■
The system should not draw more than 2.5 mA during USB
Suspend mode
■
A high-power bus-powered system (can draw more than 100
mA when operational) must use POWER# (configured over
GPIO) to keep the current consumption below 100 mA prior to
USB enumeration and 2.5 mA during the USB Suspend state
Figure 7. USB Bus-Powered with 1.8-V, 3.3-V, or 5-V Variable I/O Voltage[6]
1.8 V or 3.3 V or 5 V
Supply to External Logic
Power
Switch
CY7C652148
1.8/3.3 V
18 TX_RX_LED
19 GPIO_1
20 SSEL_OUT
VDDD
21 MISO
22 MOSI
VBUS
23 SCLK
USBDP
USBDM
1 GPIO_6
2 GPIO_7
1
2
3
24
Jumper to select
1.8 V/3.3 V or 5 V
15
10
11
4.7 uF
4 GPIO_8
VBUS
USB
D+
CONNECTOR
DGND
0.1uF
5 GPIO_9
6 GPIO_10
9 WAKEUP
VSSD
VCCD
VSSD
8 SUSPEND
VSSA
nXRES
VSSD
7 POWER#
14
VBUS
12
1 uF
TC 1070
1.8/3.3 V
Vout
17 16 13 3
Vin
SHDn
Vadj
1uF 1M
0.1 uF
GND
123
3.3 V
562K
1.8 V
2M
Jumper to select
1.8 V or 3.3 V
Note
6. 1.71 V VDDD 1.89 V - Short VCCD pin with VDDD pin; VDDD > 2 V - connect a 1-µF decoupling capacitor to the VCCD pin.
Document Number: 002-31601 Rev. **
Page 21 of 32
CY7C652148
Application Examples
The following section provides CY7C652148 application
examples.
Battery-Operated, Bus-Powered USB to MCU with
Battery Charge Detection
Figure 8 illustrates CY7C652148 as a USB-to-microcontroller
interface. The TXD and RXD lines are used for data transfer, and
the RTS# and CTS# lines are used for handshaking. The
SUSPEND pin indicates to the MCU if the device is in USB
Suspend, and the WAKEUP pin is used to wake up
CY7C652148, which in turn issues a remote wakeup to the USB
host.
This application illustrates a battery-operated system, which is
bus-powered. CY7C652148 implements the battery charger
detection functionality based on the USB Battery Charging
Specification, Rev. 1.2.
Battery-operated bus power systems must comply with the
following conditions:
■
The system can be powered from the battery (if not discharged)
and can be operational if the VBUS is not connected or powered
down.
■
The system should not draw more than 100 mA from the VBUS
prior to USB enumeration and USB Suspend.
■
The system should not draw more than 500 mA for SDP and
1.5 A for CDP/DCP
To comply with the first requirement, the VBUS from the USB
host is connected to the battery charger as well as to
CY7C652148, as shown in Figure 8. When the VBUS is
connected, CY7C652148 initiates battery charger detection and
indicates the type of USB charger over BCD0 and BCD1. If the
USB charger is SDP or CDP, CY7C652148 enables a 1.5-K
pull-up resistor on the USBDP for Full-Speed enumeration.
When the VBUS is disconnected, CY7C652148 indicates an
absence of the USB charger over BCD0 and BCD1, and
removes the 1.5-K pull-up resistor on USBDP. Removing this
resistor ensures that no current flows from the supply to the USB
host through the USBDP, to comply with the USB 2.0 specification.
To comply with the second and third requirements, two signals
(BCD0 and BCD1) are configured over GPIO to communicate
the type of USB host charger and the amount of current it can
draw from the battery charger. BCD0 and BCD1 signals can be
configured using the configuration utility.
Figure 8. USB to MCU Interface with Battery Charge Detection[7, 8, 9]
VDDD
VCC
CY7C652148
10K
SSEL
MISO
VDDD
20
21
MOSI
MCU
SCLK
22
23
SSEL_OUT
10K
MISO
GPIO_9
GPIO_10
MOSI
nXRES
SCLK
GPIO_9
VSSD
VSSD
GND
8 SUSPEND
9 WAKEUP
VSSA
I/O
VBUS
USBDP
USBDM
VSSD
I/O
24
VCCD
10K
5
BCD0
EN1
6
BCD1
EN2
14
3
Battery
Charger
(MAX8856)
IN
SYS
BAT +
-
BUSDETECT
15
10
11
OVP
12
VBUS
USB
D+
CONNECTOR
DGND
0.1 uF
1 uF
17 16 13 3
VBUS
4.7 uF
0.1 uF
Notes
7. Add a 100-k pull-down resistor on the VBUS pin for quick discharge.
8. Refer Figure 9, Figure 10, Figure 11 and the corresponding descriptions for handling VBUS Over Voltage Protection (OVP).
9. BCD and BUSDETECT functionality are not enabled by default. USB-Serial Configuration Utility is provided to enable BCD and BUSDETECT functionality.
Document Number: 002-31601 Rev. **
Page 22 of 32
CY7C652148
In a battery charger system, a 9-V spike on the VBUS is possible. The CY7C652148 VBUS pin is intolerant to voltage above 6 V. In
the absence of over-voltage protection (OVP) on the VBUS line, the VBUS should be connected to BUSDETECT (GPIO configured)
using the resistive network and the output of the battery charger to the VBUS pin of CY7C652148, as shown in Figure 9.
Figure 9. 9 V Tolerant
A
Rs
B
VBUS
VBUS = VDDD
SYS
Battery Charger
CY7C652148
GPIO
BUSDETECT
A
BAT
Figure 10. GPIO VBUS Detection, VBUS = VDDD
VDDD
CY7C652148
BUSDETECT
Rs
VBUS
R1
A
+
B
-
R2
VBUS
VBUS > VDDD
B
When the VBUS and VDDD are at the same voltage potential,
the VBUS can be connected to the GPIO using a series resistor
(Rs). This is shown in the following figure. If there is a charger
failure and the VBUS becomes 9 V, then the 10-k resistor plays
two roles. It reduces the amount of current flowing into the
forward-biased diodes in the GPIO, and it reduces the voltage
seen on the pad.
Rs = 10 K
R1 ≥ 10 kΩ
R2/(R1+R2) = VDDD/VBUS
When the VBUS > VDDD, a resistor voltage divider is required
to reduce the voltage from the VBUS down to VDDD for the GPIO
sensing the VBUS voltage. This is shown in the following figure.
The resistors should be sized as follows:
R1 >= 10 k
R2 / (R1 + R2) = VDDD / VBUS
The first condition limits the voltage and current for the charger
failure situation, as described in the previous paragraph, while
the second condition allows for normal-operation VBUS
detection.
Figure 11. GPIO VBUS Detection, VBUS > VDDD
VDDD
CY7C652148
BUSDETECT
R1
VBUS
R2
Document Number: 002-31601 Rev. **
Page 23 of 32
CY7C652148
USB to SPI Bridge
In the master mode, the SCLK, MOSI, and SSEL lines act as
outputs and MISO acts as an input. In the slave mode, the SCL
SCLK, MOSI, and SSEL lines act as inputs and MISO acts as an
output.
GPIO8 and GPIO9 are configured as RXLED# and TXLED# to
drive two LEDs to indicate USB receive and transmit.
In Figure 12, CY7C652148 is configured as a USB to SPI Bridge.
The CY7C652148 SPI can be configured as a master or a slave
using the configuration utility. CY7C652148 supports SPI master
frequency up to 3 MHz and SPI slave frequency up to 1 MHz. It
can support transaction sizes ranging from 4 bits to 16 bits,
which can be configured using the configuration utility.
Figure 12. USB to SPI Bridge
1.8/3.3 V
VDDD
CY7C652148
10K
20
VCC
21
SPI
Slave
22
23
GND
VDDD
1
2
3
24
SSEL_OUT
MISO
VBUS
USBDP
MOSI
SCLK
USBDM
Jumper to select
1.8 V/3.3 V or 5 V
15
10
VBUS
D+
DGND
11
USB
CONNECTOR
0.1 uF
XRES
VSSD
VSSD
12
1 uF
17 16 13 3
TC 1070
1.8/3.3 V
Vout
Vadj
1M
VBUS
VDDD
Vin
SHDn
1uF
VSSA
VBUS
VSSD
VCCD
14
0.1 uF
4.7 uF
GND
0.1 uF
4.7 uF
0.1 uF
123
3.3 V
562K
1.8 V
2M
Jumper to select
1.8 V or 3.3 V
CY7C652148 supports three versions of the SPI protocol:
■
Motorola - This is the original SPI protocol.
■
Texas Instruments - A variation of the original SPI protocol in
which the data frames are identified by a pulse on the SSEL line.
National Semiconductors - A half-duplex variation of the
original SPI protocol.
Motorola
The original SPI protocol is defined by Motorola. It is a full-duplex
protocol: transmission and reception occur at the same time.
A single (full-duplex) data transfer follows these steps: The
master selects a slave by driving its SSEL line to '0'. Next, it
drives the data on its MOSI line and it drives a clock on its SCLK
line. The slave uses the edges of the transmitted clock to capture
the data on the MOSI line. The slave drives data on its MISO line.
The master captures the data on the MISO line. Repeat the
process for all bits in the data transfer.
■
Document Number: 002-31601 Rev. **
Multiple data transfers may happen without the SSEL line
changing from '0' to '1' and back from '1' to '0' in between the
individual transfers. As a result, slaves must keep track of the
progress of data transfers to separate individual transfers.
When not transmitting data, the SSEL line is '1' and the SCLK is
typically off.
The Motorola SPI protocol has four modes that determine how
data is driven and captured on the MOSI and MISO lines. These
modes are determined by clock polarity (CPOL) and clock phase
(CPHA). Clock polarity determines the value of the SCLK line
when not transmitting data:
■
CPOL is '0': SCLK is '0' when not transmitting data.
CPOL is '1': SCLK is '1' when not transmitting data.
The clock phase determines when data is driven and captured.
It is dependent on the value of CPOL.
■
Page 24 of 32
CY7C652148
Table 14. SPI Protocol Modes
Mode
CPOL
CPHA
Description
0
0
0
Data is driven on a falling edge of SCLK. Data is captured on a rising edge of SCLK.
1
0
1
Data is driven on a rising edge of SCLK. Data is captured on a falling edge of SCLK.
2
1
0
Data is driven on a rising edge of SCLK. Data is captured on a falling edge of SCLK.
3
1
1
Data is driven on a falling edge of SCLK. Data is captured on a rising edge of SCLK.
Figure 13. Driving and Capturing MOSI/MISO Data As A Function of CPOL and CPHA
CPOL: ‘0’, CPHA: ‘0’
SCLK
MOSI/MISO
MSB
LSB
CPOL: ‘0’, CPHA: ‘1’
SCLK
MOSI/MISO
LSB
MSB
CPOL: ‘1’, CPHA: ‘0’
SCLK
MOSI/MISO
MSB
LSB
CPOL: ‘1’, CPHA: ‘0’
SCLK
MOSI/MISO
MSB
LEGEND:
CPOL:
CPHA:
SCLK:
MOSI:
MISO:
LSB
Clock Polarity
Clock Phase
SPI interface clock
SPI Master Out / Slave In
SPI Master In / Slave Out
Figure 14. Single 8-bit Data Transfer and Two Successive 8-bit Data Transfers in Mode 0 (CPOL is ‘0’, CPHA is ‘0’)
CPOL: ‘0’, CPHA: ‘0’, single data transfer
SCLK
SSEL
MOSI
MSB
MISO
MSB
LSB
LSB
CPOL: ‘0’, CPHA: ‘0’, two successive data transfers
SCLK
SSEL
MOSI
MSB
LSB MSB
LSB
MISO
MSB
LSB MSB
LSB
LEGEND:
CPOL:
CPHA:
SCLK:
SSEL:
MOSI:
MISO:
Document Number: 002-31601 Rev. **
Clock Polarity
Clock Phase
SPI interface clock
SPI slave select
SPI Master Out / Slave In
SPI Master In / Slave Out
Page 25 of 32
CY7C652148
Texas Instruments
Texas Instruments' SPI protocol redefines the use of the SSEL
signal. It uses the signal to indicate the start of a data transfer,
rather than a low, active slave-select signal. The start of a
transfer is indicated by a high, active pulse of a single-bit transfer
period. This pulse may occur one cycle before the transmission
of the first data bit, or it may coincide with the transmission of the
first data bit. The transmitted clock SCLK is a free-running clock.
The TI SPI protocol only supports mode 1 (CPOL is ‘0’ and CPHA
is ‘1’): Data is driven on a rising edge of SCLK and data is
captured on a falling edge of SCLK.
The following figure illustrates a single 8-bit data transfer and two
successive 8-bit data transfers. The SSEL pulse precedes the
first data bit. Note how the SSEL pulse of the second data
transfer coincides with the last data bit of the first data transfer.
Single data transfer
SCLK
SSEL
MOSI
MSB
LSB
MISO
MSB
LSB
Two successive data transfers
SCLK
SSEL
MOSI
MSB
LSB MSB
LSB
MISO
MSB
LSB MSB
LSB
LEGEND:
SCLK:
SSEL:
MOSI:
MISO:
SPI interface clock
SPI slave select pulse
SPI Master Out / Slave In
SPI Master In / Slave Out
The following figure illustrates a single 8-bit data transfer and two successive 8-bit data transfers. The SSEL pulse coincides with the
first data bit.
Single data transfer
SCLK
SSEL
MOSI
MSB
LSB
MISO
MSB
LSB
Two successive data transfers
SCLK
SSEL
MOSI
MSB
LSB MSB
LSB
MISO
MSB
LSB MSB
LSB
LEGEND:
SCLK:
SSEL:
MOSI:
MISO:
Document Number: 002-31601 Rev. **
SPI interface clock
SPI slave select pulse
SPI Master Out / Slave In
SPI Master In / Slave Out
Page 26 of 32
CY7C652148
National Semiconductor
National Semiconductor’s SPI protocol is a half-duplex protocol.
Rather than transmission and reception occurring at the same
time, they take turns (transmission happens before reception). A
single “idle” bit transfer period separates transmission from
reception.
Note Successive data transfers are NOT separated by an “idle”
bit transfer period.
The transmission data transfer size and reception data transfer
size may differ. National Semiconductor’s SPI protocol supports
only mode 0: Data is driven on a falling edge of SCLK, and data
is captured on a rising edge of SCLK.
The following figure illustrates a single data transfer and two
successive data transfers. In both cases, the transmission data
transfer size is 8 bits and the reception transfer size is 4 bits.
Single data transfer
SCLK
SSEL
MOSI
MSB
LSB
MISO
MSB
LSB
“idle” ‘0’ cycle
Two successive data transfers
SCLK
SSEL
MOSI
MSB
LSB
MISO
MSB
MSB
“idle” ‘0’ cycle
LEGEND:
SCLK:
SSEL:
MOSI:
MISO:
LSB
no “idle” cycle
SPI interface clock
SPI slave select
SPI Master Out / Slave In
SPI Master In / Slave Out
Note The above figure defines MISO and MOSI as undefined when the lines are considered idle (not carrying valid information). It
will drive the outgoing line values to '0' during idle time (to satisfy the requirements of specific master devices (NXP LPC17xx) and
specific slave devices (Microchip EEPROM).
Document Number: 002-31601 Rev. **
Page 27 of 32
CY7C652148
Ordering Information
Table 15 lists the key package features and ordering codes of the CY7C652148. For more information, contact your local sales
representative.
Table 15. Key Features and Ordering Information
Package
24-pin QFN (4.00 × 4.00 × 0.55 mm, 0.5 mm pitch) (Pb-free)
24-pin QFN (4.00 × 4.00 × 0.55 mm, 0.5 mm pitch) (Pb-free) – Tape and
Reel
Ordering Code
Operating Range
CY7C652148-24LTXI
Industrial
CY7C652148-24LTXIT
Industrial
Ordering Code Definitions
CY 7
C
65 XXXX - 24
XX X
I
X
X = blank or T
blank = Tray; T = Tape and Reel
Temperature Range:
I = Industrial
Pb-free
Package Type:
LT = QFN
Number of pins: 24 pins
Part Number: XXXX = 2148
Family Code:
65 = USB Hubs
Technology Code: C = CMOS
Marketing Code: 7 = Cypress products
Company ID: CY = Cypress
Document Number: 002-31601 Rev. **
Page 28 of 32
CY7C652148
Package Information
Support currently is planned for the 24-pin QFN package.
Figure 15. 24-pin QFN 4 mm 4 mm 0.55 mm LQ24A 2.65 2.65 EPAD (Sawn)
001-13937 *H
Table 16. Package Characteristics
Description
Min
Typ
Max
Units
TA
Parameter
Operating ambient temperature
–40
25
85
°C
THJ
Package JA
–
18.4
–
°C/W
Table 17. Solder Reflow Peak Temperature
Package
Maximum Peak Temperature
Maximum Time at Peak Temperature
24-pin QFN
260 °C
30 seconds
Table 18. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package
MSL
24-pin QFN
MSL 3
Document Number: 002-31601 Rev. **
Page 29 of 32
CY7C652148
Acronyms
Document Conventions
Table 19. Acronyms Used in this Document
Units of Measure
Acronym
Description
Table 20. Units of Measure
BCD
battery charger detection
CDC
communication driver class
C
degree Celsius
CDP
charging downstream port
DMIPS
Dhrystone million instructions per second
DCP
dedicated charging port
k
kilo-ohm
DLL
dynamic link library
KB
kilobyte
ESD
electrostatic discharge
kHz
kilohertz
GPIO
general purpose input/output
kV
kilovolt
HBM
human-body model
Mbps
megabits per second
MCU
microcontroller unit
MHz
megahertz
OSC
oscillator
mm
millimeter
PHDC
personal health care device class
V
volt
PID
product identification
SCB
serial communication block
SDP
standard downstream port
SIE
serial interface engine
SPI
serial peripheral interface
VCOM
virtual communication port
USB
Universal Serial Bus
VID
vendor identification
Document Number: 002-31601 Rev. **
Symbol
Unit of Measure
Page 30 of 32
CY7C652148
Document History Page
Document Title: CY7C652148, USB-SPI Single Channel Bridge Controller
Document Number: 002-31601
Revision
ECN
Submission
Date
**
7021631
11/26/2020
Document Number: 002-31601 Rev. **
Description of Change
Final datasheet to NSO.
Page 31 of 32
CY7C652148
Sales, Solutions, and Legal Information
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cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries ("Cypress"). This document, including any software or firmware
included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all
rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the
Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal,
non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software
solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through
resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified)
to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
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as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, "Security
Breach"). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In
addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted
by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or
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responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. "High-Risk Device"
means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other
medical devices. "Critical Component" means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk
Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of
a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from
and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress
product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i)
Cypress's published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to
use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-31601 Rev. **
Revised November 26, 2020
Page 32 of 32
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