CY8C21645-24PVXA

Automotive PSoC Programmable System-on-Chip™ Features ■ ■ ❐ ❐ ■ CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 ® Automotive Electronics Council (AEC) Q100 qualified Powerful Harvard-architecture processor ❐ M8C processor speeds up to 24 MHz ❐ 8 × 8 multiply, 32-bit accumulate ❐ Low power at high speed ❐ Automotive A-grade: 3.0 V to 5.25 V operation at –40 °C to +85 °C temperature range ❐ Automotive E-grade: 4.75 V to 5.25 V operation at –40 °C to +125 °C temperature range ® ■ Advanced peripherals (PSoC blocks) ❐ Six analog Type ‘E’ PSoC blocks provide: • Up to four comparators with digital-to-analog converters (DAC) references • Up to 10-bit single or dual analog-to-digital converters (ADCs) ❐ Up to eight digital PSoC blocks provide: • 8 to 32-bit timers, counters, and pulse width modulators (PWMs) • One-shot, multi-shot mode in timers and PWMs • PWM with deadband in one digital block • Shift register, cyclical redundancy check (CRC), and pseudo random sequence (PRS) modules • Full- or half-duplex UARTs • SPI masters or slaves, 8- to 16-bit variable data length • Connectable to all general-purpose I/O (GPIO) pins ❐ Complex peripherals by combining blocks ❐ Powerful synchronization support, analog module operations can be synchronized by digital blocks or external signals. ■ High-speed 10-bit successive approximation register (SAR) ADC with sample and hold optimized for embedded control ® ® ■ CY8C22345H devices integrate Immersion TouchSense haptics technology for ERM drive control ■ Precision, programmable clocking ❐ Internal oscillator up to 24 MHz ❐ High accuracy 24 MHz with optional 32-kHz crystal and phase locked loop (PLL) ❐ Optional external oscillator, up to 24 MHz ❐ Internal low speed, low-power oscillator for watchdog and sleep functionality ■ Flexible on-chip memory ❐ Up to 16 KB flash program storage, 1000 erase/write cycles ❐ Up to 1 KB SRAM data storage ❐ In-System Serial Programming (ISSP) ❐ Partial flash updates ❐ Flexible protection modes ❐ EEPROM emulation in flash ® ■ Optimized CapSense resource ❐ Supports two CapSense channels with simultaneous scanning ❐ Two current DACs provide programmable sensor tuning in firmware Cypress Semiconductor Corporation Document Number: 001-55397 Rev. *I • ■ ■ Two dedicated clock resources for CapSense Two dedicated 16-bit timers/counters for CapSense scanning Versatile analog mux ❐ Common internal analog bus ❐ Simultaneous connection of I/O combinations Programmable pin configurations ❐ 25 mA sink, 10 mA drive on all GPIOs ❐ Pull-up, pull-down, high Z, strong, or open drain drive modes on all GPIOs ❐ Analog input on all GPIOs ❐ Configurable interrupt on all GPIOs Additional system resources: 2 ❐ I C master, slave, or multi-master • Operation up to 400 kHz • Hardware address detection feature ❐ Watchdog and sleep timers ❐ User-configurable low voltage detection ❐ Integrated supervisory circuit ❐ On-chip precision voltage reference ❐ Hardware real time clock (RTC) block Block Diagram Port 4 Port 3 Port 2 Port 1 Port 0 PSoC CORE System Bus Global Digital Interconnect SRAM 1KB/512B Interrupt Controller SROM Global Analog Interconnect Flash 16K/8K Sleep and Watchdog CPU Core (M8C) Multiple Clock Sources (Includes IMO, ILO, PLL, and ECO) DIGITAL SYSTEM ANALOG SYSTEM 10-bit SAR ADC Analog Ref Analog Input Muxing Digital Block Array CapSense Digital Resources Analog Block Array Digital Clocks Multiply Accum. POR and LVD I2C RTC System Resets Internal Voltage Ref. SYSTEM RESOURCES 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 18, 2011 [+] Feedback CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 Contents PSoC Functional Overview .............................................. 3 PSoC Core .................................................................. 3 Digital System ............................................................. 3 Analog System ............................................................ 4 Haptics TS2000 Controller .......................................... 4 Additional System Resources ..................................... 5 PSoC Device Characteristics ...................................... 5 Getting Started .................................................................. 6 Application Notes ........................................................ 6 Development Kits ........................................................ 6 Training ....................................................................... 6 CYPros Consultants .................................................... 6 Solutions Library .......................................................... 6 Technical Support ....................................................... 6 Development Tools .......................................................... 6 PSoC Designer Software Subsystems ........................ 6 Designing with PSoC Designer ....................................... 7 Select User Modules ................................................... 7 Configure User Modules .............................................. 7 Organize and Connect ................................................ 7 Generate, Verify, and Debug ....................................... 7 Pinouts .............................................................................. 8 28-Pin Part Pinout ....................................................... 8 48-Pin Part Pinout ....................................................... 9 Registers ......................................................................... 11 Register Conventions ................................................ 11 Register Mapping Tables .......................................... 11 Electrical Specifications ................................................ 14 Absolute Maximum Ratings ....................................... 15 Operating Temperature ............................................ 15 DC Electrical Characteristics ..................................... 16 AC Electrical Characteristics ..................................... 21 Packaging Information ................................................... 26 Package Dimensions ................................................. 26 Thermal Impedances ................................................ 27 Capacitance on Crystal Pins .................................... 27 Solder Reflow Peak Temperature ............................. 27 Tape and Reel Information ........................................ 28 Development Tool Selection ......................................... 30 Software .................................................................... 30 Development Kits ...................................................... 30 Evaluation Tools ........................................................ 30 Device Programmers ................................................. 31 Accessories (Emulation and Programming) .............. 31 Ordering Information ...................................................... 32 Ordering Code Definitions ........................................ 33 Document Conventions ................................................. 34 Acronyms Used ......................................................... 34 Units of Measure ....................................................... 34 Numeric Naming ........................................................ 34 Document History Page ................................................. 35 Sales, Solutions, and Legal Information ...................... 36 Worldwide Sales and Design Support ....................... 36 Products .................................................................... 36 PSoC Solutions ......................................................... 36 Document Number: 001-55397 Rev. *I Page 2 of 36 [+] Feedback CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 PSoC Functional Overview The PSoC programmable system-on-chip series of products consists of many devices. These devices are designed to replace multiple traditional MCU-based system components with one low cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, as well as programmable interconnects. This architecture enables the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts and packages. The PSoC architecture, shown in the Block Diagram on page 1, consists of four main areas: PSoC core, digital system, analog system, and system resources. Configurable global busing allows the combining of all the device resources into a complete custom system. The PSoC family can have up to five I/O ports connecting to the global digital and analog interconnects, providing access to eight digital blocks[1] and six analog blocks. Digital System The digital system is composed of eight digital PSoC blocks. Each block is an 8-bit resource that may be used alone or combined with other blocks to form 8-, 16-, 24-, and 32-bit peripherals, which are called user modules. Figure 1. Digital System Block Diagram[1] Port 3 Port 4 Port 2 Port 1 Port 0 Digital Clocks From Core To System Bus To Analog System DIGITAL SYSTEM Digital PSoC Block Array Row Input Configuration Row 0 DBC00 DBC01 DCC02 4 DCC03 4 Row Output Configuration 8 PSoC Core The PSoC core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO. The M8C CPU core is a powerful processor with speeds up to 24 MHz (up to 12 MHz for E-grade devices), providing four MIPS (two MIPS for E-grade devices) 8-bit Harvard architecture microprocessor. The CPU uses an interrupt controller to simplify the programming of real time embedded events. Program execution is timed and protected using the included Sleep Timer and Watch Dog Timer (WDT). Memory encompasses 16 KB of flash (8 KB for CY8C21x45 devices) for program storage, 1 KB of SRAM (512 bytes for CY8C21x45 devices) for data storage, and EEPROM emulation using the flash. Program flash uses four protection levels on blocks of 64 bytes, allowing customized software IP protection. The PSoC device incorporates flexible internal clock generators, including a 24-MHz internal main oscillator (IMO). For A-grade devices the 24-MHz IMO can also be doubled to 48 MHz for use by the digital system. A low-power 32-kHz internal low-speed oscillator (ILO) is provided for the Sleep Timer and WDT. If crystal accuracy is required, the 32.768 kHz external crystal oscillator (ECO) is available for use as a RTC, and can optionally generate a crystal-accurate 24-MHz system clock using a PLL. The clocks, together with programmable clock dividers (as a system resource), provide the flexibility to integrate almost any timing requirement into the PSoC device. PSoC GPIOs provide connection to the CPU, digital, and analog resources of the device. Each pin’s drive mode may be selected from eight options, allowing great flexibility in external interfacing. Each pin can also generate a system interrupt. 8 8 Row Input Configuration 8 Row 1 DBC00 DBC01 DCC02 DCC03 Row Output Configuration GIE[7:0] GIO[7:0] Global Digital Interconnect GOE[7:0] GOO[7:0] Digital peripheral configurations are: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ PWMs (8- to 32-bit) PWMs with deadband (8- to 32-bit) Counters (8- to 32-bit) Timers (8- to 32-bit) One-shot and multi-shot modules Full or half-duplex 8-bit UART with selectable parity (up to two full-duplex or four half-duplex) SPI master and slave (up to four total) with programmable data length from 8 to 16 bits. Shift register (1- to 32-bit) I2C master, slave, or multi-master (one available) CRC/generator (16-bit) IrDA (up to two) PRS generators (8- to 32-bit) Note 1. CY8C22x45 devices have 2 digital rows with 8 digital blocks. CY8C21x45 devices only have 1 digital row with 4 digital blocks. Document Number: 001-55397 Rev. *I Page 3 of 36 [+] Feedback CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 The digital blocks may be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This provides a choice of system resources for your application. Family resources are shown in Table 1 on page 5. Figure 2. Analog System Block Diagram Array Input Configuration ACI0[1:0] ACI1[1:0] ACI1[1:0] ACI1[1:0] Analog System The Analog System of CY8C21x45 and CY8C22x45 PSoC devices consists of a 10-bit SAR ADC and six configurable analog blocks. The programmable 10-bit SAR ADC is an optimized ADC with a fast maximum sample rate. External filters are required on ADC input channels for antialiasing. This ensures that any out-of-band content is not folded into the input signal band. Reconfigurable analog resources allow creating complex analog signal flows. Analog peripherals are very flexible and may be customized to support specific application requirements. Some of the more common PSoC analog functions (most available as user modules) are: ■ ■ ■ ■ ACE00 ASE10 ACE01 ASE11 ACE10 ACE11 Block Array AmuxL AmuxR P0[0:7] ACI2[3:0] 10 bit SAR ADC Analog Reference Interface to Digital System Reference Generators Analog-to-digital converters (single or dual, with up to 10-bit resolution) Pin-to-pin comparator Single-ended comparators (up to four) with absolute (1.3 V) reference or DAC reference Precision voltage reference (1.3 V nominal) AGND Bandgap M8C Interface (Address Bus, Data Bus, Etc.) CY8C21x45 and CY8C22x45 devices have six limited-functionality Type 'E' analog blocks. These analog blocks are arranged in four columns. Each column contains one continuous time (CT) Type E block. The first two columns also have a switched capacitor (SC) type E block. Refer to the PSoC Technical Reference Manual for CY8C21x45 and CY8C22x45 devices for detailed information on the Type E analog blocks. Haptics TS2000 Controller The CY8C22x45H family of devices features an easy-to-use Haptics controller resource with up to 14 different effects. These effects are available for use with three different, selectable ERM modules. Document Number: 001-55397 Rev. *I Page 4 of 36 [+] Feedback CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 Additional System Resources System Resources, some of which are listed in the previous sections, provide additional capability useful for complete systems. Additional resources include a MAC, low voltage detection, and power on reset. The merits of each system resource are: ■ PSoC Device Characteristics Depending on your PSoC device characteristics, the digital and analog systems can have varying numbers of digital and analog blocks. The following table lists the resources available for specific PSoC device groups. The PSoC families covered by this datasheet are highlighted in the table. Table 1. PSoC Device Characteristics Analog Columns Analog Outputs Analog Inputs Analog Blocks Digital Blocks Digital I/O Digital Rows SRAM Size 2 KB 1 KB 1 KB 256 Bytes 256 Bytes 1 KB 512 Bytes 512 Bytes 256 Bytes 512 Bytes PSoC Part Number CY8C29x66[2] CY8C28xxx CY8C27x43 CY8C24x94[2] CY8C24x23A[2] CY8C23x33 CY8C22x45[2] CY8C21x45[2] CY8C21x34[2] CY8C21x23 CY8C20x34[2] Flash Size 32 KB 16 KB 16 KB 4 KB 8 KB 16 KB 8 KB 8 KB 4 KB 8 KB Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks may be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers. Additional digital resources and clocks dedicated to and optimized for CapSense. RTC hardware block. A multiply accumulate (MAC) provides a fast 8-bit multiplier with 32-bit accumulate, to assist in both general math and digital filters. The I2C module provides 0 to 400 kHz communication over two wires. Slave, master, and multi-master modes are all supported. Low voltage detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced power on reset (POR) circuit eliminates the need for a system supervisor. An internal voltage reference provides an absolute reference for the analog system, including ADCs and DACs. ■ ■ ■ up to 64 up to 44 up to 44 up to 56 up to 24 up to 25 up to 38 up to 38 up to 28 up to 16 up to 28 4 16 up to 12 4 4 12 up to up to up to up to up to up to 3 12 44 4 6 16 2 1 1 1 2 1 1 1 0 8 4 4 4 8 4 4 4 0 up to 12 up to 48 up to 12 up to 12 up to 38 up to 38 up to 28 up to 8 up to 28 4 2 2 2 0 0 0 0 0 4 2 2 2 4 4 2 2 0 12 6 6 4 6[3] 6[3] 4[3] 4[3] 3[3, 4] 256 16 KB Bytes ■ ■ ■ Notes 2. Automotive qualified devices available in this group. 3. Limited analog functionality. 4. Two analog blocks and one CapSense® block. Document Number: 001-55397 Rev. *I Page 5 of 36 [+] Feedback CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 Getting Started For in depth information, along with detailed programming details, see the PSoC® Technical Reference Manual. For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device datasheets on the web. Development Tools PSoC Designer™ is the revolutionary Integrated Design Environment (IDE) that you can use to customize PSoC to meet your specific application requirements. PSoC Designer software accelerates system design and time to market. Develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. Then, customize your design by leveraging the dynamically generated application programming interface (API) libraries of code. Finally, debug and test your designs with the integrated debug environment, including in-circuit emulation and standard software debug features. PSoC Designer includes: ■ ■ ■ ■ ■ ■ ■ Application Notes Cypress application notes are an excellent introduction to the wide variety of possible PSoC designs. Development Kits PSoC Development Kits are available online from and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark. Application editor graphical user interface (GUI) for device and user module configuration and dynamic reconfiguration Extensive user module catalog Integrated source-code editor (C and assembly) Free C compiler with no size restrictions or time limits Built-in debugger In-circuit emulation Training Free PSoC technical training (on demand, webinars, and workshops), which is available online via www.cypress.com, covers a wide variety of topics and skill levels to assist you in your designs. CYPros Consultants Certified PSoC consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC consultant go to the CYPros Consultants web site. Solutions Library Visit our growing library of solution focused designs. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. Built-in support for communication interfaces: 2 ❐ Hardware and software I C slaves and masters ❐ Full-speed USB 2.0 ❐ Up to four full-duplex universal asynchronous receiver/transmitters (UARTs), SPI master and slave, and wireless PSoC Designer supports the entire library of PSoC 1 devices and runs on Windows XP, Windows Vista, and Windows 7. PSoC Designer Software Subsystems Design Entry In the chip-level view, choose a base device to work with. Then select different onboard analog and digital components that use the PSoC blocks, which are called user modules. Examples of user modules are analog-to-digital converters (ADCs), digital-to-analog converters (DACs), amplifiers, and filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration makes it possible to change configurations at run time. In essence, this allows you to use more than 100 percent of PSoC's resources for a given application. Code Generation Tools The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. You can develop your design in C, assembly, or a combination of the two. Assemblers. The assemblers allow you to merge assembly code seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. Technical Support Technical support – including a searchable Knowledge Base articles and technical forums – is also available online. If you cannot find an answer to your question, call our Technical Support hotline at 1-800-541-4736. Document Number: 001-55397 Rev. *I Page 6 of 36 [+] Feedback CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all of the features of C, tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger PSoC Designer has a debug environment that provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow you to read and program and read and write data memory, and read and write I/O registers. You can read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows you to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer. In-Circuit Emulator A low-cost, high-functionality In-Circuit Emulator (ICE) is available for development support. This hardware can program single devices. The emulator consists of a base unit that connects to the PC using a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full-speed (24-MHz) operation. Configure User Modules Each user module that you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a pulse width modulator (PWM) User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. All the user modules are documented in datasheets that may be viewed directly in PSoC Designer or on the Cypress website. These user module datasheets explain the internal operation of the user module and provide performance specifications. Each datasheet describes the use of each user module parameter, and other information you may need to successfully implement your design. Organize and Connect You build signal chains at the chip level by interconnecting user modules to each other and the I/O pins. You perform the selection, configuration, and routing so that you have complete control over all on-chip resources. Generate, Verify, and Debug When you are ready to test the hardware configuration or move on to developing code for the project, you perform the “Generate Configuration Files” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. The generated code provides application programming interfaces (APIs) with high-level functions to control and respond to hardware events at run time and interrupt service routines that you can adapt as needed. A complete code development environment allows you to develop and customize your applications in either C, assembly language, or both. The last step in the development process takes place inside PSoC Designer’s debugger (access by clicking the Connect icon). PSoC Designer downloads the HEX image to the ICE where it runs at full speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the debug interface provides a large trace buffer and allows you to define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. Designing with PSoC Designer The development process for the PSoC® device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process is summarized in four steps: 1. Select User Modules. 2. Configure user modules. 3. Organize and connect. 4. Generate, verify, and debug. Select User Modules PSoC Designer provides a library of prebuilt, pretested hardware peripheral components called “user modules.” User modules make selecting and implementing peripheral devices, both analog and digital, simple. Document Number: 001-55397 Rev. *I Page 7 of 36 [+] Feedback CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 Pinouts The automotive CY8C21x45 and CY8C22x45 PSoC devices are available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a “P”) is capable of digital I/O and connection to the common analog mux bus. However, VSS, VDD, and XRES are not capable of digital I/O. 28-Pin Part Pinout Table 2. 28-Pin Part Pinout (SSOP) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input MR MR MR I, MR I, MR I, MR I, MR I, MR Power I/O I/O I/O I/O Type Digital I/O I/O I/O I/O I/O I/O I/O I/O Analog I, MR I, ML I, ML I, ML I, ML ML ML ML Power ML ML ML ML Power MR MR MR MR Pin Name P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] VSS P1[7] P1[5] P1[3] P1[1] VSS P1[0] P1[2] P1[4] P1[6] XRES P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] VDD Direct input to analog block Analog column mux input Analog column mux input Analog column mux input Analog column mux input Supply voltage Active high external reset with internal pull-down Optional external clock input (EXTCLK) Crystal Input (XTALin), I2C SCL, ISSP-SCLK[5] Ground Connection Crystal Output (XTALout), I2C SDA, ISSP-SDATA[5] Ground connection I2C Serial Clock (SCL) I C Serial Data (SDA) 2 Description Analog column mux input, CMOD capacitor pin Analog column mux input, CMOD capacitor pin Analog column mux input Analog column mux input Direct input to analog block Optional SAR ADC external reference (EXTREF) Figure 3. CY8C21345, CY8C22345, and CY8C22345H 28-Pin PSoC Device AI, MR, P0[7] AI, ML, P0[5] AI, ML, P0[3] AI, ML, P0[1] AI, ML, P2[7] EXTREF, ML, P2[5] ML, P2[3] ML, P2[1] VSS I2C SCL, ML, P1[7] I2C SDA, ML, P1[5] ML, P1[3] XTALin, I2C SCL, ML, P1[1] VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD P0[6], MR, AI P0[4], MR, AI P0[2], MR, AI P0[0], MR, AI P2[6], MR, AI P2[4], MR P2[2], MR P2[0], MR XRES P1[6], MR P1[4], MR, EXTCLK P1[2], MR P1[0], MR, I2C SDA, XTALout LEGEND: A = Analog, I = Input, O = Output, MR= Right analog mux bus input, ML= Left analog mux bus input. Note 5. These are the ISSP pins, which are not High Z after exiting a reset state. See the PSoC Technical Reference Manual for CY8C21x45 and CY8C22x45 devices for details. Document Number: 001-55397 Rev. *I Page 8 of 36 [+] Feedback CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 48-Pin Part Pinout Table 3. 48-Pin Part Pinout (SSOP) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Type Pin Name Description Digital Analog I/O I, MR P0[7] Analog column mux input, CMOD capacitor pin I/O I, ML P0[5] Analog column mux input, CMOD capacitor pin I/O I, ML P0[3] Analog column mux input I/O I, ML P0[1] Analog column mux input I/O I, ML P2[7] Direct input to analog block I/O ML P2[5] Optional SAR ADC external reference I/O ML P2[3] I/O ML P2[1] Power VDD Supply voltage I/O ML P4[5] I/O ML P4[3] I/O ML P4[1] Power VSS Ground connection I/O ML P3[7] I/O ML P3[5] I/O ML P3[3] I/O ML P3[1] NC Not connected NC Not connected I/O ML P1[7] I2C Serial Clock I/O ML P1[5] I2C Serial Data I/O ML P1[3] I/O ML P1[1] Crystal Input (XTALin), I2C SCL, ISSP-SCLK[6] Power VSS I/O MR P1[0] Crystal Output (XTALout), I2C SDA, ISSP-SDATA[6] I/O MR P1[2] I/O MR P1[4] Optional external clock input I/O MR P1[6] NC Not connected NC Not connected I/O MR P3[0] I/O MR P3[2] I/O MR P3[4] I/O MR P3[6] Input XRES Active high external reset with internal pull-down I/O MR P4[0] I/O MR P4[2] I/O MR P4[4] Power VSS Ground Connection I/O MR P2[0] Figure 4. CY8C21645 and CY8C22645 48-Pin PSoC Device AI, MR, P0[7] AI, ML, P0[5] AI, ML, P0[3] AI, ML, P0[1] AI, ML, P2[7] EXTREF, ML, P2[5] ML, P2[3] ML, P2[1] VDD ML, P4[5] ML, P4[3] ML, P4[1] VSS ML, P3[7] ML, P3[5] ML, P3[3] ML, P3[1] NC NC I2C SCL, ML, P1[7] I2C SDA, ML, P1[5] ML, P1[3] XTALin, I2C SCL, ML, P1[1] VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SSOP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDD P0[6], MR, AI P0[4], MR, AI P0[2], MR, AI P0[0], MR, AI P2[6], MR, AI P2[4], MR P2[2], MR P2[0], MR VSS P4[4], MR P4[2], MR P4[0], MR XRES P3[6], MR P3[4], MR P3[2], MR P3[0], MR NC NC P1[6], MR P1[4], MR, EXTCLK P1[2], MR P1[0], MR, I2C SDA, XTALout Note 6. These are the ISSP pins, which are not High Z after exiting a reset state. See the PSoC Technical Reference Manual for CY8C21x45 and CY8C22x45 devices for details. Document Number: 001-55397 Rev. *I Page 9 of 36 [+] Feedback CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 Table 3. 48-Pin Part Pinout (SSOP) (continued) Pin No. 41 42 43 44 45 46 47 48 Type Pin Name Digital Analog I/O MR P2[2] I/O MR P2[4] I/O I, MR P2[6] I/O I, MR P0[0] I/O I, MR P0[2] I/O I, MR P0[4] I/O I, MR P0[6] Power VDD Description Direct input to analog block Analog column mux input Analog column mux input Analog column mux input Analog column mux input Supply voltage LEGEND: A = Analog, I = Input, O = Output, MR= Right analog mux bus input, ML= Left analog mux bus input Document Number: 001-55397 Rev. *I Page 10 of 36 [+] Feedback CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 Registers This section lists the registers of this PSoC device family by mapping tables. For detailed register information, refer to the PSoC Technical Reference Manual for CY8C21x45 and CY8C22x45 devices. Register Conventions The register conventions specific to this section are listed in the following table. Register Mapping Tables The PSoC device has a total register address space of 512 bytes. The register space is referred to as I/O space and is divided into two banks. The XIO bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XIO bit is set the user is in Bank 1. Table 4. Abbreviations Convention RW R W L C # Description Read and write register or bit(s) Read register or bit(s) Write register or bit(s) Logical register or bit(s) Clearable register or bit(s) Access is bit specific Note In the following register mapping tables, blank fields are Reserved and must not be accessed. Document Number: 001-55397 Rev. *I Page 11 of 36 [+] Feedback CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 Table 5. Register Map Bank 0 Table: User Space Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 Addr (0,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBC00DR0 DBC00DR1 DBC00DR2 DBC00CR0 DBC01DR0 DBC01DR1 DBC01DR2 DBC01CR0 DCC02DR0 DCC02DR1 DCC02DR2 DCC02CR0 DCC03DR0 DCC03DR1 DCC03DR2 DCC03CR0 DBC10DR0 DBC10DR1 DBC10DR2 DBC10CR0 DBC11DR0 DBC11DR1 DBC11DR2 DBC11CR0 DCC12DR0 DCC12DR1 DCC12DR2 DCC12CR0 DCC13DR0 DCC13DR1 DCC13DR2 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW ACE01CR1 ACE01CR2 ACE00CR1 ACE00CR2 ADC0_CR ADC1_CR SADC_DH SADC_DL TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW CSD0_DR0_L CSD0_DR1_L CSD0_CNT_L CSD0_CR0 CSD0_DR0_H CSD0_DR1_H CSD0_CNT_H CSD0_CR1 CSD1_DR0_L CSD1_DR1_L CSD1_CNT_L CSD1_CR0 CSD1_DR0_H CSD1_DR1_H CSD1_CNT_H CSD1_CR1 AMX_IN AMUX_CFG PWM_CR ARF_CR CMP_CR0 ASY_CR CMP_CR1 Name Addr (0,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F RW RW RW RW # # RW RW RW RW RW RW RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0DSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI1DSM # Access is bit specific. R W R # R W R RW R W R # R W R RW RW RW RW RW # # RW ASE11CR0 Access Name ASE10CR0 Addr (0,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW IDACR_D IDACL_D CPU_SCR1 CPU_SCR0 CPU_F DEC _CR0 DEC_CR1 MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW RW # # RL RW RW W W R R RW RW RW RW IDX_PP MVR_PP MVW_PP I2C0_CFG I2C0_SCR I2C0_DR I2C0_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT PWMVREF0 PWMVREF1 IDAC_MODE PWM_SRC TS_CR0 TS_CMPH TS_CMPL TS_CR1 CUR PP STK_PP RW Access RW Name Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W # # RW # RW RW RW RW RW RW Access DCC13CR0 3F # Blank fields are Reserved and must not be accessed. Document Number: 001-55397 Rev. *I Page 12 of 36 [+] Feedback CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 Table 6. Register Map Bank 1 Table: Configuration Space Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 Addr (1,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBC00FN DBC00IN DBC00OU DBC00CR1 DBC01FN DBC01IN DBC01OU DBC01CR1 DCC02FN DCC02IN DCC02OU DBC02CR1 DCC03FN DCC03IN DCC03OU DBC03CR1 DBC10FN DBC10IN DBC10OU DBC10CR1 DBC11FN DBC11IN DBC11OU DBC11CR1 DCC12FN DCC12IN DCC12OU DBC12CR1 DCC13FN DCC13IN DCC13OU 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ACE01CR1 ACE01CR2 ACE00CR1 ACE00CR2 VDAC51CR0 CSCMPCR0 CSCMPGOEN CSLUTCR0 CMPCOLMUX CMPPWMCR CMPFLTCR CMPCLK1 CMPCLK0 CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 CMP_GO_EN CMP_GO_EN1 AMD_CR1 ALT_CR0 ALT_CR1 CLK_CR2 AMUX_CFG1 CLK_CR3 TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW VDAC50CR0 CMP1CR1 CMP1CR2 CMP0CR1 CMP0CR2 Name Addr (1,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F RW RW RW RW RW # RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0DSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI1DSM # Access is bit specific. GDI_O_IN_CR GDI_E_IN_CR GDI_O_OU_CR GDI_E_OU_CR RTC_H RTC_M RTC_S RTC_CR SADC_CR0 SADC_CR1 SADC_CR2 SADC_CR3TRIM SADC_CR4 I2C0_AD RW RW RW RW RW ASE11CR0 Access Name ASE10CR0 Addr (1,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW DAC_CR0# CPU_SCR1 CPU_SCR0 FLS_PR1 CPU_F RW RW RW RW RW RW RW RW RW RW RW RW RW RW MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 DAC_CR1# OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP ADC0_TR ADC1_TR V2BG_TR IMO_TR ILO_TR BDG_TR ECO_TR MUX_CR4 GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU RW Access RW Name Addr (1,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW # # RW RL RW RW RW RW RW RW RW RW RW RW RW RW R RW RW RW W W RW W RW RW RW RW RW Access DBC13CR1 3F RW Blank fields are Reserved and must not be accessed. Document Number: 001-55397 Rev. *I Page 13 of 36 [+] Feedback CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 Electrical Specifications This section presents the DC and AC electrical specifications for automotive CY8C21x45 and CY8C22x45 PSoC devices. For the latest electrical specifications, check the most recent data sheet by visiting the web at http://www.cypress.com. Specifications are valid for A-grade devices at –40 °C  TA  85 °C, TJ  100 °C, and for E-grade devices at –40 °C  TA  125 °C, TJ  150 °C, unless noted otherwise. Figure 5. Voltage vs. CPU Frequency for A-grade Devices Figure 6. Voltage vs. CPU Frequency for E-grade Devices 5.25 5.25 O Va p R era lid eg t i o i ng n 4.75 Vdd Voltage (V) 4.75 Vdd Voltage (V) lid g Va atin er n Op egio R 3.0 0 93 kHz CPU Frequency (nominal setting) 12 MHz 24 MHz 0 93 kHz CPU Frequency (nominal setting) 12 MHz 24 MHz Figure 7. IMO Frequency Trim Options (A-grade Devices Only) 5.25 SLIMO Mode=1 4.75 Vdd Voltage (V) SLIMO Mode=0 3.6 SLIMO Mode=1 3.0 SLIMO Mode=0 0 6 MHz 12 MHz IMO Frequency 24 MHz Document Number: 001-55397 Rev. *I Page 14 of 36 [+] Feedback CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 7. Absolute Maximum Ratings Symbol TSTG Description Storage temperature Min –55 Typ 25 Max +150 Units °C Notes Recommended storage temperature is 25 °C ± 25 °C. Higher storage temperatures reduce data retention time. TBAKETEMP Bake temperature – 125 TBAKETIME Bake time See package label –40 –40 –0.5 VSS – 0.5 VSS – 0.5 –25 2000 – – See package label 72 C Hours TA VDD VIO VIOz IMIO ESD LU Ambient temperature with power applied A-grade devices E-grade devices Supply voltage on VDD relative to VSS DC input voltage DC voltage applied to tristate Maximum current into any port pin Electrostatic discharge voltage Latch up current – – – – – – – – +85 +125 +6.0 VDD + 0.5 VDD + 0.5 +50 – 200 °C °C V V V mA V mA Human body model ESD Operating Temperature Table 8. Operating Temperature Symbol Description TA Ambient temperature A-grade devices E-grade devices TJ Junction temperature A-grade devices E-grade devices Min –40 –40 –40 –40 Typ – – – – Max +85 +125 +100 +135 Units °C °C °C °C Notes The temperature rise from ambient to junction is package specific. See Table 24 on page 27. The user must limit the power consumption to comply with this requirement. Document Number: 001-55397 Rev. *I Page 15 of 36 [+] Feedback CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 DC Electrical Characteristics DC Chip Level Specifications Table 9 lists the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless otherwise noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C, unless specified otherwise, and are for design guidance only. Table 9. DC Chip Level Specifications Symbol VDD Description Supply voltage A-grade devices E-grade devices Supply current A-grade devices, 3.0 V  VDD  3.6 V A-grade devices, 4.75 V  VDD  5.25 V E-grade devices Sleep (mode) current A-grade devices, 3.0 V  VDD  3.6 V A-grade devices, 4.75 V  VDD  5.25 V E-grade devices Sleep (mode) current with ECO A-grade devices, 3.0 V  VDD  3.6 V A-grade devices, 4.75 V  VDD  5.25 V E-grade devices Reference voltage (Bandgap) Min 3.0 4.75 – – – – – – – – – 1.275 Typ – – 4 7 8 3 4 4 4 5 5 1.30 Max 5.25 5.25 7 12 15 12 25 25 13 26 26 1.325 Units V V mA mA mA A A A A A A V Notes See Table 14 on page 19 IDD ISB CPU = 3 MHz, 48 MHz disabled. VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, Analog blocks disabled Everything disabled except ILO, POR, LVD, Sleep Timer, and WDT circuits Everything disabled except ECO, POR, LVD, Sleep Timer, and WDT circuits Trimmed for appropriate VDD setting. ISBXTL VREF Document Number: 001-55397 Rev. *I Page 16 of 36 [+] Feedback CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 DC General Purpose I/O Specifications Table 10 lists the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless otherwise noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C, unless specified otherwise, and are for design guidance only. Table 10. DC GPIO Specifications Symbol RPU RPD VOH VOL IOH IOL VIL VIH VH IIL CIN COUT Description Pull-up resistor Pull-down resistor High output level Min Typ 4 5.6 4 5.6 VDD – 1.0 – – – Max 8 8 – Low output level 0.75 High-level source current 10 – – Low-level sink current 25 – – Input low level Input high level Input hysteresis Input leakage (absolute value) Capacitive load on pins as input Capacitive load on pins as output – 2.1 – – – – – – 60 1 3.5 3.5 0.8 – – 10 10 Units Notes k k V IOH = 10 mA, VDD = 4.75 to 5.25 V (80 mA maximum combined IOH budget) V IOL = 25 mA, VDD = 4.75 to 5.25 V (100 mA maximum combined IOL budget) mA VOH  VDD – 1.0 V, see the limitations of the total current in the note for VOH. mA VOL  0.75 V, see the limitations of the total current in the note for VOL. V V mV nA Gross tested to 1 A pF Package and pin dependent. Temp = 25 °C pF Package and pin dependent. Temp = 25 °C DC Operational Amplifier Specifications The following table lists the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless otherwise noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V at 25°C, unless specified otherwise, and are for design guidance only. Table 11. DC Operational Amplifier Specifications Description Input offset voltage (absolute value) Supply current (absolute value) A-grade devices E-grade devices TCVOSOA Average input offset voltage drift Input leakage current (Port 0 analog pins) IEBOA[7] Input capacitance (Port 0 analog pins) CINOA VCMOA Common mode voltage range Symbol VOSOA ISOA Min – – – – – – 0.5 Typ 2.5 – – 10 200 4.5 – Max 15 30 35 – – 9.5 Units mV Notes A µA V/°C pA Gross tested to 1 A pF Package and pin dependent. Temp = 25 °C VDD – 1 V Note 7. Atypical behavior: IEBOA of Port 0 Pin 0 is below 1 nA at 25 °C; 50 nA over temperature. Use Port 0 Pins 1 – 7 for the lowest leakage of 200 nA. Document Number: 001-55397 Rev. *I Page 17 of 36 [+] Feedback CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 DC SAR10 ADC Specifications Table 12 lists the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless otherwise noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C, unless specified otherwise, and are for design guidance only. Table 12. DC SAR10 ADC Specifications Symbol VADCREF Description Reference voltage at pin P2[5] when configured as ADC reference voltage Min 3.0 Typ – Max 5.25 Units V Notes When VREF is buffered inside ADC, the voltage level at P2[5] (when configured as ADC reference voltage) must be always maintained to be at least 300 mV less than the chip supply voltage level on VDD pin. (VADCREF < VDD) Disables the internal voltage reference buffer 10-bit resolution IADCREF INLADC Current into P2[5] when configured as ADC VREF Integral nonlinearity A-grade devices E-grade devices Differential nonlinearity A-grade devices E-grade devices – – 100 µA –3.0 –5.0 –1.5 –4.0 – – – – 3.0 5.0 1.5 4.0 LSbit LSbit 10-bit resolution LSbit LSbit DNLADC DC Analog Mux Bus Specifications Table 13 lists the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless otherwise noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C, unless specified otherwise, and are for design guidance only. Table 13. DC Analog Mux Bus Specifications Symbol RSW RGND Description Switch resistance to common analog bus Resistance of initialization switch to GND Min – – Typ – – Max 400 800 Units   Notes Document Number: 001-55397 Rev. *I Page 18 of 36 [+] Feedback CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 DC POR and LVD Specifications Table 14 lists the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless otherwise noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C, unless specified otherwise, and are for design guidance only. Table 14. DC POR and LVD Specifications Symbol VPPOR1 VPPOR2 Description VDD value for PPOR trip PORLEV[1:0] = 01b PORLEV[1:0] = 10b Min – – Typ 2.82 4.55 Max 2.95 4.73 Units V V Notes VDD must be greater than or equal to 3.0 V during startup, reset from the XRES pin, or reset from Watchdog. VPPOR1 is only applicable to A-grade devices. VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 VDD value for LVD trip VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b 2.95 3.06 4.37 4.50 4.62 4.71 3.02 3.13 4.48 4.64 4.73 4.81 3.09 3.20 4.55 4.75 4.83 4.95 V V V V V V Document Number: 001-55397 Rev. *I Page 19 of 36 [+] Feedback CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 DC Programming Specifications Table 15 lists the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless otherwise noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C, unless specified otherwise, and are for design guidance only. Table 15. DC Programming Specifications Symbol Description VDDIWRITE Supply voltage for flash write operations IDDP VILP VIHP IILP Supply current during programming or verify Input low voltage during programming or verify Input high voltage during programming or verify Min 3.0 – – 2.2 – – – VDD – 1.0 Typ – 5 – – – – – – Max – 25 0.8 – 0.2 1.5 0.75 VDD Units V mA V V mA mA V V Notes Input current when applying VILP to P1[0] or P1[1] during programming or verify IIHP Input current when applying VIHP to P1[0] or P1[1] during programming or verify VOLV Output low voltage during programming or verify VOHV Output high voltage during programming or verify FlashENPB Flash endurance (per block)[8, 9] A-grade devices E-grade devices FlashENT Flash endurance (total)[9, 10] CY8C21x45 A-grade devices CY8C22x45 A-grade devices CY8C21x45 E-grade devices CY8C22x45 E-grade devices FlashDR Flash data retention[9] A-grade devices E-grade devices Driving internal pull-down resistor Driving internal pull-down resistor Erase/write cycles per block 1,000 100 128,000 256,000 12,800 25,600 10 10 – – – – – – – – – – – – – – – – – – Erase/write cycles – – – – Years Years Notes 8. The erase/write cycle limit per block (FlashENPB) is only guaranteed if the device operates within one voltage range. Voltage ranges are 3.0 V to 3.6 V and 4.75 V to 5.25 V. 9. For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) or other temperature sensor and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 for more information. 10. The maximum total number of allowed erase/write cycles is the minimum FlashENPB value multiplied by the number of flash blocks in the device. Document Number: 001-55397 Rev. *I Page 20 of 36 [+] Feedback CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 AC Electrical Characteristics AC Chip Level Specifications The following tables list the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless otherwise noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C, unless specified otherwise, and are for design guidance only. Table 16. AC Chip-Level Specifications Symbol FIMO24 Description Internal main oscillator frequency for 24 MHz A-grade devices, 4.75 V  VDD  5.25 V A-grade devices, 3.0 V  VDD  3.6 V E-grade devices Internal main oscillator frequency for 6 MHz A-grade devices E-grade devices CPU frequency (5 V VDD operation) A-grade devices E-grade devices CPU frequency (3.3 V VDD operation) Digital PSoC block operation) A-grade devices E-grade devices frequency0(5 V VDD 0 0 0 15 5 48 24 24 32 – 50.4[11, 12] 25.2[11, 12] 24.6[11] 75 – MHz MHz MHz kHz kHz A-grade devices only This specification applies when the ILO has been trimmed. After a reset and before the M8C processor starts to execute, the ILO is not trimmed. Min 22.8 22.5 22.3 5.5 5.5 0.089 0.089 0.089 Typ 24 24 24 6 6 – – – Max 25.2[11] 25.5[11] 25.7[11] 6.5[11] 6.5[11] 25.2[11] 12.6[11] 12.6[11] Units MHz MHz MHz MHz MHz MHz MHz MHz A-grade devices only Refer to Table 19 on page 23. Notes Trimmed for 5 V or 3.3 V operation using factory trim values. See Figure 7 on page 14. Trimmed for 5 V or 3.3 V operation using factory trim values. See Figure 7 on page 14. FIMO6 FCPU1 FCPU2 FBLK5 FBLK33 F32K1 F32KU Jitter32k TXRST DC24M DCILO Fout48M Jitter24M1 FMAX Digital PSoC block frequency (3.3 V VDD operation) ILO frequency ILO untrimmed frequency 32 kHz RMS period jitter External reset pulse width 24 MHz duty cycle ILO duty cycle 48 MHz output frequency 24 MHz period jitter (IMO) Maximum frequency of signal on row input or row output – 10 40 20 45.6 – – – – 100 – 50 50 48.0 300 – – 16 – – 60 80 50.4[11] 600 12.6 250 100 ns µs % % MHz ps MHz V/ms ms VDD slew rate during power-up. Power-up from 0 V. SRPOWERUP Power supply slew rate TPOWERUP Time between end of POR state and CPU code execution Figure 8. 24 MHz Period Jitter (IMO) Timing Diagram Jitter24M1 F 24M Notes 11. Accuracy derived from IMO with appropriate trim for VDD range 12. Refer to the individual user module data sheets for information on maximum frequencies for user modules. Document Number: 001-55397 Rev. *I Page 21 of 36 [+] Feedback CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 Figure 9. 32 kHz Period Jitter (ILO) Timing Diagram Jitter32k F 32K1 AC General Purpose I/O Specifications Table 17 lists the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless otherwise noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C, unless specified otherwise, and are for design guidance only. Table 17. AC GPIO Specifications Symbol FGPIO TRiseF Description GPIO operating frequency Rise time, normal strong mode, Cload = 50 pF A-grade devices E-grade devices Fall time, normal strong mode, Cload = 50 pF A-grade devices E-grade devices Rise time, slow strong mode, Cload = 50 pF A-grade devices E-grade devices Fall time, slow strong mode, Cload = 50 pF A-grade devices E-grade devices Min 0 3 3 2 2 7 7 7 7 Typ – – – – – 27 32 22 28 Max 12.6 18 24 18 28 – – – – TFallF TRiseS TFallS Units Notes MHz Normal strong mode Refer to Figure 10 ns ns Refer to Figure 10 ns ns Refer to Figure 10 ns ns Refer to Figure 10 ns ns Figure 10. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% TRiseF T RiseS T FallF TFallS AC Operational Amplifier Specifications Table 18 lists the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless otherwise noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C, unless specified otherwise, and are for design guidance only. Table 18. AC Operational Amplifier Specifications Symbol TCOMP Description Comparator mode response time, 50 mV Min – Typ – Max 100 Units ns Notes Document Number: 001-55397 Rev. *I Page 22 of 36 [+] Feedback CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 AC Digital Block Specifications The following tables list the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless otherwise noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C, unless specified otherwise, and are for design guidance only. Table 19. AC Digital Block Specifications Function All Functions Timer Description Maximum block clocking frequency ( 4.75 V) Maximum block clocking frequency (< 4.75 V) Capture pulse width Maximum frequency, no capture Maximum frequency, with or without capture Enable pulse width Maximum frequency, no enable input Maximum frequency, enable input Kill pulse width: Asynchronous restart mode Synchronous restart mode Disable mode Maximum frequency Maximum input clock frequency Min – – 50[13] – – 50[13] – – 20 50[13] 50[13] – – – – – 50[13] – – – – Typ – – – – – – – – – – – – – – – – – – – – – Max 50.4 25.2 – 50.4 25.2 – 50.4 25.2 – – – 50.4 50.4 25.2 8.4 4.2 – 25.2 50.4 25.2 50.4 Counter Units Notes MHz Note [14] MHz VDD < 4.75 V and/or temperature > 85 °C ns MHz Note [14] MHz ns MHz Note [14] MHz ns ns ns MHz Note [14] MHz Note [14] MHz MHz Maximum nominal data rate is 4 Mbps due to 2 x overclocking MHz ns MHz Maximum nominal baud rate is 3 Mbaud due to 8 × overclocking MHz Maximum nominal baud rate is 6 Mbaud due to 8 × overclocking MHz Maximum nominal baud rate is 3 Mbaud due to 8 × overclocking MHz Maximum nominal baud rate is 6 Mbaud due to 8 × overclocking Dead Band CRCPRS (PRS Mode) CRCPRS Maximum input clock frequency (CRC Mode) SPIM Maximum input clock frequency SPIS Transmitter Maximum input clock frequency Width of SS_ negated between transmissions Maximum input clock frequency Maximum input clock frequency with VDD 4.75 V, 2 stop bits Maximum input clock frequency Maximum input clock frequency with VDD 4.75 V, 2 stop bits Receiver Notes 13. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period). 14. 4.75 V  VDD  5.25 V at –40 °C to 85 °C Document Number: 001-55397 Rev. *I Page 23 of 36 [+] Feedback CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 AC External Clock Specifications The following tables list the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless otherwise noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C, unless specified otherwise, and are for design guidance only. Table 20. AC External Clock Specifications Symbol FOSCEXT – – – Frequency High period Low period Power-up IMO to switch Description Min 0.093 20.0 20.0 150 Typ – – – – Max 24.6 5300 – – Units MHz ns ns s Notes AC SAR10 ADC Specifications Table 21 lists the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless otherwise noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C, unless specified otherwise, and are for design guidance only. Table 21. AC SAR10 ADC Specifications Symbol FINADC Description SAR ADC input clock frequency Min – Typ – Max 2 Units Notes MHz The sample rate of the SAR10 ADC is equal to FINADC divided by 13. AC Programming Specifications Table 22 lists the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless otherwise noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C, unless specified otherwise, and are for design guidance only. Table 22. AC Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK FSCLK3 TERASEB TWRITE TDSCLK TDSCLK3 TPRGH TPRGC Description Rise time of SCLK Fall time of SCLK Data setup time to falling edge of SCLK Data hold time from falling edge of SCLK Frequency of SCLK Frequency of SCLK Flash erase time (block) Flash block write time Data out delay from falling edge of SCLK Data out delay from falling edge of SCLK Total flash block program time (TERASEB + TWRITE), Hot Total flash block program time (TERASEB + TWRITE), Cold Min 1 1 40 40 0 0 – – – – – – Typ – – – – – – 10 40 – – – – Max 20 20 – – 8 6 40[15] 160[15] 55 65 100[15] 200[15] Units ns ns ns ns MHz MHz VDD  3.6 V ms ms ns ns ms ms Notes VDD > 3.6 V, 30 pF load TJ  0 °C TJ 0 °C 3.0 V VDD 3.6 V, 30 pF load Note 15. For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) or other temperature sensor and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 for more information. Document Number: 001-55397 Rev. *I Page 24 of 36 [+] Feedback CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 AC I2C Specifications Table 23 lists the guaranteed maximum and minimum specifications for automotive A-grade and E-grade devices. Unless otherwise noted, all specifications in the table apply to A-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 85 °C, or 3.0 V to 3.6 V and –40 °C to 85 °C. Unless otherwise noted, all specifications in the table also apply to E-grade devices for the voltage and temperature ranges of: 4.75 V to 5.25 V and –40 °C to 125 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C, unless specified otherwise, and are for design guidance only. Table 23. AC Characteristics of the I2C SDA and SCL Pins Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C Description SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated. LOW period of the SCL clock HIGH period of the SCL clock Setup time for a repeated START condition Data hold time Data setup time Setup time for STOP condition Bus-free time between a STOP and START condition Pulse width of spikes are suppressed by the input filter Standard Mode Min Max 0 100[16] 4.0 4.7 4.0 4.7 0 250 4.0 4.7 – – – – – – – – – – Fast Mode Min Max 0 400[16] 0.6 1.3 0.6 0.6 0 100[17] 0.6 1.3 0 – – – – – – – – 50 Units kHz s s s s s ns s s ns Figure 11. Definition for Timing for Fast/Standard Mode on the I2C Bus SDA TLOWI2C T SUDATI2C T HDSTAI2C TSPI2C TBUFI2C SCL S T HDSTAI2C T HDDATI2C T HIGHI2C T SUSTAI2C T SUSTOI2C Sr P S Notes 16. FSCLI2C is derived from SysClk of the PSoC. This specification assumes that SysClk is operating at 24 MHz, nominal. If SysClk is at a lower frequency, then the FSCLI2C specification adjusts accordingly. 17. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement TSUDATI2C  250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + TSUDATI2C = 1000 + 250 = 1250 ns (according to the standard-mode I2C-bus specification) before the SCL line is released. Document Number: 001-55397 Rev. *I Page 25 of 36 [+] Feedback CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 Packaging Information This section provides the packaging specifications for the automotive CY8C21x45 and CY8C22x45 PSoC devices. The thermal impedances for each package and the typical package capacitance on crystal pins are given. Package Dimensions Figure 12. 28-Pin (210-Mil) SSOP 51-85079 *D Document Number: 001-55397 Rev. *I Page 26 of 36 [+] Feedback CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 Figure 13. 48-Pin (300-Mil) SSOP .020 24 1 0.395 0.420 0.292 0.299 DIMENSIONS IN INCHES MIN. MAX. 25 48 0.620 0.630 0.088 0.092 0.095 0.110 SEATING PLANE GAUGE PLANE .010 0.005 0.010 0.025 BSC 0.004 0.008 0.0135 0.008 0.016 0°-8° 0.024 0.040 51-85061 *D Thermal Impedances Table 24. Thermal Impedances per Package Package 28-pin SSOP 48-pin SSOP Capacitance on Crystal Pins Table 25. Typical Package Capacitance on Crystal Pins [18] Typical JA 69 °C/W Package 28-pin SSOP 48-pin SSOP Package Capacitance 2.8 pF 3.3 pF 97.6 °C/W Solder Reflow Peak Temperature Following is the minimum solder reflow peak temperature to achieve good solderability. Table 26. Solder Reflow Peak Temperature Package 28-pin SSOP 48-pin SSOP Minimum Peak Temperature[19] Maximum Peak Temperature 240 °C 240 °C 260 °C 260 °C Notes 18. TJ = TA + POWER x JA 19. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 °C with Sn-Pb or 245 ± 5 °C with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications. Document Number: 001-55397 Rev. *I Page 27 of 36 [+] Feedback CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 Tape and Reel Information Figure 14. 28-Pin SSOP Carrier Tape Drawing 51-51100 *B Document Number: 001-55397 Rev. *I Page 28 of 36 [+] Feedback CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 Figure 15. 48-Pin SSOP Carrier Tape Drawing 51-51104 *D Table 27. Tape and Reel Specifications Package 28-Pin SSOP 48-Pin SSOP Cover Tape Width (mm) 13.3 25.5 Hub Size (inches) 7 4 Minimum Leading Empty Pockets 42 32 Minimum Trailing Empty Pockets 25 19 Standard Full Reel Quantity 1000 1000 Document Number: 001-55397 Rev. *I Page 29 of 36 [+] Feedback CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 Development Tool Selection This section presents the development tools available for the automotive CY8C21x45 and CY8C22x45 families. Software PSoC Designer At the core of the PSoC development software suite is PSoC Designer. Utilized by thousands of PSoC developers, this robust software has been facilitating PSoC designs for years. PSoC Designer is available free of charge at http://www.cypress.com. PSoC Designer comes with a free C compiler. PSoC Programmer Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer. PSoC Programmer software is compatible with both PSoC ICE-Cube In-Circuit Emulator and PSoC MiniProg. PSoC programmer is available free of charge at http://www.cypress.com. CY3280-22X45 Universal CapSense Controller Board The CY3280-22X45 controller board is an additional controller board for the CY3280-BK1 Universal CapSense Controller Kit. The Universal CapSense Controller kit is designed for easy prototyping and debug of CapSense designs with pre-defined control circuitry and plug-in hardware. The CY3280-22X45 kit contains no plug-in hardware. Therefore, it is only usable if plug-in hardware is purchased as part of the CY3280-BK1 kit or other separate kits. The kit includes: ■ ■ ■ ■ CY3280-22X45 universal CapSense controller board CY3280-22X45 universal CapSense controller board CD DC power supply Printed documentation CY3280-CPM1 CapSensePlus Module The CY3280-CPM1 CapSensePlus Module is a plug-in module board for the CY3280-22X45 CapSense controller board kit. This plug-in module has no capacitive sensors on it. Instead, it has other general circuitry (such as a seven-segment display, potentiometer, LEDs, buttons, thermistor) that can be used to develop applications that require capacitive sensing along with other additional functionality. To use this kit, a CY3280-22X45 kit is required. Development Kits All development kits can be purchased from the Cypress Online Store. The online store also has the most up to date information on kit contents, descriptions, and availability. CY3215-DK Basic Development Kit The CY3215-DK is for prototyping and development with PSoC Designer. This kit supports in-circuit emulation and the software interface allows users to run, halt, and single step the processor and view the contents of specific memory locations. Advanced emulation features are also supported through PSoC Designer. The kit includes: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Evaluation Tools All evaluation tools can be purchased from the Cypress online store. The online store also has the most up-to-date information on kit contents, descriptions, and availability. CY3210-PSoCEval1 The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, an RS-232 port, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes: ■ ■ ■ ■ ■ ■ ICE-Cube unit 28-pin PDIP emulation pod for CY8C29466-24PXI 28-pin CY8C29466-24PXI PDIP PSoC device samples (two) PSoC Designer software CD ISSP cable MiniEval socket programming and evaluation board Backward compatibility cable (for connecting to legacy pods) Universal 110/220 power supply (12 V) European plug adapter USB 2.0 cable Getting Started guide Development kit registration form Evaluation board with LCD module MiniProg programming unit 28-pin CY8C29466-24PXI PDIP PSoC device sample (two) PSoC Designer software CD Getting Started guide USB 2.0 cable Document Number: 001-55397 Rev. *I Page 30 of 36 [+] Feedback CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 Device Programmers All device programmers can be purchased from the Cypress Online Store. CY3210-MiniProg1 The CY3210-MiniProg1 kit allows the user to program PSoC devices through the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC through a provided USB 2.0 cable. The kit includes: ■ ■ ■ ■ ■ ■ CY3207ISSP In-System Serial Programmer The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production-programming environment. Note CY3207ISSP needs special software and is not compatible with PSoC Programmer. This software is free and can be downloaded from http://www.cypress.com. The kit includes: ■ ■ ■ ■ CY3207 programmer unit PSoC ISSP software CD 110 ~ 240-V power supply, Euro-Plug adapter USB 2.0 cable MiniProg programming unit MiniEval socket programming and evaluation board 28-pin CY8C29466-24PXI PDIP PSoC device sample PSoC Designer software CD Getting Started guide USB 2.0 cable Accessories (Emulation and Programming) Table 28. Emulation and Programming Accessories Part Number CY8C21345-24PVXA CY8C21345-12PVXE CY8C22345-24PVXA CY8C22345H-24PVXA CY8C22345-12PVXE CY8C21645-24PVXA CY8C21645-12PVXE CY8C22645-24PVXA CY8C22645-12PVXE Pin Package 28-pin SSOP Pod Kit[20] CY3250-22345 Foot Kit[21] CY3250-28SSOP-FK Prototyping Module – Adapter[22] AS-28-28-02SS-6ENP-GANG 48-pin SSOP – – – AS-48-48-01SS-6-GANG Notes 20. Pod kit contains an emulation pod, a flex-cable (connects the pod to the ICE), two feet, and device samples. 21. Foot kit includes surface mount feet that can be soldered to the target PCB. 22. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at http://www.emulation.com. Document Number: 001-55397 Rev. *I Page 31 of 36 [+] Feedback CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 Ordering Information The following table lists the key package features and ordering codes of the automotive CY8C21x45 and CY8C22x45 device families. Table 29. PSoC Device Family Key Features and Ordering Information Analog Outputs 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Digital I/O Pins Ordering Code Analog Blocks Analog Inputs SRAM (Bytes) Digital Blocks Flash (Bytes) Temperature Range 28-pin (210-Mil) SSOP 28-pin (210-Mil) SSOP (Tape and Reel) 28-pin (210-Mil) SSOP 28-pin (210-Mil) SSOP (Tape and Reel) 28-pin (210-Mil) SSOP 28-pin (210-Mil) SSOP (Tape and Reel) 28-pin (210-Mil) SSOP 28-pin (210-Mil) SSOP (Tape and Reel) 28-pin (210-Mil) SSOP 28-pin (210-Mil) SSOP (Tape and Reel) 48-pin (300-Mil) SSOP 48-pin (300-Mil) SSOP (Tape and Reel) 48-pin (300-Mil) SSOP 48-pin (300-Mil) SSOP (Tape and Reel) 48-pin (300-Mil) SSOP 48-pin (300-Mil) SSOP (Tape and Reel) 48-pin (300-Mil) SSOP 48-pin (300-Mil) SSOP (Tape and Reel) CY8C21345-24PVXA CY8C21345-24PVXAT CY8C21345-12PVXE CY8C21345-12PVXET CY8C22345-24PVXA CY8C22345-24PVXAT CY8C22345H-24PVXA CY8C22345H-24PVXAT CY8C22345-12PVXE CY8C22345-12PVXET CY8C21645-24PVXA CY8C21645-24PVXAT CY8C21645-12PVXE CY8C21645-12PVXET CY8C22645-24PVXA CY8C22645-24PVXAT CY8C22645-12PVXE CY8C22645-12PVXET 8K 8K 8K 8K 16 K 16 K 16 K 16 K 16 K 16 K 8K 8K 8K 8K 16 K 16 K 16 K 16 K 512 512 512 512 1K 1K 1K 1K 1K 1K 512 512 512 512 1K 1K 1K 1K –40 °C to +85 °C –40 °C to +85 °C –40 °C to +125 °C –40 °C to +125 °C –40 °C to +85 °C –40 °C to +85 °C –40 °C to +85 °C –40 °C to +85 °C –40 °C to +125 °C –40 °C to +125 °C –40 °C to +85 °C –40 °C to +85 °C –40 °C to +125 °C –40 °C to +125 °C –40 °C to +85 °C –40 °C to +85 °C –40 °C to +125 °C –40 °C to +125 °C 4 4 4 4 8 8 8 8 8 8 4 4 4 4 8 8 8 8 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 24 24 24 24 24 24 24 24 24 24 38 38 38 38 38 38 38 38 24 24 24 24 24 24 24 24 24 24 38 38 38 38 38 38 38 38 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Document Number: 001-55397 Rev. *I Page 32 of 36 XRES Pin [+] Feedback Package CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 Ordering Code Definitions CY 8 C 2x xxx x-SPxx Package type: PX = PDIP Pb-free SX = SOIC Pb-free PVX = SSOP Pb-free LFX/LTX = QFN Pb-free AX = TQFP Pb-free CPU Speed: 12/24 MHz Optional part number modifier: H = Integrated Immersion® TouchSense® technology Part number Family code (21, 22) Technology code: C = CMOS Marketing code: 8 = PSoC Company ID: CY = Cypress Semiconductor Thermal rating: A = Automotive –40 °C to +85 °C C = Commercial E = Automotive Extended –40 °C to +125 °C I = Industrial Document Number: 001-55397 Rev. *I Page 33 of 36 [+] Feedback CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 Document Conventions Acronyms Used Table 30. Acronyms Acronym AC ADC AEC API CPU CRC CT DAC DC ECO EEPROM ERM FSR GPIO ICE IDE I/O ILO IMO IPOR LSbit LVD MSbit PC PCB POR PPOR PRS PSoC PWM RAM ROM SC SMP SPI UART Units of Measure Table 31. Units of Measure Description Symbol °C dB fF Hz KB Kbit kHz k LSbit Mbaud Mbps MHz M A F H s V Vrms W mA ms mV nA ns nV  pA pF pp ppm ps sps  V Unit of Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm least significant bit megabaud megabits per second megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square microwatts milliampere millisecond millivolts nanoampere nanosecond nanovolts ohm picoampere picofarad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts alternating current analog-to-digital converter Automotive Electronics Council application programming interface central processing unit cyclic redundancy check continuous time digital-to-analog converter direct current external crystal oscillator electrically erasable programmable read-only memory eccentric rotating motor full scale range general purpose I/O in-circuit emulator integrated development environment input/output internal low-speed oscillator internal main oscillator imprecise power on reset least significant bit low voltage detect most significant bit program counter printed circuit board power on reset precision power on reset pseudo-random sequence Programmable System-on-Chip pulse width modulator random access memory read only memory switched capacitor switch mode pump serial peripheral interface universal asynchronous receiver/transmitter Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, ‘01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘0x’, or ‘b’ are decimal. Document Number: 001-55397 Rev. *I Page 34 of 36 [+] Feedback CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 Document History Page Document Title: CY8C21345, CY8C21645, CY8C22345, CY8C22345H, CY8C22645 Automotive PSoC® Programmable System-on-Chip™ Document Number: 001-55397 Revision ** *A ECN 2759868 2788690 Orig. of Change VIVG VIVG Submission Date 09/04/09 10/20/09 New Datasheet Description of Change Added 48 SSOP to the marketing part numbers. Corrected the ISOA spec in table 13/14. Changed the ThetaJA values based on PE inputs. Corrected typo in ordering information table (Digital I/O for 48-SSOP devices) Added CY8C22345H devices and updated Features section and PSoC Functional Overview section to include haptics device information. Updated Features section. Added Contents section. Updated PSoC Functional Overview section. Updated Block Diagram of device. Updated PSoC Device Characteristics table. Updated Pinouts section. Fixed issues with the Register Map tables. Added a figure for SLIMO configuration. Updated footnotes for the DC Programming Specifications table. Corrected VDDIWRITE and FlashENT electrical specifications. Updated Ordering Information section. Added Development Tool Selection section. Combined 5 V DC Operational Amplifier Specifications table with 3.3 V DC Operational Amplifier Specifications table. Updated all AC specifications to conform to 5% IMO accuracy and 8.33% SLIMO accuracy. Split up electrical specifications for A-grade and E-grade devices in the Absolute Maximum Ratings, Operating Temperature, DC Chip Level Specifications, DC Programming Specifications, and AC Chip-Level Specifications tables. Added Solder Reflow Peak Temperature table. Added TPRGH, TPRGC, IOL, IOH, F32KU, DCILO, and TPOWERUP electrical specifications. Added maximum values and updated typical values for TERASEB and TWRITE electrical specifications. Replaced TRAMP electrical specification with SRPOWERUP electrical specification. This revision fixes CDT 62018. Updated Cypress website links Added TBAKETEMP, TBAKETIME, and Fout48M electrical specifications Removed sections ‘Third Party Tools’ ‘Build a PSoC Emulator into your Board’ Updated package diagrams Updated Ordering Information table Updated Solder Reflow Peak Temperature specifications. Updated the Getting Started and Designing with PSoC Designer sections. Converted data sheet from Preliminary to Final Fixes from CDT 72358: Deleted 5% oscillator accuracy reference in the Features section. Deleted reference to a specific SAR10 ADC sample rate in the Analog System section. Updated the following Electrical Specifications: IDD, ISB, ISBXTL, VREF, VCMOA, IADCREF, INLADC, DNLADC, VPPOR2, FlashDR, FIMO24, TRiseF, TFallF, TRiseS, TFallS. Deleted the SPSADC electrical specification, the DC Low Power Comparator Specifications, the AC Low Power Comparator Specifications, and the AC Analog Mux Bus Specifications. Post to external web Added a clarifying note to the VPPOR1 electrical specification. Added CY8C22345-12PVXE(T) devices. Moved Document Conventions to the end of the document. This revision fixes the following CDTs: 72476, 75127, 78329. Added CY8C21345-12PVXE(T) devices to the Ordering Information section. Added CY8C21645-12PVXE(T), CY8C21645-24PVXA(T), CY8C22645-12PVXE(T), and CY8C22645-24PVXA(T) devices to the Ordering Information section. Refer to CDT 87793. Added tape and reel packaging information (CDT 96026). *B *C 2792800 2822630 VIVG BTK 10/26/09 12/07/09 *D 2905459 NJF 04/06/10 *E *F 2915673 2991841 VIVG BTK 04/16/10 07/23/10 *G *H 3037161 3085024 BTK BTK 09/23/10 11/12/10 *I 3200275 BTK 03/18/11 Document Number: 001-55397 Rev. *I Page 35 of 36 [+] Feedback CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-55397 Rev. *I Revised March 18, 2011 Page 36 of 36 PSoC Designer™ is a trademark and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback