CY8C24223A, CY8C24423A
®
Automotive PSoC
Programmable System-on-Chip
Features
■
Automotive Electronics Council (AEC) Q100 qualified
■
Powerful Harvard-architecture processor
❐ M8C processor speeds up to 24 MHz
❐ 8 × 8 multiply, 32-bit accumulate
❐ Low power at high speed
❐ Operating voltage: 3.0 V to 5.25 V
❐ Automotive temperature range: –40 °C to +85 °C
■
■
■
■
Advanced peripherals (PSoC® blocks)
❐ Six rail-to-rail analog PSoC blocks provide:
• Up to 14-bit analog-to-digital converters (ADCs)
• Up to 9-bit digital-to-analog converters (DACs)
• Programmable gain amplifiers (PGAs)
• Programmable filters and comparators
❐ Four digital PSoC blocks provide:
• 8- to 32-bit timers, counters, and pulse width modulators
(PWMs)
• Cyclical redundancy check (CRC) and pseudo-random sequence (PRS) modules
• Full- or half-duplex UART
• SPI master or slave
• Connectable to all general purpose I/O (GPIO) pins
❐ Complex peripherals by combining blocks
■
Additional system resources
2
❐ Inter-Integrated Circuit (I C™) slave, master, or multimaster
operation up to 400 kHz
❐ Watchdog and sleep timers
❐ User-configurable low-voltage detection (LVD)
❐ Integrated supervisory circuit
❐ On-chip precision voltage reference
■
Complete development tools
❐ Free development software (PSoC Designer™)
❐ Full featured, in-circuit emulator (ICE) and programmer
❐ Full-speed emulation
❐ Complex breakpoint structure
❐ 128 KB trace memory
Logic Block Diagram
Precision, programmable clocking
❐ Internal ±5% 24- and 48-MHz oscillator
❐ High accuracy 24 MHz with optional 32-kHz crystal and
phase-locked loop (PLL)
❐ Optional external oscillator, up to 24 MHz
❐ Internal low-speed, low-power oscillator for watchdog and
sleep functionality
Port 2
Port 0
Analog
Drivers
PSoC CORE
System Bus
Global Digital Interconnect
SRAM
256 Bytes
SROM
Global Analog Interconnect
Flash 4 KB
CPU Core (M8C)
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Flexible on-chip memory
❐ 4 KB flash program storage, 1000 erase/write cycles
❐ 256 bytes SRAM data storage
❐ In-system serial programming (ISSP)
❐ Partial flash updates
❐ Flexible protection modes
❐ EEPROM emulation in flash
Programmable pin configurations
❐ 25 mA sink, 10 mA source on all GPIOs
❐ Pull-up, pull-down, high Z, strong, or open drain drive modes
on all GPIOs
[1]
❐ Up to 12 analog inputs on GPIOs
❐ Two 30 mA analog outputs on GPIOs
❐ Configurable interrupt on all GPIOs
Port 1
Digital
Clocks
ANALOG SYSTEM
Digital
Block
Array
Analog
Block
Array
(1 Row,
4 Blocks)
(2 Columns,
6 Blocks)
Multiply
Accum.
Decimator
I2C
Analog
Ref
Analog
Input
Muxing
POR and LVD
System Resets
Internal
Voltage
Ref.
SYSTEM RESOURCES
Note
1. There are eight standard analog inputs on the GPIO. The other four analog inputs connect from the GPIO directly to specific switched-capacitor block inputs. See
the PSoC Technical Reference Manual for more details.
Cypress Semiconductor Corporation
Document Number: 001-52469 Rev. *J
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 8, 2017
CY8C24223A, CY8C24423A
Contents
PSoC Functional Overview .............................................. 3
PSoC Core .................................................................. 3
Digital System ............................................................. 3
Analog System ............................................................ 4
Additional System Resources ..................................... 5
PSoC Device Characteristics ...................................... 5
Getting Started .................................................................. 6
Application Notes ........................................................ 6
Development Kits ........................................................ 6
Training ....................................................................... 6
CYPros Consultants .................................................... 6
Solutions Library .......................................................... 6
Technical Support ....................................................... 6
Development Tools .......................................................... 6
PSoC Designer Software Subsystems ........................ 6
Designing with PSoC Designer ....................................... 7
Select Components ..................................................... 7
Configure Components ............................................... 7
Organize and Connect ................................................ 7
Generate, Verify, and Debug ....................................... 7
Pinouts .............................................................................. 8
20-Pin Part Pinout ...................................................... 8
28-Pin Part Pinout ...................................................... 9
Registers ......................................................................... 10
Register Conventions ................................................ 10
Register Mapping Tables .......................................... 10
Electrical Specifications ................................................ 13
Absolute Maximum Ratings ....................................... 14
Operating Temperature ............................................ 14
Document Number: 001-52469 Rev. *J
DC Electrical Characteristics ..................................... 15
AC Electrical Characteristics ..................................... 27
Packaging Information ................................................... 36
Packaging Dimensions .............................................. 36
Thermal Impedances ................................................ 37
Capacitance on Crystal Pins .................................... 37
Solder Reflow Specifications ..................................... 37
Tape and Reel Information ........................................ 38
Development Tool Selection ......................................... 40
Software .................................................................... 40
Development Kits ...................................................... 40
Evaluation Tools ........................................................ 40
Device Programmers ................................................. 40
Accessories (Emulation and Programming) .............. 41
Ordering Information ...................................................... 42
Ordering Code Definitions ......................................... 42
Reference Information ................................................... 43
Acronyms .................................................................. 43
Reference Documents ............................................... 43
Document Conventions ............................................. 44
Glossary .................................................................... 44
Document History Page ................................................. 49
Sales, Solutions, and Legal Information ...................... 51
Worldwide Sales and Design Support ....................... 51
Products .................................................................... 51
PSoC® Solutions ...................................................... 51
Cypress Developer Community ................................. 51
Technical Support ..................................................... 51
Page 2 of 51
CY8C24223A, CY8C24423A
The PSoC family consists of many programmable
system-on-chips with on-chip Controller devices. These devices
are designed to replace multiple traditional microcontroller unit
(MCU)-based system components with one, low cost single-chip
programmable device. PSoC devices include configurable
blocks of analog and digital logic, and programmable
interconnects. This architecture makes it possible for the user to
create customized peripheral configurations that match the
requirements of each individual application. Additionally, a fast
central processing unit (CPU), flash program memory, SRAM
data memory, and configurable I/O are included in a range of
convenient pinouts and packages.
Digital System
The digital system is composed of four digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8-, 16-, 24-, and 32-bit peripherals,
which are called user modules.
Figure 1. Digital System Block Diagram
Port 1
Port 2
The PSoC architecture, as shown in the Logic Block Diagram on
page 1, is comprised of four main areas: PSoC core, digital
system, analog system, and system resources. Configurable
global buses allow all the device resources to be combined into
a complete custom system. Each CY8C24x23A PSoC device
includes four digital blocks and six analog blocks. Depending on
the PSoC package, up to 24 GPIOs are also included. The
GPIOs provide access to the global digital and analog
interconnects.
8
8
PSoC GPIOs provide connection to the CPU, digital, and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system
interrupt.
Document Number: 001-52469 Rev. *J
Row 0
DBB00
DBB01
DCB02
4
DCB03
4
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
8
Row Output
Configuration
The PSoC device incorporates flexible internal clock generators,
including a 24-MHz internal main oscillator (IMO) accurate to
±5% over temperature and voltage. A low-power 32-kHz internal
low-speed oscillator (ILO) is provided for the sleep timer and
WDT. If crystal accuracy is desired, the 32.768-kHz external
crystal oscillator (ECO) is available for use as a real time clock
(RTC) and can optionally generate a crystal-accurate 24-MHz
system clock using a PLL. The clocks, together with
programmable clock dividers (as a system resource), provide the
flexibility to integrate almost any timing requirement into the
PSoC device.
To Analog
System
DIGITAL SYSTEM
The PSoC core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPIO.
Memory includes 4 KB of flash for program storage and 256
bytes of SRAM for data storage. Program flash uses four
protection levels on blocks of 64 bytes, allowing customized
software IP protection.
To System Bus
Digital PSoC Block Array
PSoC Core
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a four-million instructions per second (MIPS)
8-bit Harvard-architecture microprocessor. The CPU uses an
interrupt controller with multiple vectors, to simplify programming
of real time embedded events. Program execution is timed and
protected using the included sleep timer and watchdog timer
(WDT).
Port 0
Digital Clocks
From Core
Row Input
Configuration
PSoC Functional Overview
8
GOE[7:0]
GOO[7:0]
Digital peripheral configurations include:
■
PWMs (8- to 32-bit)
■
PWMs with dead band (8- to 24-bit)
■
Counters (8- to 32-bit)
■
Timers (8- to 32-bit)
■
Full- or half-duplex 8-bit UART with selectable parity
■
SPI master and slave
■
I2C master, slave, or multimaster (implemented in a dedicated
I2C block)
■
Cyclical redundancy checker/generator (16-bit)
■
Infrared Data Association (IrDA)
■
PRS generators (8- to 32-bit)
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows the optimum
choice of system resources for your application. Family
resources are shown in Table 1 on page 5.
Page 3 of 51
CY8C24223A, CY8C24423A
The analog system is composed of six configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the common PSoC analog functions for this device
(most available as user modules) are:
■
ADCs (up to two, with 6- to 14-bit resolution, selectable as
incremental, delta-sigma, or successive approximation register
(SAR))
■
Filters (two- and four-pole band pass, low pass, and notch)
■
Amplifiers (up to two, with selectable gain up to 48x)
■
Instrumentation amplifiers (one with selectable gain up to 93x)
■
Comparators (up to two, with 16 selectable thresholds)
■
DACs (up to two, with 6- to 9-bit resolution)
■
Multiplying DACs (up to two, with 6- to 9-bit resolution)
■
High current output drivers (two with 30-mA drive)
■
1.3 V reference (as a system resource)
■
DTMF dialer
■
Modulators
■
Correlators
■
Peak detectors
■
Many other topologies possible
Figure 2. Analog System Block Diagram
P0[7]
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
P0[1]
P0[0]
AGNDIn RefIn
Analog System
P2[6]
P2[4]
P2[3]
P2[2]
P2[1]
P2[0]
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
Block Array
Analog blocks are arranged in a column of three, which includes
one continuous time (CT) and two switched capacitor (SC)
blocks, as shown in Figure 2.
ACB00
ACB01
ASC10
ASD11
ASD20
ASC22
Analog Reference
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
BandGap
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 001-52469 Rev. *J
Page 4 of 51
CY8C24223A, CY8C24423A
Additional System Resources
System resources, some of which have been previously listed,
provide additional capability useful for complete systems.
Additional resources include a multiplier, decimator, low voltage
detection, and power-on reset (POR). Brief statements
describing the merits of each system resource follow:
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
■
A multiply accumulate (MAC) provides a fast 8-bit multiplier
with 32-bit accumulate, to assist in both general math as well
as digital filters.
■
■
The decimator provides a custom hardware filter for digital
signal processing applications including the creation of
delta-sigma ADCs.
The I2C module provides 0 to 400 kHz communication over two
wires. Slave, master, and multimaster modes are all supported.
■
LVD interrupts can signal the application of falling voltage
levels, while the advanced POR circuit eliminates the need for
a system supervisor.
■
An internal 1.3-V voltage reference provides an absolute
reference for the analog system, including ADCs and DACs.
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and analog systems can have varying numbers of digital and analog
blocks. The following table lists the resources available for specific PSoC device groups. The device covered by this data sheet is
shown in the highlighted row of the table.
Table 1. PSoC Device Characteristics
PSoC Part
Number
Digital
I/O
CY8C29x66[2]
up to 64
CY8C28xxx
up to 44
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Outputs
4
16
up to 12
4
up to 3
up to 12
up to 44
up to 4
Analog
Columns
Analog
Blocks
SRAM
Size
Flash
Size
4
12
2K
32 K
up to 6
up to
12 + 4[3]
1K
16 K
CY8C27x43
up to 44
2
8
up to 12
4
4
12
256
16 K
CY8C24x94[2]
up to 56
1
4
up to 48
2
2
6
1K
16 K
CY8C24x23A[2]
up to 24
1
4
up to 12
2
2
6
256
4K
CY8C23x33
up to 26
1
4
up to 12
2
2
4
256
8K
CY8C22x45[2]
up to 38
2
8
up to 38
0
4
6[3]
1K
16 K
CY8C21x45[2]
up to 24
1
4
up to 24
0
4
6[3]
512
8K
CY8C21x34[2]
up to 28
1
4
up to 28
0
2
4[3]
512
8K
CY8C21x23
up to 16
1
4
up to 8
0
2
4[3]
256
4K
[3,4]
CY8C20x34
[2]
CY8C20xx6
up to 28
0
0
up to 28
0
0
3
up to 36
0
0
up to 36
0
0
3[3,4]
512
8K
up to 2 K
up to 32 K
Notes
2. Automotive qualified devices available in this group.
3. Limited analog functionality.
4. Two analog blocks and one CapSense® block.
Document Number: 001-52469 Rev. *J
Page 5 of 51
CY8C24223A, CY8C24423A
Getting Started
■
Built-in debugger
For in-depth information, along with detailed programming
details, see the PSoC® Technical Reference Manual.
■
In-circuit emulation
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device datasheets on the web.
Application Notes
Cypress application notes are an excellent introduction to the
wide variety of possible PSoC designs.
Development Kits
PSoC Development Kits are available online from and through a
growing number of regional and global distributors, which
include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and
Newark.
Training
Free PSoC technical training (on demand, webinars, and
workshops), which is available online via www.cypress.com,
covers a wide variety of topics and skill levels to assist you in
your designs.
CYPros Consultants
Certified PSoC consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC consultant go to the CYPros Consultants web site.
Solutions Library
Visit our growing library of solution focused designs. Here you
can find various application designs that include firmware and
hardware design files that enable you to complete your designs
quickly.
Technical Support
Technical support – including a searchable Knowledge Base
articles and technical forums – is also available online. If you
cannot find an answer to your question, call our Technical
Support hotline at 1-800-541-4736.
Development Tools
PSoC Designer™ is the revolutionary integrated design
environment (IDE) that you can use to customize PSoC to meet
your specific application requirements. PSoC Designer software
accelerates system design and time to market. Develop your
applications using a library of precharacterized analog and digital
peripherals (called user modules) in a drag-and-drop design
environment. Then, customize your design by leveraging the
dynamically generated application programming interface (API)
libraries of code. Finally, debug and test your designs with the
integrated debug environment, including in-circuit emulation and
standard software debug features. PSoC Designer includes:
Built-in support for communication interfaces:
2
❐ Hardware and software I C slaves and masters
❐ Full-speed USB 2.0
❐ Up to four full-duplex universal asynchronous
receiver/transmitters (UARTs), SPI master and slave, and
wireless
PSoC Designer supports the entire library of PSoC 1 devices and
runs on Windows XP, Windows Vista, and Windows 7.
■
PSoC Designer Software Subsystems
Design Entry
In the chip-level view, choose a base device to work with. Then
select different onboard analog and digital components that use
the PSoC blocks, which are called user modules. Examples of
user modules are ADCs, DACs, amplifiers, and filters. Configure
the user modules for your chosen application and connect them
to each other and to the proper pins. Then generate your project.
This prepopulates your project with APIs and libraries that you
can use to program your application.
The tool also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
reconfiguration makes it possible to change configurations at run
time. In essence, this allows you to use more than 100 percent
of PSoC's resources for an application.
Code Generation Tools
The code generation tools work seamlessly within the
PSoC Designer interface and have been tested with a full range
of debugging tools. You can develop your design in C, assembly,
or a combination of the two.
Assemblers. The assemblers allow you to merge assembly
code seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and are
linked with other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices. The
optimizing C compilers provide all of the features of C, tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
■
Application editor graphical user interface (GUI) for device and
user module configuration and dynamic reconfiguration
■
Extensive user module catalog
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow you to read and program and
read and write data memory, and read and write I/O registers.
You can read and write CPU registers, set and clear breakpoints,
and provide program run, halt, and step control. The debugger
also allows you to create a trace buffer of registers and memory
locations of interest.
■
Integrated source-code editor (C and assembly)
Online Help System
■
Free C compiler with no size restrictions or time limits
The online help system displays online, context-sensitive help.
Designed for procedural and quick reference, each functional
Document Number: 001-52469 Rev. *J
Page 6 of 51
CY8C24223A, CY8C24423A
subsystem has its own context-sensitive help. This system also
provides tutorials and links to FAQs and an online support Forum
to aid the designer.
In-Circuit Emulator
A low-cost, high-functionality in-circuit emulator (ICE) is
available for development support. This hardware can program
single devices.
The emulator consists of a base unit that connects to the PC
using a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full-speed
(24 MHz) operation.
Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
The PSoC development process can be summarized in the
following four steps:
1. Select User Modules
2. Configure User Modules
3. Organize and Connect
4. Generate, Verify, and Debug
Select Components
PSoC Designer provides a library of pre-built, pre-tested
hardware peripheral components called "user modules." User
modules make selecting and implementing peripheral devices,
both analog and digital, simple.
Configure Components
Each of the User Modules you select establishes the basic
register settings that implement the selected function. They also
provide parameters and properties that allow you to tailor their
Document Number: 001-52469 Rev. *J
precise configuration to your particular application. For example,
a PWM User Module configures one or more
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by
selecting values from drop-down menus. All the user modules
are documented in datasheets that may be viewed directly in
PSoC Designer or on the Cypress website. These user module
datasheets explain the internal operation of the User Module and
provide performance specifications. Each datasheet describes
the use of each user module parameter, and other information
you may need to successfully implement your design.
Organize and Connect
You build signal chains at the chip level by interconnecting user
modules to each other and the I/O pins. You perform the
selection, configuration, and routing so that you have complete
control over all on-chip resources.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, you perform the "Generate
Configuration Files" step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system. The
generated code provides application programming interfaces
(APIs) with high-level functions to control and respond to
hardware events at run time and interrupt service routines that
you can adapt as needed.
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
The last step in the development process takes place inside
PSoC Designer's Debugger (access by clicking the Connect
icon). PSoC Designer downloads the HEX image to the ICE
where it runs at full speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition
to traditional single-step, run-to-breakpoint and watch-variable
features, the debug interface provides a large trace buffer and
allows you to define complex breakpoint events that include
monitoring address and data bus values, memory locations and
external signals.
Page 7 of 51
CY8C24223A, CY8C24423A
Pinouts
The automotive CY8C24x23A PSoC device is available in a variety of packages which are listed and illustrated in the following tables.
Every port pin (labeled with a “P”) is capable of digital I/O. However, VSS, VDD, and XRES are not capable of digital I/O.
20-Pin Part Pinout
Table 2. 20-Pin Part Pinout (Shrink Small-Outline Package (SSOP))
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Type
Pin
Description
Digital Analog Name
I/O
I
P0[7] Analog column mux input
I/O
I/O
P0[5] Analog column mux input and column
output
I/O
I/O
P0[3] Analog column mux input and column
output
I/O
I
P0[1] Analog column mux input
Power
VSS
Ground connection
I/O
P1[7] I2C serial clock (SCL)
I/O
P1[5] I2C serial data (SDA)
I/O
P1[3]
I/O
P1[1] Crystal input (XTALin), I2C serial clock
(SCL), ISSP-SCLK[5]
Power
VSS
Ground connection
I/O
P1[0] Crystal output (XTALout), I2C serial data
(SDA), ISSP-SDATA[5]
I/O
P1[2]
I/O
P1[4] Optional external clock input (EXTCLK)
I/O
P1[6]
Input
XRES Active high external reset with internal pull
down
I/O
I
P0[0] Analog column mux input
I/O
I
P0[2] Analog column mux input
I/O
I
P0[4] Analog column mux input
I/O
I
P0[6] Analog column mux input
Power
VDD
Supply voltage
Figure 3. CY8C24223A 20-Pin PSoC Device
AI, P0[7]
AIO, P0[5]
AIO, P0[3]
AI, P0[1]
VSS
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
VSS
1
2
3
4
5
6
7
8
9
10
SSOP
20
19
18
17
16
15
14
13
12
11
VDD
P0[6], AI
P0[4], AI
P0[2], AI
P0[0], AI
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA
LEGEND: A = Analog, I = Input, and O = Output.
Note
5. These are the ISSP pins, which are not high Z when coming out of POR. See the PSoC Technical Reference Manual for details.
Document Number: 001-52469 Rev. *J
Page 8 of 51
CY8C24223A, CY8C24423A
28-Pin Part Pinout
Table 3. 28-Pin Part Pinout (SSOP)
Type
Pin
Pin
Description
No. Digital Analog Name
1
I/O
I
P0[7] Analog column mux input
2
I/O
I/O
P0[5] Analog column mux input and column
output
3
I/O
I/O
P0[3] Analog column mux input and column
output
4
I/O
I
P0[1] Analog column mux input
5
I/O
P2[7]
6
I/O
P2[5]
7
I/O
I
P2[3] Direct switched capacitor block input
8
I/O
I
P2[1] Direct switched capacitor block input
9
Power
VSS
Ground connection
10
I/O
P1[7] I2C serial clock (SCL)
11
I/O
P1[5] I2C serial data (SDA)
12
I/O
P1[3]
13
I/O
P1[1] Crystal input (XTALin), I2C serial clock
(SCL), ISSP-SCLK[6]
14
Power
VSS
Ground connection
15
I/O
P1[0] Crystal output (XTALout), I2C serial data
(SDA), ISSP-SDATA[6]
16
I/O
P1[2]
17
I/O
P1[4] Optional external clock input (EXTCLK)
18
I/O
P1[6]
19
Input
XRES Active high external reset with internal
pull down
20
I/O
I
P2[0] Direct switched capacitor block input
21
I/O
I
P2[2] Direct switched capacitor block input
22
I/O
P2[4] External analog ground (AGND)
23
I/O
P2[6] External voltage reference (VRef)
24
I/O
I
P0[0] Analog column mux input
25
I/O
I
P0[2] Analog column mux input
26
I/O
I
P0[4] Analog column mux input
27
I/O
I
P0[6] Analog column mux input
28
Power
VDD
Supply voltage
Figure 4. CY8C24423A 28-Pin PSoC Device
AI, P0[7]
AIO, P0[5]
AIO, P0[3]
AI, P0[1]
P2[7]
P2[5]
AI, P2[3]
AI, P2[1]
VSS
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
P0[6], AI
P0[4], AI
P0[2], AI
P0[0], AI
P2[6], External VRef
P2[4], External AGND
P2[2], AI
P2[0], AI
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA
LEGEND: A = Analog, I = Input, and O = Output.
Note
6. These are the ISSP pins, which are not high Z when coming out of POR. See the PSoC Technical Reference Manual for details.
Document Number: 001-52469 Rev. *J
Page 9 of 51
CY8C24223A, CY8C24423A
Registers
Register Conventions
Register Mapping Tables
This section lists the registers of the automotive CY8C24x23A
PSoC device. For detailed register information, refer to the PSoC
Technical Reference Manual.
The PSoC device has a total register address space of 512
bytes. The register space is referred to as I/O space and is
divided into two banks, bank 0 and bank 1. The XIO bit in the
Flag register (CPU_F) determines which bank the user is
currently in. When the XIO bit is set to ‘1’, the user is in bank 1.
The register conventions specific to this section are listed in the
following table.
Table 4. Abbreviations
Convention
R
Note In the following register mapping tables, blank fields are
Reserved and must not be accessed.
Description
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
Document Number: 001-52469 Rev. *J
Page 10 of 51
CY8C24223A, CY8C24423A
Table 5. Register Map Bank 0 Table: User Space
Name
PRT0DR
PRT0IE
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
Addr (0,Hex) Access
Name
Addr (0,Hex)
00
RW
40
01
RW
41
02
RW
42
03
RW
43
04
RW
44
05
RW
45
06
RW
46
07
RW
47
08
RW
48
09
RW
49
0A
RW
4A
0B
RW
4B
0C
4C
0D
4D
0E
4E
0F
4F
10
50
11
51
12
52
13
53
14
54
15
55
16
56
17
57
18
58
19
59
1A
5A
1B
5B
1C
5C
1D
5D
1E
5E
1F
5F
DBB00DR0
20
#
AMX_IN
60
DBB00DR1
21
W
61
DBB00DR2
22
RW
62
DBB00CR0
23
#
ARF_CR
63
DBB01DR0
24
#
CMP_CR0
64
DBB01DR1
25
W
ASY_CR
65
DBB01DR2
26
RW
CMP_CR1
66
DBB01CR0
27
#
67
DCB02DR0
28
#
68
DCB02DR1
29
W
69
DCB02DR2
2A
RW
6A
DCB02CR0
2B
#
6B
DCB03DR0
2C
#
6C
DCB03DR1
2D
W
6D
DCB03DR2
2E
RW
6E
DCB03CR0
2F
#
6F
30
ACB00CR3
70
31
ACB00CR0
71
32
ACB00CR1
72
33
ACB00CR2
73
34
ACB01CR3
74
35
ACB01CR0
75
36
ACB01CR1
76
37
ACB01CR2
77
38
78
39
79
3A
7A
3B
7B
3C
7C
3D
7D
3E
7E
3F
7F
Blank fields are Reserved and must not be accessed.
Document Number: 001-52469 Rev. *J
Access
RW
RW
#
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
Addr (0,Hex)
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
ASD20CR0
90
ASD20CR1
91
ASD20CR2
92
ASD20CR3
93
ASC21CR0
94
ASC21CR1
95
ASC21CR2
96
ASC21CR3
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
RDI0RI
B0
RDI0SYN
B1
RDI0IS
B2
RDI0LT0
B3
RDI0LT1
B4
RDI0RO0
B5
RDI0RO1
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
# Access is bit specific.
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
I2C_CFG
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
INT_CLR3
INT_MSK3
INT_MSK0
INT_MSK1
INT_VC
RES_WDT
DEC_DH
DEC_DL
DEC_CR0
DEC_CR1
MUL_X
MUL_Y
MUL_DH
MUL_DL
ACC_DR1
ACC_DR0
ACC_DR3
ACC_DR2
RW
RW
RW
RW
RW
RW
RW
CPU_F
CPU_SCR1
CPU_SCR0
Addr (0,Hex)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Access
RW
#
RW
#
RW
RW
RW
RW
RW
RW
RC
W
RC
RC
RW
RW
W
W
R
R
RW
RW
RW
RW
RL
#
#
Page 11 of 51
CY8C24223A, CY8C24423A
Table 6. Register Map Bank 1 Table: Configuration Space
Name
PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
Addr (1,Hex) Access
Name
Addr (1,Hex)
00
RW
40
01
RW
41
02
RW
42
03
RW
43
04
RW
44
05
RW
45
06
RW
46
07
RW
47
08
RW
48
09
RW
49
0A
RW
4A
0B
RW
4B
0C
4C
0D
4D
0E
4E
0F
4F
10
50
11
51
12
52
13
53
14
54
15
55
16
56
17
57
18
58
19
59
1A
5A
1B
5B
1C
5C
1D
5D
1E
5E
1F
5F
DBB00FN
20
RW
CLK_CR0
60
DBB00IN
21
RW
CLK_CR1
61
DBB00OU
22
RW
ABF_CR0
62
23
AMD_CR0
63
DBB01FN
24
RW
64
DBB01IN
25
RW
65
DBB01OU
26
RW
AMD_CR1
66
27
ALT_CR0
67
DCB02FN
28
RW
68
DCB02IN
29
RW
69
DCB02OU
2A
RW
6A
2B
6B
DCB03FN
2C
RW
6C
DCB03IN
2D
RW
6D
DCB03OU
2E
RW
6E
2F
6F
30
ACB00CR3
70
31
ACB00CR0
71
32
ACB00CR1
72
33
ACB00CR2
73
34
ACB01CR3
74
35
ACB01CR0
75
36
ACB01CR1
76
37
ACB01CR2
77
38
78
39
79
3A
7A
3B
7B
3C
7C
3D
7D
3E
7E
3F
7F
Blank fields are Reserved and must not be accessed.
Document Number: 001-52469 Rev. *J
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
Addr (1,Hex)
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
ASD20CR0
90
ASD20CR1
91
ASD20CR2
92
ASD20CR3
93
ASC21CR0
94
ASC21CR1
95
ASC21CR2
96
ASC21CR3
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
RDI0RI
B0
RDI0SYN
B1
RDI0IS
B2
RDI0LT0
B3
RDI0LT1
B4
RDI0RO0
B5
RDI0RO1
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
# Access is bit specific.
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
GDI_O_IN
GDI_E_IN
GDI_O_OU
GDI_E_OU
OSC_GO_EN
OSC_CR4
OSC_CR3
OSC_CR0
OSC_CR1
OSC_CR2
VLT_CR
VLT_CMP
IMO_TR
ILO_TR
BDG_TR
ECO_TR
RW
RW
RW
RW
RW
RW
RW
CPU_F
CPU_SCR1
CPU_SCR0
Addr (1,Hex)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
W
W
RW
W
RL
#
#
Page 12 of 51
CY8C24223A, CY8C24423A
Electrical Specifications
This section presents the DC and AC electrical specifications of the automotive CY8C24x23A PSoC devices. For the latest electrical
specifications, visit http://www.cypress.com.
Specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted.
Refer to Table 21 on page 27 for the electrical specifications of the IMO using slow IMO (SLIMO) mode.
Figure 5. Voltage versus CPU Frequency
Figure 6. IMO Frequency Trim Options
5.25
5.25
lid ing
Va rat n
pe io
O eg
R
SLIMO
Mode = 0
SLIMO
Mode = 1
SLIMO
Mode = 0
4.75
VDD Voltage (V)
VDD Voltage (V)
4.75
SLIMO
Mode = 1
3.0
3.6
3.0
0
0
93 kHz
12 MHz
CPU Frequency
(nominal setting)
Document Number: 001-52469 Rev. *J
24 MHz
6 MHz
12 MHz
24 MHz
IMO Frequency
Page 13 of 51
CY8C24223A, CY8C24423A
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Table 7. Absolute Maximum Ratings
Symbol
TSTG
Description
Storage temperature
TBAKETEMP Bake temperature
tBAKETIME
Bake time
TA
VDD
VIO
VIOZ
IMIO
ESD
LU
Ambient temperature with power applied
Supply voltage on VDD relative to VSS
DC input voltage
DC voltage applied to tristate
Maximum current into any port pin
Electrostatic discharge voltage
Latch up current
Min
–55
Typ
25
Max
+100
Units
Notes
°C Higher storage temperatures
reduce data retention time.
Recommended storage
temperature is +25 °C ± 25 °C.
Time spent in storage at a
temperature greater than 65 °C
counts toward the FlashDR
electrical specification in Table
20 on page 26.
C
–
125
See
package
label
–40
–0.5
VSS – 0.5
VSS – 0.5
–25
2000
–
–
See
package
label
72
Hours
–
–
–
–
–
–
–
+85
+6.0
VDD + 0.5
VDD + 0.5
+50
–
200
°C
V
V
V
mA
V
mA
Human body model ESD.
Operating Temperature
Table 8. Operating Temperature
Symbol
TA
TJ
Description
Ambient temperature
Junction temperature
Document Number: 001-52469 Rev. *J
Min
–40
–40
Typ
–
–
Max
+85
+100
Units
Notes
°C
°C The temperature rise from
ambient to junction is package
specific. See Table 33 on page 37.
The user must limit the power
consumption to comply with this
requirement.
Page 14 of 51
CY8C24223A, CY8C24423A
DC Electrical Characteristics
DC Chip-Level Specifications
Table 9 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and
are for design guidance only.
Table 9. DC Chip-Level Specifications
Symbol
Description
VDD
Supply voltage
Min
3.0
Typ
–
Max
5.25
IDD
Supply current
–
5
8
IDD3
Supply current
–
3.3
6.0
ISB
Sleep (mode) current with POR, LVD, sleep
timer, and WDT.[7]
Sleep (mode) current with POR, LVD, sleep
timer, and WDT at high temperature.[7]
Sleep (mode) current with POR, LVD, sleep
timer, WDT, and external crystal.[7]
–
3
6.5
–
4
25
–
4
7.5
ISBXTLH Sleep (mode) current with POR, LVD, sleep
timer, WDT, and external crystal at high
temperature.[7]
–
5
26
1.28
1.30
1.32
ISBH
ISBXTL
VREF
Reference voltage (bandgap)
Units
Notes
V
See DC POR and LVD specifications,
Table 19 on page 25.
mA Conditions are VDD = 5.0 V,
CPU = 3 MHz, 48 MHz disabled,
VC1 = 1.5 MHz, VC2 = 93.75 kHz,
VC3 = 93.75 kHz, analog power = off.
IMO = 24 MHz.
mA Conditions are VDD = 3.3 V,
CPU = 3 MHz, 48 MHz disabled,
VC1 = 1.5 MHz, VC2 = 93.75 kHz,
VC3 = 93.75 kHz, Analog power = off.
IMO = 24 MHz.
A VDD = 3.3 V, –40 °C TA 55 °C,
Analog power = off.
A VDD = 3.3 V, 55 °C < TA 85 °C,
Analog power = off.
A Conditions are with properly loaded,
1 W max, 32.768 kHz crystal.
VDD = 3.3 V, –40 °C TA 55 °C,
Analog power = off.
A Conditions are with properly loaded,
1 W max, 32.768 kHz crystal.
VDD = 3.3 V, 55 °C < TA 85 °C,
Analog power = off.
V
Trimmed for appropriate VDD.
Note
7. Standby current includes all functions (POR, LVD, WDT, sleep timer) needed for reliable system operation. This must be compared with devices that have similar
functions enabled.
Document Number: 001-52469 Rev. *J
Page 15 of 51
CY8C24223A, CY8C24423A
DC GPIO Specifications
Table 10 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and
are for design guidance only.
Table 10. DC GPIO Specifications
Min
Typ
Max
Units
RPU
Symbol
Pull-up resistor
Description
4
5.6
8
k
Notes
RPD
Pull-down resistor
4
5.6
8
k
VOH
High output level
VDD – 1.0
–
–
V
IOH = 10 mA, VDD = 4.75 to 5.25 V
(maximum 40 mA on even port pins (for
example, P0[2], P1[4]), maximum 40 mA
on odd port pins (for example, P0[3],
P1[5])). 80 mA maximum combined IOH
budget.
VOL
Low output level
–
–
0.75
V
IOL = 25 mA, VDD = 4.75 to 5.25 V
(maximum 100 mA on even port pins (for
example, P0[2], P1[4]), maximum 100 mA
on odd port pins (for example, P0[3],
P1[5])). 150 mA maximum combined IOL
budget.
IOH
High-level source current
10
–
–
mA
VOH VDD – 1.0 V, see the limitations of
the total current in the note for VOH.
IOL
Low-level sink current
25
–
–
mA
VOL 0.75 V, see the limitations of the total
current in the note for VOL.
0.8
Also applies to the internal pull-down
resistor on the XRES pin.
VIL
Input low level
–
–
VIH
Input high level
2.1
–
VH
Input hysteresis
–
60
–
mV
IIL
Input leakage (absolute value)
–
1
–
nA
Gross tested to 1 A.
CIN
Capacitive load on pins as input
–
3.5
10
pF
Package and pin dependent.
TA = 25 °C
COUT
Capacitive load on pins as output
–
3.5
10
pF
Package and pin dependent.
TA = 25 °C
Document Number: 001-52469 Rev. *J
V
V
Page 16 of 51
CY8C24223A, CY8C24423A
DC Operational Amplifier Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at
25 °C and are for design guidance only.
The operational amplifier is a component of both the analog CT PSoC blocks and the analog SC PSoC blocks. The guaranteed
specifications are measured in the analog CT PSoC block.
Table 11. 5-V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Input offset voltage (absolute value)
Power = low, Opamp bias = high
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
TCVOSOA Average input offset voltage drift
Input leakage current (Port 0 analog pins)
IEBOA
CINOA
Input capacitance (Port 0 analog pins)
VCMOA
Common mode voltage range
Common mode voltage range (high power or
high opamp bias)
GOLOA
Open loop gain
Power = low, Opamp bias = high
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
VOHIGHOA High output voltage swing (internal signals)
Power = low, Opamp bias = high
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
VOLOWOA Low output voltage swing (internal signals)
Power = low, Opamp bias = high
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
ISOA
Supply current (including associated AGND
buffer)
Power = low, Opamp bias = high
Power = low, Opamp bias = high
Power = medium, Opamp bias = high
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
Power = high, Opamp bias = high
PSRROA Supply voltage rejection ratio
Document Number: 001-52469 Rev. *J
Min
Typ
Max
Units
–
–
–
–
–
–
1.6
1.3
1.2
10
8
7.5
mV
mV
mV
0.0
0.5
–
–
60
60
80
–
–
–
VDD – 0.2
VDD – 0.2
VDD – 0.5
–
–
–
–
–
–
V
V
V
–
–
–
–
–
–
0.2
0.2
0.5
V
V
V
–
–
–
–
–
–
64
150
300
600
1200
2400
4600
80
200
400
800
1600
3200
6400
–
A
A
A
A
A
A
dB
7.0
20
4.5
Notes
V/°C
pA Gross tested to 1 A.
pF Package and pin dependent.
TA = 25 °C.
V
The common-mode input voltage
VDD
VDD – 0.5
V
range is measured through an
analog output buffer. The
specification includes the
limitations imposed by the
characteristics of the analog
output buffer.
Specification is applicable at high
–
dB power. For all other bias modes
–
dB (except high power, high opamp
–
dB bias), minimum is 60 dB.
35.0
–
9.5
VSS VIN (VDD – 2.25 V) or
(VDD – 1.25 V) VIN VDD.
Page 17 of 51
CY8C24223A, CY8C24423A
Table 12. 3.3-V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Input offset voltage (absolute value)
Power = low, Opamp bias = high
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
Min
Typ
Max
Units
–
–
–
1.65
1.32
–
10
8
–
mV
mV
mV
TCVOSOA Average input offset voltage drift
–
7.0
35.0
V/°C
Notes
Power = high, Opamp bias = high
is not allowed.
IEBOA
Input leakage current (Port 0 analog pins)
–
20
–
pA
Gross tested to 1 A.
CINOA
Input capacitance (Port 0 analog pins)
–
4.5
9.5
pF
Package and pin dependent.
TA = 25 °C
VCMOA
Common mode voltage range
0.2
–
VDD – 0.2
V
The common-mode input voltage
range is measured through an
analog output buffer. The
specification includes the
limitations imposed by the
characteristics of the analog
output buffer.
GOLOA
Open loop gain
Power = low, Opamp bias = low
Power = medium, Opamp bias = low
Power = high, Opamp bias = low
60
60
80
–
–
–
–
–
–
dB
dB
dB
VOHIGHOA High output voltage swing (internal signals)
Power = low, Opamp bias = low
Power = medium, Opamp bias = low
Power = high, Opamp bias = low
VDD – 0.2
VDD – 0.2
VDD – 0.2
–
–
–
–
–
–
V
V
V
VOLOWOA Low output voltage swing (internal signals)
Power = low, Opamp bias = low
Power = medium, Opamp bias = low
Power = high, Opamp bias = low
–
–
–
–
–
–
0.2
0.2
0.2
V
V
V
ISOA
PSRROA
Supply current (including associated AGND
buffer)
Power = low, Opamp bias = low
Power = low, Opamp bias = high
Power = medium, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = low
Power = high, Opamp bias = high
–
–
–
–
–
–
150
300
600
1200
2400
–
200
400
800
1600
3200
–
A
A
A
A
A
A
Supply voltage rejection ratio
64
80
–
dB
Specification is applicable at high
power. For all other bias modes
(except high power, high opamp
bias), minimum is 60 dB.
Power = high, Opamp bias = high
is not allowed.
VSS VIN (VDD – 2.25) or
(VDD – 1.25 V) VIN VDD.
DC Low Power Comparator Specifications
Table 13 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V at 25 °C and are for design
guidance only.
Table 13. DC Low Power Comparator Specifications
Symbol
VREFLPC
ISLPC
VOSLPC
Description
Low power comparator (LPC) reference
voltage range
LPC supply current
LPC voltage offset
Document Number: 001-52469 Rev. *J
Min
0.2
Typ
–
Max
VDD – 1
Units
V
–
–
10
2.5
40
30
A
mV
Notes
Page 18 of 51
CY8C24223A, CY8C24423A
DC Analog Output Buffer Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at
25 °C and are for design guidance only.
Table 14. 5-V DC Analog Output Buffer Specifications
Symbol
VOSOB
TCVOSOB
VCMOB
ROUTOB
Description
Min
Typ
Max
Units
Notes
Input offset voltage (absolute value)
–
3
12
mV
Average input offset voltage drift
–
+6
–
V/°C
Common mode input voltage range
0.5
–
VDD – 1.0
V
Output resistance
Power = low
–
1
–
Power = high
–
1
–
VOHIGHOB High output voltage swing (Load = 32 to VDD/2)
Power = low
0.5 × VDD + 1.1
–
–
V
Power = high
0.5 × VDD + 1.1
–
–
V
VOLOWOB Low output voltage swing (Load = 32 to VDD/2)
Power = low
–
– 0.5 × VDD – 1.3
V
Power = high
–
– 0.5 × VDD – 1.3
V
ISOB
Supply current including bias cell (no load)
Power = low
–
1.1
5.1
mA
Power = high
–
2.6
8.8
mA
PSRROB Supply voltage rejection ratio
52
64
–
dB VOUT > (VDD – 1.25).
CL
Load Capacitance
–
–
200
pF This specification
applies to the
external circuit that is
being driven by the
analog output buffer.
Table 15. 3.3-V DC Analog Output Buffer Specifications
Symbol
VOSOB
TCVOSOB
VCMOB
ROUTOB
Description
Min
Typ
Max
Units
Notes
Input offset voltage (absolute value)
–
3
12
mV
Average input offset voltage drift
–
+6
–
V/°C
Common mode input voltage range
0.5
–
VDD – 1.0
V
Output resistance
Power = low
–
1
–
Power = high
–
1
–
VOHIGHOB High output voltage swing (Load = 1 k to VDD/2)
Power = low
0.5 × VDD + 1.0
–
–
V
Power = high
0.5 × VDD + 1.0
–
–
V
VOLOWOB Low output voltage swing (Load = 1 k to VDD/2)
Power = low
–
– 0.5 × VDD – 1.0
V
Power = high
–
– 0.5 × VDD – 1.0
V
ISOB
Supply current including bias cell (no load)
Power = low
–
0.8
2.0
mA
Power = high
–
2.0
4.3
mA
PSRROB Supply voltage rejection ratio
52
64
–
dB VOUT > (VDD – 1.25).
CL
Load Capacitance
–
–
200
pF This specification
applies to the
external circuit that is
being driven by the
analog output buffer.
Document Number: 001-52469 Rev. *J
Page 19 of 51
CY8C24223A, CY8C24423A
DC Analog Reference Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at
25 °C and are for design guidance only.
The guaranteed specifications for RefHI and RefLO are measured through the analog continuous time PSoC blocks. The power levels
for RefHI and RefLO refer to the analog reference control register. AGND is measured at P2[4] in AGND bypass mode. Each analog
continuous time PSoC block adds a maximum of 10 mV additional offset error to guaranteed AGND specifications from the local
AGND buffer. Reference control power can be set to medium or high unless otherwise noted.
Note Avoid using P2[4] for digital signaling when using an analog resource that depends on the analog reference. Some coupling of
the digital signal may appear on the AGND.
Table 16. 5-V DC Analog Reference Specifications
Reference
ARF_CR
[5:3]
0b000
Reference Power
Settings
Symbol
Reference
RefPower = high
Opamp bias = high
VREFHI
Ref High
VAGND
AGND
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
0b001
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
Description
Min
Typ
Max
Units
VDD/2 + Bandgap
VDD/2 + 1.136 VDD/2 + 1.288 VDD/2 + 1.409
V
VDD/2
VDD/2 – 0.138 VDD/2 + 0.003 VDD/2 + 0.132
VDD/2 – 1.417 VDD/2 – 1.289 VDD/2 – 1.154
V
VREFLO
Ref Low
VDD/2 – Bandgap
VREFHI
Ref High
VDD/2 + Bandgap
VAGND
AGND
V
V
VDD/2
VDD/2 + 1.202 VDD/2 + 1.290 VDD/2 + 1.358
VDD/2 – 0.055 VDD/2 + 0.001 VDD/2 + 0.055
V
VREFLO
Ref Low
VDD/2 – Bandgap
VDD/2 – 1.369 VDD/2 – 1.295 VDD/2 – 1.218
V
VREFHI
Ref High
VDD/2 + Bandgap
V
VAGND
AGND
VDD/2
VDD/2 + 1.211 VDD/2 + 1.292 VDD/2 + 1.357
VDD/2 – 0.055
VDD/2
VDD/2 + 0.052
VREFLO
Ref Low
VDD/2 – Bandgap
VDD/2 – 1.368 VDD/2 – 1.298 VDD/2 – 1.224
V
VREFHI
Ref High
VDD/2 + Bandgap
VDD/2 + 1.215 VDD/2 + 1.292 VDD/2 + 1.353
VDD/2 – 0.040 VDD/2 – 0.001 VDD/2 + 0.033
V
VDD/2 – 1.368 VDD/2 – 1.299 VDD/2 – 1.225
P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] +
– 0.076
0.021
0.041
V
V
VAGND
AGND
VREFLO
Ref Low
VDD/2 – Bandgap
VREFHI
Ref High
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
VAGND
AGND
VREFLO
Ref Low
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] – P2[6] P2[4] – P2[6] + P2[4] – P2[6] +
– 0.025
0.011
0.085
V
VREFHI
Ref High
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] +
– 0.069
0.014
0.043
V
VAGND
AGND
VREFLO
Ref Low
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] – P2[6] P2[4] – P2[6] + P2[4] – P2[6] +
– 0.029
0.005
0.052
V
VREFHI
Ref High
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] +
– 0.072
0.011
0.048
V
VDD/2
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
V
V
–
–
VAGND
AGND
VREFLO
Ref Low
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] – P2[6] P2[4] – P2[6] + P2[4] – P2[6] +
– 0.031
0.002
0.057
V
VREFHI
Ref High
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] +
– 0.070
0.009
0.047
V
VAGND
AGND
VREFLO
Ref Low
Document Number: 001-52469 Rev. *J
P2[4]
P2[4]
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4] – P2[6] P2[4] – P2[6] + P2[4] – P2[6] +
– 0.033
0.001
0.039
–
–
V
Page 20 of 51
CY8C24223A, CY8C24423A
Table 16. 5-V DC Analog Reference Specifications (continued)
Reference
ARF_CR
[5:3]
0b010
Reference Power
Settings
Symbol
Reference
RefPower = high
Opamp bias = high
VREFHI
Ref High
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
0b011
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
0b100
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
Description
VDD
Min
Typ
Max
Units
VDD – 0.121
VDD – 0.003
VDD
V
VAGND
AGND
VDD/2 – 0.040
VDD/2
VDD/2 + 0.034
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.006
VSS + 0.019
V
VREFHI
Ref High
VDD
VDD – 0.083
VDD – 0.002
VDD
V
VDD/2
VAGND
AGND
VREFLO
Ref Low
VSS
VSS
VSS + 0.004
VSS + 0.016
V
VREFHI
Ref High
VDD
VDD – 0.075
VDD – 0.002
VDD
V
VDD/2
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
VDD
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
VAGND
AGND
VREFLO
VDD/2
VDD/2
VDD/2 – 0.040 VDD/2 – 0.001 VDD/2 + 0.033
VDD/2 – 0.040 VDD/2 – 0.001 VDD/2 + 0.032
V
V
VSS
VSS + 0.003
VSS + 0.015
V
VDD – 0.074
VDD – 0.002
VDD
V
VDD/2 – 0.040 VDD/2 – 0.001 VDD/2 + 0.032
V
VSS
VSS + 0.002
VSS + 0.014
V
3 × Bandgap
3.753
3.874
3.979
V
2 × Bandgap
2.511
2.590
2.657
V
Ref Low
Bandgap
1.243
1.297
1.333
V
VREFHI
Ref High
3 × Bandgap
3.767
3.881
3.974
V
VAGND
AGND
2 × Bandgap
2.518
2.592
2.652
V
VREFLO
Ref Low
Bandgap
1.241
1.295
1.330
V
VREFHI
Ref High
3 × Bandgap
2.771
3.885
3.979
V
VAGND
AGND
2 × Bandgap
2.521
2.593
2.649
V
VREFLO
Ref Low
Bandgap
1.240
1.295
1.331
V
VREFHI
Ref High
3 × Bandgap
3.771
3.887
3.977
V
VAGND
AGND
2 × Bandgap
2.522
2.594
2.648
V
VREFLO
Ref Low
Bandgap
VREFHI
Ref High
2 × Bandgap + P2[6]
(P2[6] = 1.3 V)
1.239
1.295
1.332
V
2.481 + P2[6]
2.569 + P2[6]
2.639 + P2[6]
V
VAGND
AGND
2.511
2.590
2.658
V
VREFLO
Ref Low
2 × Bandgap – P2[6]
(P2[6] = 1.3 V)
2.515 – P2[6]
2.602 – P2[6]
2.654 – P2[6]
V
VREFHI
Ref High
2 × Bandgap + P2[6]
(P2[6] = 1.3 V)
2.498 + P2[6]
2.579 + P2[6]
2.642 + P2[6]
V
VAGND
AGND
2.518
2.592
2.652
V
VREFLO
Ref Low
2 × Bandgap – P2[6]
(P2[6] = 1.3 V)
2.513 – P2[6]
2.598 – P2[6]
2.650 – P2[6]
V
VREFHI
Ref High
2 × Bandgap + P2[6]
(P2[6] = 1.3 V)
2.504 + P2[6]
2.583 + P2[6]
2.646 + P2[6]
V
VAGND
AGND
2.521
2.592
2.650
V
VREFLO
Ref Low
2 × Bandgap – P2[6]
(P2[6] = 1.3 V)
2.513 – P2[6]
2.596 – P2[6]
2.649 – P2[6]
V
VREFHI
Ref High
2 × Bandgap + P2[6]
(P2[6] = 1.3 V)
2.505 + P2[6]
2.586 + P2[6]
2.648 + P2[6]
V
VAGND
AGND
2.521
2.594
2.648
V
VREFLO
Ref Low
2.513 – P2[6]
2.595 – P2[6]
2.648 – P2[6]
V
Document Number: 001-52469 Rev. *J
2 × Bandgap
2 × Bandgap
2 × Bandgap
2 × Bandgap
2 × Bandgap – P2[6]
(P2[6] = 1.3 V)
Page 21 of 51
CY8C24223A, CY8C24423A
Table 16. 5-V DC Analog Reference Specifications (continued)
Reference
ARF_CR
[5:3]
0b101
Reference Power
Settings
Symbol
Reference
RefPower = high
Opamp bias = high
VREFHI
Ref High
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
0b110
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
0b111
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
Description
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4]
Min
Typ
Max
Units
P2[4] + 1.228
P2[4] + 1.284
P2[4] + 1.332
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.358
P2[4] – 1.293
P2[4] – 1.226
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.236
P2[4] + 1.289
P2[4] + 1.332
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.357
P2[4] – 1.297
P2[4] – 1.229
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.237
P2[4] + 1.291
P2[4] + 1.337
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.356
P2[4] – 1.299
P2[4] – 1.232
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.237
P2[4] + 1.292
P2[4] + 1.337
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.357
P2[4] – 1.300
P2[4] – 1.233
V
VREFHI
Ref High
2 × Bandgap
2.512
2.594
2.654
V
VAGND
AGND
Bandgap
1.250
1.303
1.346
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.011
VSS + 0.027
V
VREFHI
Ref High
2 × Bandgap
2.515
2.592
2.654
V
VAGND
AGND
Bandgap
1.253
1.301
1.340
V
P2[4]
P2[4]
P2[4]
VREFLO
Ref Low
VSS
VSS
VSS + 0.006
VSS + 0.02
V
VREFHI
Ref High
2 × Bandgap
2.518
2.593
2.651
V
VAGND
AGND
Bandgap
1.254
1.301
1.338
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.004
VSS + 0.017
V
VREFHI
Ref High
2 × Bandgap
2.517
2.594
2.650
V
VAGND
AGND
Bandgap
1.255
1.300
1.337
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.003
VSS + 0.015
V
VREFHI
Ref High
3.2 × Bandgap
4.011
4.143
4.203
V
1.6 × Bandgap
2.020
2.075
2.118
V
VSS
VSS + 0.011
VSS + 0.026
V
4.138
4.203
V
V
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
3.2 × Bandgap
4.022
1.6 × Bandgap
2.023
2.075
2.114
VSS
VSS + 0.006
VSS + 0.017
V
4.141
4.207
V
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
3.2 × Bandgap
4.026
1.6 × Bandgap
2.024
2.075
2.114
V
VSS
VSS + 0.004
VSS + 0.015
V
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
3.2 × Bandgap
4.030
4.143
4.206
V
VAGND
AGND
1.6 × Bandgap
2.024
2.076
2.112
V
VREFLO
Ref Low
VSS
VSS + 0.003
VSS + 0.013
V
Document Number: 001-52469 Rev. *J
VSS
Page 22 of 51
CY8C24223A, CY8C24423A
Table 17. 3.3-V DC Analog Reference Specifications
Reference
ARF_CR
[5:3]
0b000
Reference Power
Settings
Symbol
Reference
RefPower = high
Opamp bias = high
VREFHI
Ref High
VAGND
AGND
VREFLO
Ref Low
VREFHI
Ref High
VAGND
AGND
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
0b001
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
0b010
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
0b011
All power settings
Not allowed at 3.3 V
Description
Min
Typ
Max
Units
VDD/2 + Bandgap
VDD/2 + 1.170 VDD/2 + 1.288 VDD/2 + 1.376
V
VDD/2
VDD/2 – Bandgap
VDD/2 – 0.098 VDD/2 + 0.003 VDD/2 + 0.097
VDD/2 – 1.386 VDD/2 – 1.287 VDD/2 – 1.169
V
VDD/2 + Bandgap
VDD/2 + 1.210 VDD/2 + 1.290 VDD/2 + 1.355
V
VDD/2
V
V
VREFLO
Ref Low
VDD/2 – Bandgap
VDD/2 – 0.055 VDD/2 + 0.001 VDD/2 + 0.054
VDD/2 – 1.359 VDD/2 – 1.292 VDD/2 – 1.214
VREFHI
Ref High
VDD/2 + Bandgap
VDD/2 + 1.198 VDD/2 + 1.292 VDD/2 + 1.368
V
VAGND
AGND
VDD/2
VDD/2 – 0.041
VDD/2 + 0.04
V
VDD/2
V
VREFLO
Ref Low
VDD/2 – Bandgap
VDD/2 – 1.362 VDD/2 – 1.295 VDD/2 – 1.220
V
VREFHI
Ref High
VDD/2 + Bandgap
V
VAGND
AGND
VDD/2
VDD/2 + 1.202 VDD/2 + 1.292 VDD/2 + 1.364
VDD/2 – 0.033
VDD/2
VDD/2 + 0.030
V
VREFLO
Ref Low
VDD/2 – Bandgap
VDD/2 – 1.364 VDD/2 – 1.297 VDD/2 – 1.222
V
VREFHI
Ref High
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] +
– 0.072
0.017
0.041
V
VAGND
AGND
VREFLO
Ref Low
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] – P2[6] P2[4] – P2[6] + P2[4] – P2[6] +
– 0.029
0.010
0.048
V
VREFHI
Ref High
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] +
– 0.066
0.010
0.043
V
P2[4]
P2[4]
P2[4]
P2[4]
–
VAGND
AGND
VREFLO
Ref Low
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] – P2[6] P2[4] – P2[6] + P2[4] – P2[6] +
– 0.024
0.004
0.034
V
VREFHI
Ref High
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] +
– 0.073
0.007
0.053
V
VAGND
AGND
VREFLO
Ref Low
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] – P2[6] P2[4] – P2[6] + P2[4] – P2[6] +
– 0.028
0.002
0.033
V
VREFHI
Ref High
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] +
– 0.073
0.006
0.056
V
P2[4]
P2[4]
VAGND
AGND
VREFLO
Ref Low
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
VREFHI
Ref High
VDD
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
VDD
VAGND
AGND
P2[4]
VDD/2
VDD/2
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
–
–
P2[4]
P2[4]
P2[4]
–
P2[4] – P2[6]
– 0.030
P2[4] – P2[6]
P2[4] – P2[6] +
0.032
V
VDD – 0.102
VDD – 0.003
VDD
V
VDD/2 – 0.040 VDD/2 + 0.001 VDD/2 + 0.039
VSS
VSS + 0.005
VSS + 0.020
V
V
VDD – 0.082
VDD – 0.002
VDD
V
VDD/2 – 0.031
VDD/2
VDD/2 + 0.028
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.003
VSS + 0.015
V
VREFHI
Ref High
VDD
VDD – 0.083
VDD – 0.002
VDD
V
VAGND
AGND
VDD/2
VREFLO
Ref Low
VSS
VREFHI
Ref High
VDD
VAGND
AGND
VREFLO
Ref Low
–
–
Document Number: 001-52469 Rev. *J
VDD/2
VSS
–
VDD/2 – 0.032 VDD/2 – 0.001 VDD/2 + 0.029
VSS
VSS + 0.002
VSS + 0.014
VDD – 0.081
VDD – 0.002
VDD
VDD/2 – 0.033 VDD/2 – 0.001 VDD/2 + 0.029
VSS
VSS + 0.002
VSS + 0.013
–
–
–
V
V
V
V
V
–
Page 23 of 51
CY8C24223A, CY8C24423A
Table 17. 3.3-V DC Analog Reference Specifications (continued)
Reference
ARF_CR
[5:3]
Reference Power
Settings
Symbol
Reference
Description
Min
Typ
Max
Units
–
–
–
–
P2[4] + 1.211
P2[4] + 1.285
P2[4] + 1.348
V
P2[4]
P2[4]
P2[4]
–
0b100
All power settings
Not allowed at 3.3 V
–
–
0b101
RefPower = high
Opamp bias = high
VREFHI
Ref High
VAGND
AGND
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.354
P2[4] – 1.290
P2[4] – 1.197
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.209
P2[4] + 1.289
P2[4] + 1.353
V
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
0b110
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
0b111
All power settings
Not allowed at 3.3 V
–
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4]
VAGND
AGND
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.352
P2[4] – 1.294
P2[4] – 1.222
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.218
P2[4] + 1.291
P2[4] + 1.351
V
P2[4]
VAGND
AGND
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.351
P2[4] – 1.296
P2[4] – 1.224
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.215
P2[4] + 1.292
P2[4] + 1.354
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.352
P2[4] – 1.297
P2[4] – 1.227
V
VREFHI
Ref High
2 × Bandgap
2.460
2.594
2.695
V
Bandgap
1.257
1.302
1.335
V
VSS
VSS + 0.01
VSS + 0.029
V
2.592
2.692
V
V
P2[4]
P2[4]
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
2 × Bandgap
2.462
Bandgap
1.256
1.301
1.332
VSS
VSS + 0.005
VSS + 0.017
V
2.593
2.682
V
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
2 × Bandgap
2.473
Bandgap
1.257
1.301
1.330
V
VSS
VSS + 0.003
VSS + 0.014
V
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
2 × Bandgap
2.470
2.594
2.685
V
VAGND
AGND
Bandgap
1.256
1.300
1.332
V
VREFLO
Ref Low
VSS
VSS + 0.002
VSS + 0.012
V
–
–
–
–
–
–
VSS
–
DC Analog PSoC Block Specifications
Table 15 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and
are for design guidance only.
Table 18. DC Analog PSoC Block Specifications
Symbol
Description
RCT
Resistor unit value (continuous time)
CSC
Capacitor unit value (switched capacitor)
Document Number: 001-52469 Rev. *J
Min
–
–
Typ
12.2
80
Max
–
–
Units
k
fF
Notes
Page 24 of 51
CY8C24223A, CY8C24423A
DC POR and LVD Specifications
Table 19 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and
are for design guidance only.
Note The bits PORLEV and VM in the following table refer to bits in the VLT_CR register. See the PSoC Programmable
System-on-Chip Technical Reference Manual for more information on the VLT_CR register.
Table 19. DC POR and LVD Specifications
Symbol
Description
VDD value for PPOR trip
VPPOR0 PORLEV[1:0] = 00b
VPPOR1 PORLEV[1:0] = 01b
VPPOR2 PORLEV[1:0] = 10b
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
VDD value for LVD trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
Min
Typ
Max
Units
Notes
–
–
–
2.36
2.82
4.55
2.40
2.95
4.70
V
V
V
VDD must be greater than or
equal to 2.5 V during startup,
reset from the XRES pin, or
reset from Watchdog.
2.40
2.85
2.95
3.06
4.37
4.50
4.62
4.71
2.450
2.920
3.02
3.13
4.48
4.64
4.73
4.81
2.51[8]
2.99[9]
3.09
3.20
4.55
4.75
4.83
4.95
V
V
V
V
V
V
V
V
Notes
8. Always greater than 50 mV above VPPOR (PORLEV=00) for falling supply.
9. Always greater than 50 mV above VPPOR (PORLEV=01) for falling supply.
Document Number: 001-52469 Rev. *J
Page 25 of 51
CY8C24223A, CY8C24423A
DC Programming Specifications
Table 20 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and
are for design guidance only.
Table 20. DC Programming Specifications
Symbol
VDDP
Description
VDD for programming and erase
Min
4.5
Typ
5.0
Max
5.5
VDDLV
Low VDD for verify
3.0
3.1
3.2
VDDHV
High VDD for verify
5.1
5.2
5.3
VDDIWRITE
Supply voltage for flash write operation
3.0
–
5.25
IDDP
VILP
VIHP
IILP
5
–
–
–
25
0.8
–
0.2
–
1.5
VOLV
VOHV
FlashENPB
Supply current during programming or verify
–
Input low voltage during programming or verify
–
Input high voltage during programming or verify
2.1
Input current when applying VILP to P1[0] or P1[1]
–
during programming or verify
Input current when applying VIHP to P1[0] or P1[1]
–
during programming or verify
Output low voltage during programming or verify
–
Output high voltage during programming or verify VDD – 1.0
Flash endurance (per block)[10, 11]
1,000
–
–
–
0.75
VDD
–
FlashENT
FlashDR
Flash endurance (total)[11, 12]
Flash data retention
–
–
–
–
IIHP
64,000
10
Units
Notes
V
This specification
applies to the functional
requirements of external
programmer tools
V
This specification
applies to the functional
requirements of external
programmer tools
V
This specification
applies to the functional
requirements of external
programmer tools
V
This specification
applies to this device
when it is executing
internal flash writes
mA
V
V
mA Driving internal pull down
resistor.
mA Driving internal pull down
resistor.
V
V
–
Erase/write cycles per
block
–
Erase/write cycles
Years
Notes
10. The erase/write cycle limit per block (FlashENPB) is only guaranteed if the device operates within one voltage range. Voltage ranges are 3.0 V to 3.6 V and 4.75 V to
5.25 V.
11. For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) or other temperature sensor, and feed the result to the
temperature argument before writing. Refer to the Flash APIs Application Note AN2015 for more information.
12. The maximum total number of allowed erase/write cycles is the minimum FlashENPB value multiplied by the number of flash blocks in the device.
Document Number: 001-52469 Rev. *J
Page 26 of 51
CY8C24223A, CY8C24423A
AC Electrical Characteristics
AC Chip-Level Specifications
Table 21 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and
are for design guidance only.
Table 21. AC Chip-Level Specifications
Symbol
FIMO24
Description
IMO frequency for 24 MHz
Min
22.8[13]
Typ
24
Max
25.2[13]
FIMO6
IMO frequency for 6 MHz
5.5[13]
6
6.5[13]
FCPU1
CPU frequency (5 V VDD nominal) 0.089[13]
–
25.2[13]
FCPU2
0.089[13]
–
12.6[13]
0
–
50.4[13,14]
0
–
25.2[13,14]
F32K1
CPU frequency (3.3 V VDD
nominal)
Digital PSoC block frequency (5 V
VDD nominal)
Digital PSoC block frequency (3.3
V VDD nominal)
ILO frequency
15
32
64
F32KU
ILO untrimmed frequency
5
–
100
F32K2
External crystal oscillator
–
–
FPLL
PLL frequency
–
tPLLSLEW
tPLLSLEWSLOW
tOS
PLL lock time
PLL lock time for low gain setting
External crystal oscillator startup to
1%
External crystal oscillator startup to
100 ppm
0.5
0.5
–
32.76
8
23.98
6
–
–
1700
10
50
2620
ms
ms
ms
Refer to Figure 7 on page 28.
Refer to Figure 8 on page 28.
Refer to Figure 9 on page 28.
–
2800
3800
ms
10
40
20
–
45.6[13]
–
–
50
50
50
48.0
–
–
60
80
–
50.4[13]
12.6[13]
s
%
%
kHz
MHz
MHz
The crystal oscillator frequency is within 100
ppm of its final value by the end of the tOSACC
period. Correct operation assumes a properly
loaded 1 µW maximum drive level 32.768 kHz
crystal. 3.0 V VDD 5.25 V, –40 C TA 85 C.
–
–
–
16
250
100
–
200
700
ps
–
300
900
ps
N = 32
–
–
–
100
200
300
400
800
1200
ps
ps
ps
N = 32
–
100
700
ps
FBLK5
FBLK33
tOSACC
tXRST
DC24M
DCILO
Step24M
Fout48M
FMAX
SRPOWERUP
tPOWERUP
tJIT_IMO [15]
tJIT_PLL [15]
External reset pulse width
24 MHz duty cycle
ILO duty cycle
24 MHz trim step size
48 MHz output frequency
Maximum frequency of signal on
row input or row output.
Power supply slew rate
Time between end of POR state
and CPU code execution
24 MHz IMO cycle-to-cycle jitter
(RMS)
24 MHz IMO long term N
cycle-to-cycle jitter (RMS)
24 MHz IMO period jitter (RMS)
PLL cycle-to-cycle jitter (RMS)
PLL long term N cycle-to-cycle
jitter (RMS)
PLL period jitter (RMS)
–
Units
Notes
MHz Trimmed for 5 V or 3.3 V operation using factory
trim values. See Figure 6 on page 13. SLIMO
mode = 0.
MHz Trimmed for 5 V or 3.3 V operation using factory
trim values. See Figure 6 on page 13. SLIMO
mode = 1.
MHz Minimum CPU frequency is 0.022 MHz when
SLIMO mode = 0.
MHz Minimum CPU frequency is 0.022 MHz when
SLIMO mode = 0.
MHz Refer to AC Digital Block Specifications on
page 32.
MHz Refer to AC Digital Block Specifications on
page 32.
kHz This specification applies when the ILO has
been trimmed.
kHz After a reset and before the M8C processor
starts to execute, the ILO is not trimmed.
kHz Accuracy is capacitor and crystal dependent.
50% duty cycle.
MHz Is a multiple (x732) of crystal frequency.
Trimmed. Using factory trim values.
V/ms VDD slew rate during power up.
ms Power up from 0 V.
Notes
13. Accuracy derived from IMO with appropriate trim for VDD range.
14. See the individual user module data sheets for information on maximum frequencies for user modules.
15. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information.
Document Number: 001-52469 Rev. *J
Page 27 of 51
CY8C24223A, CY8C24423A
Figure 7. PLL Lock Timing Diagram
PLL
Enable
t
T
PLLSLEW
24 MHz
FPLL
PLL
Gain
0
Figure 8. PLL Lock for Low Gain Setting Timing Diagram
PLL
Enable
t PLLSLEWLOW
T
24 MHz
FPLL
PLL
Gain
1
Figure 9. External Crystal Oscillator Startup Timing Diagram
32K
Select
32 kHz
t OS
T
F32K2
Document Number: 001-52469 Rev. *J
Page 28 of 51
CY8C24223A, CY8C24423A
AC GPIO Specifications
Table 22 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and
are for design guidance only.
Table 22. AC GPIO Specifications
Symbol
Description
Min
Typ
Max
[16]
Units
Notes
MHz
Normal strong mode
FGPIO
GPIO operating frequency
0
–
12.6
tRISEF
Rise time, normal strong mode, Cload = 50 pF
3
–
18
tFALLF
Fall time, normal strong mode, Cload = 50 pF
2
–
18
ns
VDD = 4.5 to 5.25 V, 10% to 90%
tRISES
Rise time, slow strong mode, Cload = 50 pF
10
27
–
ns
VDD = 3 to 5.25 V, 10% to 90%
tFALLS
Fall time, slow strong mode, Cload = 50 pF
10
22
–
ns
VDD = 3 to 5.25 V, 10% to 90%
ns
VDD = 4.5 to 5.25 V, 10% to 90%
Figure 10. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
tRISEF
TRiseF
tRISES
TRiseS
tFALLF
TFallF
tFALLS
TFallS
Note
16. Accuracy derived from IMO with appropriate trim for VDD range.
Document Number: 001-52469 Rev. *J
Page 29 of 51
CY8C24223A, CY8C24423A
AC Operational Amplifier Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at
25 °C and are for design guidance only.
Settling times, slew rates, and gain bandwidth are based on the analog CT PSoC block.
Power = high and Opamp bias = high is not allowed at 3.3 V.
Table 23. 5-V AC Operational Amplifier Specifications
Symbol
tROA
tSOA
SRROA
SRFOA
BWOA
ENOA
Description
Rising settling time from 80% of V to 0.1% of V
(10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
Falling settling time from 20% of V to 0.1% of V
(10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
Rising slew rate (20% to 80%) (10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
Falling slew rate (80% to 20%) (10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
Gain bandwidth product
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
Noise at 1 kHz (Power = medium, Opamp bias = high)
Min
Typ
Max
Units
–
–
–
–
–
–
3.9
0.72
0.62
s
s
s
–
–
–
–
–
–
5.9
0.92
0.72
s
s
s
0.15
1.7
6.5
–
–
–
–
–
–
V/s
V/s
V/s
0.01
0.5
4.0
–
–
–
–
–
–
V/s
V/s
V/s
0.75
3.1
5.4
–
–
–
–
100
–
–
–
–
MHz
MHz
MHz
nV/rt-Hz
Min
Typ
Max
Units
–
–
–
–
3.92
0.72
s
s
–
–
–
–
5.41
0.72
s
s
0.31
2.7
–
–
–
–
V/s
V/s
0.24
1.8
–
–
–
–
V/s
V/s
0.67
2.8
–
–
–
100
–
–
–
MHz
MHz
nV/rt-Hz
Table 24. 3.3-V AC Operational Amplifier Specifications
Symbol
tROA
tSOA
SRROA
SRFOA
BWOA
ENOA
Description
Rising settling time from 80% of V to 0.1% of V
(10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Falling settling time from 20% of V to 0.1% of V
(10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Rising slew rate (20% to 80%) (10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Falling slew rate (80% to 20%) (10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Gain bandwidth product
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Noise at 1 kHz (Power = medium, Opamp bias = high)
Document Number: 001-52469 Rev. *J
Page 30 of 51
CY8C24223A, CY8C24423A
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1 k resistance and the external capacitor.
Figure 11. Typical AGND Noise with P2[4] Bypass
nV/rtHz
10000
0
0.01
0.1
1.0
10
1000
100
0.001
0.01
0.1 Freq (kHz)
1
10
100
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high
frequencies, increased power level reduces the noise spectrum level.
Figure 12. Typical Opamp Noise
nV/rtHz
10000
PH_BH
PH_BL
PM_BL
PL_BL
1000
100
10
0.001
Document Number: 001-52469 Rev. *J
0.01
0.1
Freq (kHz)
1
10
100
Page 31 of 51
CY8C24223A, CY8C24423A
AC Low Power Comparator Specifications
Table 25 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and
are for design guidance only.
Table 25. AC Low Power Comparator Specifications
Symbol
tRLPC
Description
LPC response time
Min
–
Typ
–
Max
50
Units
s
Notes
50 mV overdrive comparator
reference set within VREFLPC
AC Digital Block Specifications
Table 26 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and
are for design guidance only.
Table 26. AC Digital Block Specifications
Function
All functions
Timer
Counter
Dead Band
CRCPRS
(PRS Mode)
CRCPRS
(CRC Mode)
SPIM
SPIS
Transmitter
Receiver
Description
Block input clock frequency
VDD 4.75 V
VDD < 4.75 V
Input clock frequency
No capture, VDD 4.75 V
No capture, VDD < 4.75 V
With capture
Capture pulse width
Input clock frequency
No enable input, VDD 4.75 V
No enable input, VDD < 4.75 V
With enable input
Enable input pulse width
Kill pulse width
Asynchronous restart mode
Synchronous restart mode
Disable mode
Input clock frequency
VDD 4.75 V
VDD < 4.75 V
Input clock frequency
VDD 4.75 V
VDD < 4.75 V
Input clock frequency
Min
Typ
Max
Units
–
–
–
–
50.4[18]
25.2[18]
MHz
MHz
–
–
–
50[17]
–
–
–
–
50.4[18]
25.2[18]
25.2[18]
–
MHz
MHz
MHz
ns
–
–
–
50[17]
–
–
–
–
50.4[18]
25.2[18]
25.2[18]
–
MHz
MHz
MHz
ns
20
50[17]
50[17]
–
–
–
–
–
–
ns
ns
ns
–
–
–
–
50.4[18]
25.2[18]
MHz
MHz
–
–
–
–
–
–
50.4[18]
25.2[18]
25.2[18]
MHz
MHz
MHz
Input clock frequency
–
–
8.4[18]
Input clock (SCLK) frequency
–
–
4.2[18]
50[17]
–
–
–
–
–
–
–
–
50.4[18]
25.2[18]
25.2[18]
–
–
–
–
–
–
50.4[18]
25.2[18]
25.2[18]
MHz The SPI serial clock (SCLK)
frequency is equal to the input clock
frequency divided by 2.
MHz The input clock is the SPI SCLK in
SPIS mode.
ns
The baud rate is equal to the input
MHz clock frequency divided by 8.
MHz
MHz
The baud rate is equal to the input
MHz clock frequency divided by 8.
MHz
MHz
Width of SS_Negated between transmissions
Input clock frequency
VDD 4.75 V, 2 stop bits
VDD 4.75 V, 1 stop bit
VDD < 4.75 V
Input clock frequency
VDD 4.75 V, 2 stop bits
VDD 4.75 V, 1 stop bit
VDD < 4.75 V
Notes
Notes
17. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
18. Accuracy derived from IMO with appropriate trim for VDD range.
Document Number: 001-52469 Rev. *J
Page 32 of 51
CY8C24223A, CY8C24423A
AC Analog Output Buffer Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at
25 °C and are for design guidance only.
Table 27. 5-V AC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Units
tROB
Rising settling time to 0.1%, 1 V Step, 100 pF load
Power = low
Power = high
–
–
–
–
2.5
2.5
s
s
tSOB
Falling settling time to 0.1%, 1 V Step, 100 pF load
Power = low
Power = high
–
–
–
–
2.2
2.2
s
s
SRROB
Rising slew rate (20% to 80%), 1 V Step, 100 pF load
Power = low
Power = high
0.65
0.65
–
–
–
–
V/s
V/s
SRFOB
Falling slew rate (80% to 20%), 1 V Step, 100 pF load
Power = low
Power = high
0.65
0.65
–
–
–
–
V/s
V/s
BWOB
Small signal bandwidth, 20 mVpp, 3dB BW, 100 pF load
Power = low
Power = high
0.8
0.8
–
–
–
–
MHz
MHz
BWOB
Large signal bandwidth, 1 Vpp, 3dB BW, 100 pF load
Power = low
Power = high
300
300
–
–
–
–
kHz
kHz
Min
Typ
Max
Units
Table 28. 3.3-V AC Analog Output Buffer Specifications
Symbol
Description
tROB
Rising settling time to 0.1%, 1 V Step, 100 pF load
Power = low
Power = high
–
–
–
–
3.8
3.8
s
s
tSOB
Falling settling time to 0.1%, 1 V Step, 100 pF load
Power = low
Power = high
–
–
–
–
2.6
2.6
s
s
SRROB
Rising slew rate (20% to 80%), 1 V Step, 100 pF load
Power = low
Power = high
0.5
0.5
–
–
–
–
V/s
V/s
SRFOB
Falling slew rate (80% to 20%), 1 V Step, 100 pF load
Power = low
Power = high
0.5
0.5
–
–
–
–
V/s
V/s
BWOB
Small signal bandwidth, 20 mVpp, 3dB BW, 100 pF load
Power = low
Power = high
0.7
0.7
–
–
–
–
MHz
MHz
BWOB
Large signal bandwidth, 1 Vpp, 3dB BW, 100 pF load
Power = low
Power = high
200
200
–
–
–
–
kHz
kHz
Document Number: 001-52469 Rev. *J
Page 33 of 51
CY8C24223A, CY8C24423A
AC External Clock Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at
25 °C and are for design guidance only.
Table 29. 5 V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
FOSCEXT
Frequency
0.093
–
24.6
MHz
–
High period
20.6
–
5300
ns
–
Low period
20.6
–
–
ns
–
Power-up IMO to switch
150
–
–
s
Min
Typ
Max
Units
0.093
–
12.3
MHz
0.186
–
24.6
MHz
Table 30. 3.3 V AC External Clock Specifications
Symbol
Description
1[19]
FOSCEXT
Frequency with CPU clock divide by
FOSCEXT
Frequency with CPU clock divide by 2 or greater[20]
–
High period with CPU clock divide by 1
41.7
–
5300
ns
–
Low period with CPU clock divide by 1
41.7
–
–
ns
–
Power-up IMO to switch
150
–
–
s
AC Programming Specifications
Table 31 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and
are for design guidance only.
Table 31. AC Programming Specifications
Symbol
Description
Min
Typ
Max
Units
1
–
20
ns
Fall time of SCLK
1
–
20
ns
Data setup time to falling edge of SCLK
40
–
–
ns
tHSCLK
Data hold time from falling edge of SCLK
40
–
–
ns
FSCLK
Frequency of SCLK
0
–
8
MHz
tERASEB
Flash erase time per block
–
20
80[21]
ms
tWRITE
Flash block write time
–
80
320[21]
ms
tDSCLK
Data out delay from falling edge of SCLK
–
–
45
ns
VDD 3.6
tDSCLK3
Data out delay from falling edge of SCLK
–
–
50
ns
3.0 VDD 3.6
tERASEALL
Flash erase time (bulk)
–
20
–
ms
Erase all blocks and
protection fields at
once
tPRGH
Total flash block program time
(tERASEB + tWRITE), hot
–
–
200[21]
ms
TJ 0 °C
tPRGC
Total flash block program time
(tERASEB + tWRITE), cold
–
–
400[21]
ms
TJ 0 °C
tRSCLK
Rise time of SCLK
tFSCLK
tSSCLK
Notes
Notes
19. Maximum CPU frequency is 12 MHz nominal at 3.3 V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle
requirements.
20. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the
fifty percent duty cycle requirement is met.
21. For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) or other temperature sensor, and feed the result to the
temperature argument before writing. Refer to the Flash APIs Application Note AN2015 for more information.
Document Number: 001-52469 Rev. *J
Page 34 of 51
CY8C24223A, CY8C24423A
AC I2C Specifications
Table 32 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and
are for design guidance only.
Table 32. AC Characteristics of the I2C SDA and SCL Pins
Symbol
Standard Mode
Description
Fast Mode
Units
Min
Max
Min
Max
0
100[22]
0
400[22]
kHz
FSCLI2C
SCL clock frequency
tHDSTAI2C
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
4.0
–
0.6
–
s
tLOWI2C
LOW period of the SCL clock
4.7
–
1.3
–
s
tHIGHI2C
HIGH period of the SCL clock
4.0
–
0.6
–
s
tSUSTAI2C
Setup time for a repeated START condition
4.7
–
0.6
–
s
tHDDATI2C
Data hold time
0
–
0
–
s
–
ns
tSUDATI2C
Data setup time
250
–
100[23]
tSUSTOI2C
Setup time for STOP condition
4.0
–
0.6
–
s
tBUFI2C
Bus free time between a STOP and START condition
4.7
–
1.3
–
s
tSPI2C
Pulse width of spikes are suppressed by the input
filter.
–
–
0
50
ns
Figure 13. Definition for Timing for Fast/Standard Mode on the I2C Bus
I2C_SDA
tSUDATI2C
tSPI2C
tHDDATI2C tSUSTAI2C
tHDSTAI2C
tBUFI2C
I2C_SCL
tHIGHI2C
S
START Condition
tLOWI2C
tSUSTOI2C
Sr
Repeated START Condition
P
S
STOP Condition
Notes
22. FSCLI2C is derived from SysClk of the PSoC. This specification assumes that SysClk is operating at 24 MHz, nominal. If SysClk is at a lower frequency, then the
FSCLI2C specification adjusts accordingly.
23. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSUDATI2C 250 ns must then be met. This is automatically the
case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line trmax + tSUDATI2C = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Document Number: 001-52469 Rev. *J
Page 35 of 51
CY8C24223A, CY8C24423A
Packaging Information
This section illustrates the packaging specifications for the automotive CY8C24x23A PSoC device, along with the thermal impedances
for the package and the typical package capacitance on crystal pins.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the emulator pod drawings at http://www.cypress.com.
Packaging Dimensions
Figure 14. 20-Pin (210-Mil) SSOP
51-85077 *F
Document Number: 001-52469 Rev. *J
Page 36 of 51
CY8C24223A, CY8C24423A
Figure 15. 28-Pin (210-Mil) SSOP
51-85079 *F
Thermal Impedances
Solder Reflow Specifications
Table 33. Thermal Impedances per Package
Table 35 shows the solder reflow temperature limits that must
not be exceeded.
Typical JA [24]
Package
20-pin SSOP
117 °C/W
28-pin SSOP
101 °C/W
Capacitance on Crystal Pins
Table 35. Solder Reflow Specifications
Package
Maximum Peak
Temperature (TC)
Maximum Time
above TC – 5 °C
20-Pin SSOP
260 C
30 seconds
28-Pin SSOP
260 C
30 seconds
Table 34. Capacitance on Crystal Pins
Package
Package Capacitance
20-pin SSOP
2.6 pF
28-pin SSOP
2.8 pF
Note
24. TJ = TA + Power × JA
Document Number: 001-52469 Rev. *J
Page 37 of 51
CY8C24223A, CY8C24423A
Tape and Reel Information
Figure 16. 20-Pin SSOP Carrier Tape Drawing
51-51101 *C
Document Number: 001-52469 Rev. *J
Page 38 of 51
CY8C24223A, CY8C24423A
Figure 17. 28-Pin SSOP Carrier Tape Drawing
51-51100 *D
Table 36. Tape and Reel Specifications
Package
Cover Tape
Width (mm)
Hub Size
(inches)
Minimum Leading
Empty Pockets
20-Pin SSOP
28-Pin SSOP
13.3
13.3
4
7
42
42
Document Number: 001-52469 Rev. *J
Minimum
Trailing Empty
Pockets
25
25
Standard Full Reel
Quantity
2000
1000
Page 39 of 51
CY8C24223A, CY8C24423A
Development Tool Selection
This section presents the development tools available for the
CY8C24x23A family.
Software
PSoC Designer
At the core of the PSoC development software suite is PSoC
Designer, used to generate PSoC firmware applications. PSoC
Designer is available free of charge at http://www.cypress.com
and includes a free C compiler.
Evaluation Tools
All evaluation tools can be purchased from the Cypress Online
Store.
CY3210-PSoCEval1
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, an RS-232 port, and
plenty of breadboarding space to meet all of your evaluation
needs. The kit includes:
■
Evaluation board with LCD module
PSoC Programmer
■
MiniProg programming unit
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can operate
directly from PSoC Designer or PSoC Express. PSoC
Programmer software is compatible with both PSoC ICE-Cube
In-Circuit Emulator and PSoC MiniProg. PSoC programmer is
available free of charge at http://www.cypress.com.
■
28-Pin CY8C29466-24PXI PDIP PSoC device sample (2)
■
PSoC Designer software CD
■
Getting Started guide
■
USB 2.0 cable
Development Kits
All development kits can be purchased from the Cypress Online
Store. The online store also has the most up to date information
on kit contents, descriptions, and availability.
CY3215-DK Basic Development Kit
The CY3215-DK is for prototyping and development with PSoC
Designer. This kit supports in-circuit emulation and the software
interface allows users to run, halt, and single step the processor
and view the contents of specific memory locations. Advanced
emulation features are also supported through PSoC Designer.
The kit includes:
CY3210-24X23 Evaluation Pod (EvalPod)
PSoC EvalPods are pods that connect to the ICE (CY3215-DK
kit) to allow debugging capability. They can also function as a
standalone device without debugging capability. The EvalPod
has a 28-pin DIP footprint on the bottom for easy connection to
development kits or other hardware. The top of the EvalPod has
prototyping headers for easy connection to the device's pins.
CY3210-24X23 provides evaluation of the CY8C24x23A PSoC
device family.
Device Programmers
All device programmers can be purchased from the Cypress
Online Store.
■
ICE-Cube unit
CY3210-MiniProg1
■
28-Pin PDIP emulation pod for CY8C29466-24PXI
■
28-Pin CY8C29466-24PXI PDIP PSoC device samples (two)
■
PSoC Designer software CD
The CY3210-MiniProg1 kit allows a user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
■
ISSP cable
■
MiniProg programming unit
■
MiniEval socket programming and evaluation board
■
MiniEval socket programming and evaluation board
■
Backward compatibility cable (for connecting to legacy pods)
■
28-pin CY8C29466-24PXI PDIP PSoC device sample
■
Universal 110/220 power supply (12 V)
■
PSoC Designer software CD
■
European plug adapter
■
Getting Started guide
■
USB 2.0 cable
■
USB 2.0 cable
■
Getting Started guide
CY3207ISSP In-System Serial Programmer (ISSP)
■
Development kit registration form
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production-programming environment.
Document Number: 001-52469 Rev. *J
Page 40 of 51
CY8C24223A, CY8C24423A
Note CY3207ISSP needs special software and is not compatible
with PSoC Programmer. This software is free and can be
downloaded from http://www.cypress.com. The kit includes:
■
CY3207 programmer unit
■
PSoC ISSP software CD
■
110 ~ 240-V power supply, Euro-Plug adapter
■
USB 2.0 cable
Accessories (Emulation and Programming)
Table 37. Emulation and Programming Accessories
Part Number
Pin Package
Pod Kit[25]
Foot Kit[26]
Adapter[27]
CY8C24223A-24PVXA
20-pin SSOP
CY3250-24X23A
CY3250-20SSOP-FK
AS-20-20-01SS-6
CY8C24423A-24PVXA
28-pin SSOP
CY3250-24X23A
CY3250-28SSOP-FK
AS-28-28-02SS-6ENP-GANG
Notes
25. Pod kit contains an emulation pod, a flex-cable (connects the pod to the ICE), two feet, and device samples.
26. Foot kit includes surface mount feet that can be soldered to the target PCB.
27. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at
http://www.emulation.com.
Document Number: 001-52469 Rev. *J
Page 41 of 51
CY8C24223A, CY8C24423A
Ordering Information
The following table lists the automotive CY8C24x23A PSoC device group’s key package features and ordering codes.
SRAM
(Bytes)
Temperature
Range
Digital Blocks
Analog Blocks
Digital I/O Pins
Analog Inputs
Analog Outputs
XRES Pin
20-Pin (210-Mil) SSOP
CY8C24223A-24PVXA
4K
256
–40 °C to +85 °C
4
6
16
8
2
Yes
20-Pin (210-Mil) SSOP
(Tape and Reel)
CY8C24223A-24PVXAT
4K
256
–40 °C to +85 °C
4
6
16
8
2
Yes
28-Pin (210-Mil) SSOP
CY8C24423A-24PVXA
4K
256
–40 °C to +85 °C
4
6
24
12[1]
2
Yes
28-Pin (210-Mil) SSOP
(Tape and Reel)
CY8C24423A-24PVXAT
4K
256
–40 °C to +85 °C
4
6
24
12[1]
2
Yes
Package
Ordering
Code
Flash
(Bytes)
Table 38. CY8C24x23A Automotive PSoC Device Key Features and Ordering Information
Ordering Code Definitions
CY 8 C 24 xxx-SPxx
Package Type:
PX = PDIP Pb-free
SX = SOIC Pb-free
PVX = SSOP Pb-free
LFX/LKX = QFN Pb-free
AX = TQFP Pb-free
Thermal Rating:
C = Commercial
I = Industrial
E = Automotive Extended –40 °C to +125 °C
A = Automotive –40 °C to +85 °C
CPU Speed: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = PSoC
Company ID: CY = Cypress
Document Number: 001-52469 Rev. *J
Page 42 of 51
CY8C24223A, CY8C24423A
Reference Information
Acronyms
The following table lists the acronyms that are used in this document.
Table 39. Acronyms Used in this Datasheet
Acronym
Description
Acronym
Description
AC
alternating current
MAC
multiply-accumulate
ADC
analog-to-digital converter
MCU
microcontroller unit
AEC
Automotive Electronics Council
MIPS
million instructions per second
API
application programming interface
PCB
printed circuit board
CMOS
complementary metal oxide semiconductor
PDIP
plastic dual inline package
CPU
central processing unit
PGA
programmable gain amplifier
CRC
cyclic redundancy check
PLL
phase-locked loop
DAC
digital-to-analog converter
POR
power-on reset
DC
direct current
PPOR
precision POR
DTMF
dual-tone multi-frequency
PRS
pseudo-random sequence
ECO
external crystal oscillator
PSoC®
Programmable System-on-Chip
EEPROM
electrically erasable programmable read-only
memory
PWM
pulse-width modulator
GPIO
general-purpose I/O
RMS
root mean square
I2C
inter-integrated circuit
RTC
real time clock
I/O
input/output
SAR
successive approximation register
ICE
in-circuit emulator
SC
switched capacitor
IDE
integrated development environment
SLIMO
slow IMO
ILO
internal low speed oscillator
SPI
serial peripheral interface
IMO
internal main oscillator
SRAM
static random-access memory
IrDA
infrared data association
SROM
supervisory read-only memory
ISSP
in-system serial programming
SSOP
shrunk small outline package
LCD
liquid crystal display
UART
universal asynchronous receiver
transmitter
LED
light-emitting diode
USB
universal serial bus
LPC
low power comparator
WDT
watchdog timer
LVD
low-voltage detect
XRES
external reset
Reference Documents
CY8CPLC20, CY8CLED16P01, CY8C29x66, CY8C27x43, CY8C24x94, CY8C24x23, CY8C24x23A, CY8C22x13, CY8C21x34,
CY8C21x23, CY7C64215, CY7C603xx, CY8CNP1xx, and CYWUSB6953 PSoC® Programmable System-on-Chip Technical
Reference Manual (TRM) (001-14463)
Design Aids – Reading and Writing PSoC® Flash – AN2015 (001-40459)
Understanding Data Sheet Jitter Specifications for Cypress Timing Products – AN5054 (001-14503)
Document Number: 001-52469 Rev. *J
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CY8C24223A, CY8C24423A
Document Conventions
Units of Measure
The following table lists the units of measure that are used in this document.
Table 40. Units of Measure
Symbol
KB
dB
C
fF
Hz
kHz
k
MHz
µA
µs
µV
µW
mA
mm
Unit of Measure
1024 bytes
decibel
degree Celsius
femto farad
hertz
kilohertz
kilohm
megahertz
microampere
microsecond
microvolt
microwatt
milliampere
millimeter
Symbol
ms
mV
mVpp
nA
ns
nV
ppm
%
pA
pF
ps
V
W
Unit of Measure
millisecond
millivolt
millivolts peak-to-peak
nanoampere
nanosecond
nanovolt
ohm
parts per million
percent
picoampere
picofarad
picosecond
volt
watt
Numeric Conventions
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’).
Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended
lowercase ‘b’ (for example, ‘01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or ‘0x’ are in decimal format.
Glossary
active high
1. A logic signal having its asserted state as the logic 1 state.
2. A logic signal having the logic 1 state as the higher voltage of the two states.
analog blocks
The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks.
These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more.
analog-to-digital
converter (ADC)
A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts
a voltage to a digital number. The digital-to-analog converter (DAC) performs the reverse operation.
Application
programming
interface (API)
A series of software routines that comprise an interface between a computer application and lower level services
and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that create
software applications.
asynchronous
A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal.
bandgap
reference
A stable voltage reference design that matches the positive temperature coefficient of VT with the negative
temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference.
bandwidth
1. The frequency range of a message or information processing system measured in hertz.
2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or
loss); it is sometimes represented more specifically as, for example, full width at half maximum.
Document Number: 001-52469 Rev. *J
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CY8C24223A, CY8C24423A
Glossary (continued)
bias
1. A systematic deviation of a value from a reference value.
2. The amount by which the average of a set of values departs from a reference value.
3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to
operate the device.
block
1. A functional unit that performs a single function, such as an oscillator.
2. A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or
an analog PSoC block.
buffer
1. A storage area for data that is used to compensate for a speed difference, when transferring data from one
device to another. Usually refers to an area reserved for I/O operations, into which data is read, or from which
data is written.
2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received
from an external device.
3. An amplifier used to lower the output impedance of a system.
bus
1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing
patterns.
2. A set of signals performing a common function and carrying similar data. Typically represented using vector
notation; for example, address[7:0].
3. One or more conductors that serve as a common connection for a group of related devices.
clock
The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to
synchronize different logic blocks.
comparator
An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy
predetermined amplitude requirements.
compiler
A program that translates a high level language, such as C, into machine language.
configuration
space
In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to
‘1’.
crystal oscillator
An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric
crystal is less sensitive to ambient temperature than other circuit components.
cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear feedback shift
check (CRC)
register. Similar calculations may be used for a variety of other purposes such as data compression.
data bus
A bi-directional set of signals used by a computer to convey information from a memory location to the central
processing unit and vice versa. More generally, a set of signals used to convey data between digital functions.
debugger
A hardware and software system that allows you to analyze the operation of the system under development. A
debugger usually allows the developer to step through the firmware one step at a time, set break points, and
analyze memory.
dead band
A period of time when neither of two or more signals are in their active state or in transition.
digital blocks
The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator,
pseudo-random number generator, or SPI.
digital-to-analog
converter (DAC)
A device that changes a digital signal to an analog signal of corresponding magnitude. The analog-to-digital
converter (ADC) performs the reverse operation.
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Glossary (continued)
duty cycle
The relationship of a clock period high time to its low time, expressed as a percent.
emulator
Duplicates (provides an emulation of) the functions of one system with a different system, so that the second
system appears to behave like the first system.
external reset
(XRES)
An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop
and return to a pre-defined state.
flash
An electrically programmable and erasable, non-volatile technology that provides you the programmability and
data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is
off.
flash block
The smallest amount of flash ROM space that may be programmed at one time and the smallest amount of flash
space that may be protected.
frequency
The number of cycles or events per unit of time, for a periodic function.
gain
The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually
expressed in dB.
I2C
A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). It is used to connect
low-speed peripherals in an embedded system. The original system was created in the early 1980s as a battery
control interface, but it was later used as a simple internal bus system for building control electronics. I2C uses
only two bi-directional pins, clock and data, both running at the VDD supply voltage and pulled high with resistors.
The bus operates up to100 kbits/second in standard mode and 400 kbits/second in fast mode.
ICE
The in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging
device activity in a software environment (PSoC Designer).
input/output (I/O) A device that introduces data into or extracts data from a system.
interrupt
A suspension of a process, such as the execution of a computer program, caused by an event external to that
process, and performed in such a way that the process can be resumed.
interrupt service
routine (ISR)
A block of code that normal code execution is diverted to when the CPU receives a hardware interrupt. Many
interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends
with the RETI instruction, returning the device to the point in the program where it left normal program execution.
jitter
1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on
serial data streams.
2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between
successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles.
low voltage detect A circuit that senses VDD and provides an interrupt to the system when VDD falls below a selected threshold.
(LVD)
M8C
An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by
interfacing to the flash, SRAM, and register space.
master device
A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in
width, the master device is the one that controls the timing for data exchanges between the cascaded devices
and an external interface. The controlled device is called the slave device.
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Glossary (continued)
microcontroller
An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a
microcontroller typically includes memory, timing circuits, and I/O circuitry. The reason for this is to permit the
realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This
in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for
general-purpose computation as is a microprocessor.
mixed-signal
The reference to a circuit containing both analog and digital techniques and components.
modulator
A device that imposes a signal on a carrier.
noise
1. A disturbance that affects a signal and that may distort the information carried by the signal.
2. The random variations of one or more characteristics of any entity such as voltage, current, or data.
oscillator
A circuit that may be crystal controlled and is used to generate a clock frequency.
parity
A technique for testing transmitted data. Typically, a binary digit is added to the data to make the sum of all the
digits of the binary data either always even (even parity) or always odd (odd parity).
phase-locked
loop (PLL)
An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference
signal.
pinouts
The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their
physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between
schematic and PCB design (both being computer generated files) and may also involve pin names.
port
A group of pins, usually eight.
power-on reset
(POR)
A circuit that forces the PSoC device to reset when the voltage is below a pre-set level. This is one type of hardware
reset.
PSoC®
Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-on-Chip™ is a trademark
of Cypress.
PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology.
pulse width
An output in the form of duty cycle which varies as a function of the applied value.
modulator (PWM)
RAM
An acronym for random access memory. A data-storage device from which data can be read out and new data
can be written in.
register
A storage device with a specific capacity, such as a bit or byte.
reset
A means of bringing a system back to a known state. See hardware reset and software reset.
ROM
An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot
be written in.
serial
1. Pertaining to a process in which all events occur one after the other.
2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or
channel.
settling time
The time it takes for an output signal or value to stabilize after the input has changed from one value to another.
Document Number: 001-52469 Rev. *J
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CY8C24223A, CY8C24423A
Glossary (continued)
shift register
A memory storage device that sequentially shifts a word either left or right to output a stream of serial data.
slave device
A device that allows another device to control the timing for data exchanges between two devices. Or when
devices are cascaded in width, the slave device is the one that allows another device to control the timing of data
exchanges between the cascaded devices and an external interface. The controlling device is called the master
device.
SRAM
An acronym for static random access memory. A memory device where you can store and retrieve data at a high
rate of speed. The term static is used because, after a value is loaded into an SRAM cell, it remains unchanged
until it is explicitly altered or until power is removed from the device.
SROM
An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate
circuitry, and perform flash operations. The functions of the SROM may be accessed in normal user code,
operating from flash.
stop bit
A signal following a character or block that prepares the receiving device to receive the next character or block.
synchronous
1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal.
2. A system whose operation is synchronized by a clock signal.
tri-state
A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any
value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit,
allowing another output to drive the same net.
UART
A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits.
user modules
Pre-built, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower
level analog and digital PSoC blocks. User modules also provide high level API (Application Programming
Interface) for the peripheral function.
user space
The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal
program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during
the initialization phase of the program.
VDD
A name for a power net meaning "voltage drain". The most positive power supply signal. Usually 5 V or 3.3 V.
VSS
A name for a power net meaning "voltage source." The most negative power supply signal.
watchdog timer
A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time.
Document Number: 001-52469 Rev. *J
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CY8C24223A, CY8C24423A
Document History Page
Document Title: CY8C24223A, CY8C24423A Automotive PSoC® Programmable System-on-Chip
Document Number: 001-52469
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
**
2678061 VIVG / PYRS
*A
2685606
SHEA
*B
2702925
BTK
*C
2742354
BTK / PYRS
*D
2822792
BTK / AESA
12/07/2009 Added TPRGH, TPRGC, IOL, IOH, F32KU, DCILO, and TPOWERUP electrical specifications. Corrected the FlashENT electrical specification. Updated all footnotes
for Table 20, “DC Programming Specifications,” on page 26. Added maximum
values and updated typical values for TERASEB and TWRITE electrical specifications. Replaced TRAMP electrical specification with SRPOWERUP electrical specification. Added “Contents” on page 2.
*E
2888007
NJF
03/30/2010 Updated Cypress website links.
Removed reference to PSoC Designer 4.4.
Added TBAKETEMP and TBAKETIME parameters in Absolute Maximum Ratings on
page 14.
Updated 3.3 V DC Analog Reference Specifications on page 21.
Removed Third Party Tools and Build a PSoC Emulator into Your Board.
Updated links in Sales, Solutions, and Legal Information.
*F
3070556
BTK
10/25/2010 Added CY8C24223A-24PVXA(T) devices to datasheet.
Updated the following sections: Getting Started, Development Tools, and
Designing with PSoC Designer
Moved Acronyms and Document Conventions to the end of document.
Added Reference Information and Glossary sections.
Updated datasheet as per Cypress style guide and new datasheet template.
*G
3110316
BTK / NJF
05/12/11
Updated I2C timing diagram to improve clarity.
Updated wording, formatting, and notes of the AC Digital Block Specifications
table to improve clarity.
Added VDDP, VDDLV, and VDDHV electrical specifications to give more information
for programming the device.
Updated solder reflow temperature specifications to give more clarity.
Updated the jitter specifications.
Updated PSoC Device Characteristics table.
Updated the F32KU electrical specification.
Updated note for RPD electrical specification.
Updated note for the TSTG electrical specification to add more clarity.
Added Tape and Reel Information section.
Added CL electrical specification.
Updated Analog Reference specifications.
*H
3980449
AESA
04/24/13
Updated Figure 16 and Figure 17.
Document Number: 001-52469 Rev. *J
03/24/09
New data sheet for Automotive A-Grade
04/08/09
Minor ECN to correct the spec number in Document History.
05/06/2009 Post to external web
07/22/09
Changed title. Updated Features section. Updated text of PSoC Functional
Overview section. Updated Getting Started section. Made corrections and minor
text edits to Pinouts section. Changed the name of the Register Reference
section to "Registers". Added clarifying comments to some electrical specifications. Updated some figures. Changed TRAMP specification per MASJ input.
Fixed all AC specifications to conform to a ±5% IMO accuracy. Made other
miscellaneous minor text edits. Deleted some non-applicable or redundant information. Added a footnote to clarify that 8 of the 12 analog inputs are regular and
the other 4 are direct SC block connections. Updated Development Tool
Selection section.
Page 49 of 51
CY8C24223A, CY8C24423A
Document Title: CY8C24223A, CY8C24423A Automotive PSoC® Programmable System-on-Chip
Document Number: 001-52469
Revision
ECN
Orig. of
Change
*I
4691432
KUK
*J
5987976
AESATMP8
Submission
Date
Document Number: 001-52469 Rev. *J
Description of Change
03/18/2015 Updated Electrical Specifications:
Updated DC Electrical Characteristics:
Updated DC Analog Reference Specifications:
Updated description.
Updated Packaging Information:
Updated Packaging Dimensions:
spec 51-85077 – Changed revision from *E to *F.
spec 51-85079 – Changed revision from *E to *F.
Updated Tape and Reel Information:
spec 51-51100 – Changed revision from *C to *D.
Updated to new template.
Completing Sunset Review.
12/08/2017 Updated logo and Copyright.
Page 50 of 51
CY8C24223A, CY8C24423A
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
cypress.com/clocks
cypress.com/interface
Internet of Things
Memory
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6
Cypress Developer Community
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2009-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-52469 Rev. *J
Revised December 8, 2017
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