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PSoC® Programmable System-on-Chip™
PSoC® Programmable System-on-Chip™
Features
■
■
■
■
■
Powerful Harvard-architecture processor
❐ M8C processor speeds up to 24 MHz
❐ 8 × 8 multiply, 32-bit accumulate
❐ Low power at high speed
❐ Operating voltage: 3.0 V to 5.25 V
❐ Operating voltages down to 1.0 V using on-chip switch mode
pump (SMP)
❐ Industrial temperature range: –40 C to +85 C
■
Additional system resources
2
❐ I C slave, master, and multi-master to 400 kHz
❐ Watchdog and sleep timers
❐ User-configurable low-voltage detection (LVD)
❐ Integrated supervisory circuit
❐ On-chip precision voltage reference
■
Complete development tools
❐ Free development software (PSoC Designer™)
❐ Full-featured, in-circuit emulator (ICE) and programmer
❐ Full-speed emulation
❐ Complex breakpoint structure
❐ 128 KB trace memory
Advanced peripherals (PSoC® blocks)
❐ Twelve rail-to-rail analog PSoC blocks provide:
• Up to 14-bit analog-to-digital converters (ADCs)
• Up to 9-bit digital-to-analog converters (DACs)
• Programmable gain amplifiers (PGAs)
• Programmable filters and comparators
❐ Eight digital PSoC blocks provide:
• 8- to 32-bit timers and counters, 8- and 16-bit pulse-width
modulators (PWMs)
• Cyclical redundancy check (CRC) and pseudo random
sequence (PRS) modules
• Up to two full-duplex universal asynchronous receiver
transmitters (UARTs)
• Multiple serial peripheral interface (SPI)masters or slaves
• Connectable to all general-purpose I/O (GPIO) pins
❐ Complex peripherals by combining blocks
Logic Block Diagram
PSoC
CORE
Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Analog
Drivers
System Bus
Global Digital Interconnect
SRAM
256 Bytes
SROM
Flash 16 KB
CPU Core (M8C)
Interrupt
Controller
Precision, programmable clocking
❐ Internal 2.5% 24- / 48-MHz main oscillator
❐ 24- / 48-MHz with optional 32 kHz crystal
❐ Optional external oscillator up to 24 MHz
❐ Internal oscillator for watchdog and sleep
Global Analog Interconnect
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Flexible on-chip memory
❐ 16 KB flash program storage 50,000 erase/write cycles
❐ 256-bytes SRAM data storage
❐ In-system serial programming (ISSP)
❐ Partial flash updates
❐ Flexible protection modes
❐ Electronically erasable programmable read only memory
(EEPROM) emulation in flash
Programmable pin configurations
❐ 25-mA sink, 10-mA source on all GPIOs
❐ Pull-up, pull-down, high-Z, strong, or open-drain drive modes
on all GPIOs
❐ Eight standard analog inputs on GPIO, plus four additional
analog inputs with restricted routing
❐ Four 30-mA analog outputs on GPIOs
❐ Configurable interrupt on all GPIOs
ANALOG SYSTEM
Digital
Block
Array
Digital
Clocks
Multiply
Accum.
Analog
Block
Array
POR and LVD
Decimator
I2 C
System Resets
Analog
Ref.
Analog
Input
Muxing
Internal
Voltage
Ref.
Switch
Mode
Pump
SYSTEM RESOURCES
Errata: For information on silicon errata, see “Errata” on page 61. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 38-12012 Rev. AD
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 4, 2018
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More Information
Cypress provides a wealth of data at www.cypress.com to help
you to select the right PSoC device for your design, and to help
you to quickly and effectively integrate the device into your
design. For a comprehensive list of resources, see the
knowledge base article “How to Design with PSoC® 1,
PowerPSoC®, and PLC – KBA88292”. Following is an
abbreviated list for PSoC 1:
■
Overview: PSoC Portfolio, PSoC Roadmap
■
Product Selectors: PSoC 1, PSoC 3, PSoC 4, PSoC 5LP
■
In addition, PSoC Designer includes a device selection tool.
Application notes: Cypress offers a large number of PSoC
application notes covering a broad range of topics, from basic
to advanced level. Recommended application notes for getting
started with PSoC 1 are:
®
❐ Getting Started with PSoC 1 – AN75320.
®
❐ PSoC 1 - Getting Started with GPIO – AN2094.
®
❐ PSoC 1 Analog Structure and Configuration – AN74170.
®
❐ PSoC 1 Switched Capacitor Analog Blocks – AN2041.
❐ Selecting Analog Ground and Reference – AN2219.
Note: For CY8C27X43 devices related Application note please
click here.
■
■
Development Kits:
❐ CY3210-PSoCEval1 supports all PSoC 1 Mixed-Signal Array
families, including automotive, except CY8C25/26xxx
devices. The kit includes an LCD module, potentiometer,
LEDs, and breadboarding space.
❐ CY3214-PSoCEvalUSB features a development board for
the CY8C24x94 PSoC device. Special features of the board
include USB and CapSense development and debugging
support.
Note: For CY8C27X43 devices related Development Kits please
click here.
The MiniProg1 and MiniProg3 devices provide interfaces for
flash programming and debug.
PSoC Designer
PSoC Designer is a free Windows-based Integrated Design
Environment (IDE). Develop your applications using a library of
pre-characterized analog and digital peripherals in a
drag-and-drop design environment. Then, customize your
design leveraging the dynamically generated API libraries of
code. Figure 1 shows PSoC Designer windows. Note: This is not
the default view.
1. Global Resources – all device hardware settings.
2. Parameters – the parameters of the currently selected User
Modules.
3. Pinout – information related to device pins.
4. Chip-Level Editor – a diagram of the resources available on
the selected chip.
5. Datasheet – the datasheet for the currently selected UM
6. User Modules – all available User Modules for the selected
device.
7. Device Resource Meter – device resource usage for the
current project configuration.
8. Workspace – a tree level diagram of files associated with the
project.
9. Output – output from project build and debug operations.
Note: For detailed information on PSoC Designer, go to
PSoC® Designer > Help > Documentation >
Designer Specific Documents > IDE User Guide.
Figure 1. PSoC Designer Layout
Document Number: 38-12012 Rev. AD
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Contents
PSoC Functional Overview .............................................. 4
PSoC Core .................................................................. 4
Digital System ............................................................. 4
Analog System ............................................................ 5
Additional System Resources ..................................... 6
PSoC Device Characteristics ...................................... 6
Development Tools .......................................................... 7
PSoC Designer Software Subsystems ........................ 7
Designing with PSoC Designer ....................................... 8
Select User Modules ................................................... 8
Configure User Modules .............................................. 8
Organize and Connect ................................................ 8
Generate, Verify, and Debug ....................................... 8
Pinouts .............................................................................. 9
8-pin Part Pinout .......................................................... 9
20-pin Part Pinout ........................................................ 9
28-pin Part Pinout ...................................................... 10
44-pin Part Pinout ...................................................... 11
48-pin Part Pinout ...................................................... 12
56-pin Part Pinout ...................................................... 14
Register Reference ......................................................... 16
Register Conventions ................................................ 16
Register Mapping Tables .......................................... 16
Electrical Specifications ................................................ 19
Absolute Maximum Ratings ....................................... 19
Operating Temperature ............................................. 20
DC Electrical Characteristics ..................................... 20
AC Electrical Characteristics ..................................... 35
Packaging Information ................................................... 44
Document Number: 38-12012 Rev. AD
Packaging Dimensions .............................................. 44
Thermal Impedances ................................................. 50
Capacitance on Crystal Pins ..................................... 50
Solder Reflow Specifications ..................................... 50
Development Tool Selection ......................................... 51
Software .................................................................... 51
Development Kits ...................................................... 51
Evaluation Tools ........................................................ 51
Device Programmers ................................................. 52
Accessories (Emulation and Programming) ................ 52
Ordering Information ...................................................... 53
Ordering Code Definitions ......................................... 54
Acronyms ........................................................................ 55
Reference Documents .................................................... 55
Document Conventions ................................................. 56
Units of Measure ....................................................... 56
Numeric Conventions ................................................ 56
Glossary .......................................................................... 56
Errata ............................................................................... 61
In Production ............................................................. 61
Not in Production ....................................................... 63
Document History Page ................................................. 66
Sales, Solutions, and Legal Information ...................... 69
Worldwide Sales and Design Support ....................... 69
Products .................................................................... 69
PSoC® Solutions ...................................................... 69
Cypress Developer Community ................................. 69
Technical Support ..................................................... 69
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The digital system is composed of eight digital PSoC blocks.
Each block is an 8-bit resource that can be used alone or
combined with other blocks to form 8-, 16-, 24-, and 32-bit
peripherals, which are called user modules.
Figure 2. Digital System Block Diagram
Port 5
Port 1
Port 2
Digital Clocks
FromCore
To System Bus
Port 0
ToAnalog
System
DIGITAL SYSTEM
Digital PSoC Block Array
PSoC Core
Row 0
DBB00
DBB01
DCB02
4
DCB03
4
8
8
8
Row Input
Configuration
Row 1
DBB10
DBB11
DCB12
4
DCB13
4
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
8
Row Output
Configuration
The PSoC core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPIO.
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a four MIPS 8-bit Harvard architecture
microprocessor. The CPU uses an interrupt controller with 17
vectors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
sleep and watchdog timers (WDT).
Memory encompasses 16 KB of flash for program storage,
256 bytes of SRAM for data storage, and up to 2 K of EEPROM
emulated using the flash. Program flash uses four protection
levels on blocks of 64 bytes, allowing customized software IP
protection.
The PSoC device incorporates flexible internal clock generators,
including a 24-MHz internal main oscillator (IMO) accurate to
2.5% over temperature and voltage. The 24-MHz IMO can also
be doubled to 48 MHz for use by the digital system. A low power
32-kHz internal low speed oscillator (ILO) is provided for the
sleep timer and WDT. If crystal accuracy is desired, the
32.768-kHz external crystal oscillator (ECO) is available for use
as a Real Time Clock (RTC) and can optionally generate a
crystal-accurate 24-MHz system clock using a PLL. The clocks,
together with programmable clock dividers (as a system
resource), provide the flexibility to integrate almost any timing
requirement into the PSoC device.
PSoC GPIOs provide connection to the CPU, digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external
interfacing. Every pin also has the capability to generate a
system interrupt on high level, low level, and change from last
read.
Port 3
Port 4
Row Output
Configuration
The PSoC family consists of many programmable
system-on-chip controller devices. These devices are designed
to replace multiple traditional microcontroller unit (MCU)-based
system components with one, low-cost single-chip
programmable device. PSoC devices include configurable
blocks of analog and digital logic, as well as programmable
interconnects. This architecture lets you to create customized
peripheral configurations that match the requirements of each
individual application. Additionally, a fast central processing unit
(CPU), flash program memory, SRAM data memory, and
configurable I/O are included in a range of convenient pinouts
and packages.
The PSoC architecture, as illustrated in Logic Block Diagram on
page 1, consists of four main areas: PSoC core, digital system,
analog system, and system resources. Configurable global
busing allows all the device resources to be combined into a
complete custom system. The PSoC CY8C27x43 family can
have up to five I/O ports that connect to the global digital and
analog interconnects, providing access to eight digital blocks and
12 analog blocks.
Digital System
Row Input
Configuration
PSoC Functional Overview
GOE[7:0]
GOO[7:0]
Digital peripheral configurations include:
■
PWMs (8- and 16-bit)
■
PWMs with dead band (8- and 16-bit)
■
Counters (8- to 32-bit)
■
Timers (8- to 32-bit) [1, 2]
■
UART 8-bit with selectable parity (up to two)
■
SPI slave and master (up to two) [3]
■
I2C slave and multi-master (one available as a system
resource)
■
CRC/generator (8- to 32-bit)
■
IrDA (up to two)
■
Pseudo random sequence (PRS) generators (8- to 32-bit)
Notes
1. Errata: When operated between 4.75 V to 5.25 V, the input capture signal cannot be sourced from Row Output signals or the Broadcast clock signals. This problem
has been fixed in silicon Rev B. For more information, see “Errata” on page 61.
2. Errata: When operated between 3.0V to 4.75V, the input capture signal can only be sourced from Row input signal that has been re-synchronized. This problem has
been fixed in silicon Rev B. For more information, see “Errata” on page 61.
3. Errata: In PSoC, when one output of one SPI Slave block is connected to the input of other SPI slave block, data is shifted correctly but last bit is read incorrectly. For
the workaround and more information related to this problem, see “Errata” on page 61.
Document Number: 38-12012 Rev. AD
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Analog System
The analog system is composed of 12 configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common PSoC analog functions (most
available as user modules) are as follows:
Analog blocks are provided in columns of three, which includes
one continuous time (CT) and two switched capacitor (SC)
blocks, as shown in the following figure.
Figure 3. Analog System Block Diagram
P0[7]
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
P0[1]
P0[0]
AGNDIn RefIn
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also enable signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This lets you the optimum
choice of system resources for your application. Family
resources are shown in the table titled PSoC Device
Characteristics on page 6.
P2[3]
P2[1]
P2[6]
P2[4]
P2[2]
P2[0]
■
ADCs (up to 4, with 6- to 14-bit resolution, selectable as
incremental, delta sigma, and SAR)
■
Filters (2, 4, 6, and 8 pole band pass, low pass, and notch)
■
Amplifiers (up to four, with selectable gain to 48x)
■
Instrumentation amplifiers (up to two, with selectable gain to
93x)
■
Comparators (up to four, with 16 selectable thresholds)
■
DACs (up to four, with 6- to 9-bit resolution)
■
Multiplying DACs (up to four, with 6- to 9-bit resolution)
ACB00
ACB01
ACB02
ACB03
■
High current output drivers (four with 30 mA drive as a core
resource)
ASC10
ASD11
ASC12
ASD13
■
1.3-V reference (as a system resource)
ASD20
ASC21
ASD22
ASC23
■
DTMF dialer
■
Modulators
■
Correlators
■
Peak detectors
■
Many other topologies possible
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
ACI2[1:0]
ACI3[1:0]
Block Array
Analog Reference
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 38-12012 Rev. AD
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Additional System Resources
System resources, some of which have been previously listed,
provide additional capability useful to complete systems.
Additional resources include a multiplier, decimator, switch mode
pump, low voltage detection, and power on reset.
■
■
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
Multiply accumulate (MAC) provides fast 8-bit multiplier with
32-bit accumulate, to assist in general math and digital filters.
The decimator provides a custom hardware filter for digital
signal processing applications including the creation of Delta
Sigma ADCs.
■
The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, and multi-master modes are all
supported.
■
LVD interrupts can signal the application of falling voltage
levels, while the advanced power-on reset (POR) circuit
eliminates the need for a system supervisor.
■
An internal 1.3-V reference provides an absolute reference for
the analog system, including ADCs and DACs.
■
An integrated switch mode pump (SMP) generates normal
operating voltages from a single 1.2-V battery cell, providing a
low cost boost converter.
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4
analog blocks. The following table lists the resources available for specific PSoC device groups.The PSoC device covered by this
datasheet is highlighted in Table 1.
Table 1. PSoC Device Characteristics
PSoC Part
Number
Digital
I/O
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Outputs
Analog
Columns
Analog
Blocks
SRAM
Size
Flash
Size
CY8C29x66
up to 64
4
16
up to 12
4
4
12
2K
32 K
CY8C28xxx
up to 44
up to 3
up to 12
up to 44
up to 4
up to 6
up to
12 + 4[4]
1K
16 K
CY8C27x43
up to 44
2
8
up to 12
4
4
12
256
16 K
CY8C24x94
up to 56
1
4
up to 48
2
2
6
1K
16 K
CY8C24x23A
up to 24
1
4
up to 12
2
2
6
256
4K
CY8C23x33
up to 26
1
4
up to 12
2
2
4
256
8K
CY8C22x45
up to 38
2
8
up to 38
0
4
6[4]
1K
16 K
[4]
CY8C21x45
up to 24
1
4
up to 24
0
4
6
512
8K
CY8C21x34
up to 28
1
4
up to 28
0
2
4[4]
512
8K
CY8C21x23
up to 16
1
4
up to 8
0
2
4[4]
256
4K
[4, 5]
CY8C20x34
up to 28
0
0
up to 28
0
0
3
CY8C20xx6
up to 36
0
0
up to 36
0
0
3[4, 5]
512
8K
up to 2 K
up to 32 K
Notes
4. Limited analog functionality.
5. Two analog blocks and one CapSense®.
Document Number: 38-12012 Rev. AD
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Development Tools
PSoC Designer™ is the revolutionary Integrated Design
Environment (IDE) that you can use to customize PSoC to meet
your specific application requirements. PSoC Designer software
accelerates system design and time to market. Develop your
applications using a library of precharacterized analog and digital
peripherals (called user modules) in a drag-and-drop design
environment. Then, customize your design by leveraging the
dynamically generated application programming interface (API)
libraries of code. Finally, debug and test your designs with the
integrated debug environment, including in-circuit emulation and
standard software debug features. PSoC Designer includes:
■
Application editor graphical user interface (GUI) for device and
user module configuration and dynamic reconfiguration
■
Extensive user module catalog
■
Integrated source-code editor (C and assembly)
■
Free C compiler with no size restrictions or time limits
■
Built-in debugger
■
In-circuit emulation
Built-in support for communication interfaces:
2
❐ Hardware and software I C slaves and masters
❐ Full-speed USB 2.0
❐ Up
to
four
full-duplex
universal
asynchronous
receiver/transmitters (UARTs), SPI master and slave, and
wireless
PSoC Designer supports the entire library of PSoC 1 devices and
runs on Windows XP, Windows Vista, and Windows 7.
■
PSoC Designer Software Subsystems
Design Entry
In the chip-level view, choose a base device to work with. Then
select different onboard analog and digital components that use
the PSoC blocks, which are called user modules. Examples of
user modules are analog-to-digital converters (ADCs),
digital-to-analog converters (DACs), amplifiers, and filters.
Configure the user modules for your chosen application and
connect them to each other and to the proper pins. Then
generate your project. This prepopulates your project with APIs
and libraries that you can use to program your application.
The tool also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
reconfiguration makes it possible to change configurations at run
time. In essence, this lets you to use more than 100 percent of
PSoC’s resources for an application.
Document Number: 38-12012 Rev. AD
Code Generation Tools
The code generation tools work seamlessly within the
PSoC Designer interface and have been tested with a full range
of debugging tools. You can develop your design in C, assembly,
or a combination of the two.
Assemblers. The assemblers allow you to merge assembly
code seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices. The
optimizing C compilers provide all of the features of C, tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow you to read and program and
read and write data memory, and read and write I/O registers.
You can read and write CPU registers, set and clear breakpoints,
and provide program run, halt, and step control. The debugger
also lets you to create a trace buffer of registers and memory
locations of interest.
Online Help System
The online help system displays online, context-sensitive help.
Designed for procedural and quick reference, each functional
subsystem has its own context-sensitive help. This system also
provides tutorials and links to FAQs and an Online Support
Forum to aid the designer.
In-Circuit Emulator
A low-cost, high-functionality In-Circuit Emulator (ICE) is
available for development support. This hardware can program
single devices.
The emulator consists of a base unit that connects to the PC
using a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full-speed
(24-MHz) operation.
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Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
The PSoC development process is summarized in four steps:
1. Select User Modules.
2. Configure user modules.
3. Organize and connect.
4. Generate, verify, and debug.
Select User Modules
PSoC Designer provides a library of prebuilt, pretested hardware
peripheral components called “user modules.” User modules
make selecting and implementing peripheral devices, both
analog and digital, simple.
Configure User Modules
Each user module that you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a pulse
width modulator (PWM) User Module configures one or more
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to
correspond to your chosen application. Enter values directly or
by selecting values from drop-down menus. All the user modules
are documented in datasheets that may be viewed directly in
PSoC Designer or on the Cypress website. These user module
datasheets explain the internal operation of the user module and
provide performance specifications. Each datasheet describes
the use of each user module parameter, and other information
you may need to successfully implement your design.
Document Number: 38-12012 Rev. AD
Organize and Connect
You build signal chains at the chip level by interconnecting user
modules to each other and the I/O pins. You perform the
selection, configuration, and routing so that you have complete
control over all on-chip resources.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, you perform the “Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system. The
generated code provides application programming interfaces
(APIs) with high-level functions to control and respond to
hardware events at run time and interrupt service routines that
you can adapt as needed.
A complete code development environment lets you to develop
and customize your applications in either C, assembly language,
or both.
The last step in the development process takes place inside
PSoC Designer’s debugger (access by clicking the Connect
icon). PSoC Designer downloads the HEX image to the ICE
where it runs at full speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition
to traditional single-step, run-to-breakpoint and watch-variable
features, the debug interface provides a large trace buffer and
lets you to define complex breakpoint events that include
monitoring address and data bus values, memory locations and
external signals.
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Pinouts
The CY8C27x43 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port
pin (labeled with a “P”) is capable of Digital I/O. However, Vss, VDD, SMP, and XRES are not capable of Digital I/O.
8-pin Part Pinout
Table 2. Pin Definitions – 8-pin PDIP
Type
Pin
No.
Digital
Analog
Pin
Name
1
I/O
I/O
P0[5]
Analog column mux input and column output
2
I/O
I/O
P0[3]
Analog column mux input and column output
3
I/O
P1[1]
Crystal Input (XTALin), I2C serial clock (SCL),
ISSP-SCLK[6]
4
Power
5
I/O
6
I/O
7
I/O
8
Vss
Description
A, IO, P0[5]
A, IO, P0[3]
I2CSCL, XTALin, P1[1]
VSS
1
8 VDD
2 PDIP 7 P0[4], A, IO
3
6 P0[2], A, IO
4
5 P1[0], XTALout, I2CSDA
Ground connection.
P1[0]
Crystal output (XTALout), I2C serial data (SDA),
ISSP-SDATA[6]
I/O
P0[2]
Analog column mux input and column output
I/O
P0[4]
Analog column mux input and column output
VDD
Supply voltage
Power
Figure 4. CY8C27143 8-pin PSoC Device
LEGEND: A = Analog, I = Input, and O = Output.
20-pin Part Pinout
Table 3. Pin Definitions – 20-pin SSOP, SOIC
Type
Pin
No.
Digital
Analog
Pin
Name
1
I/O
I
P0[7]
Analog column mux input
2
I/O
I/O
P0[5]
Analog column mux input and column output
3
I/O
I/O
P0[3]
Analog column mux input and column output
4
I/O
I
P0[1]
Analog column mux input
SMP
Switch Mode Pump (SMP) connection to external
components required
5
Power
Description
6
I/O
P1[7]
I2C Serial Clock (SCL)
7
I/O
P1[5]
I2C Serial Data (SDA)
8
I/O
P1[3]
9
I/O
P1[1]
10
Power
Vss
11
I/O
P1[0]
12
I/O
P1[2]
13
I/O
P1[4]
14
I/O
P1[6]
15
Input
XRES
1
2
3
4
5
6
7
8
9
10
SSOP
SOIC
20
19
18
17
16
15
14
13
12
11
VDD
P0[6], A, I
P0[4], A, IO
P0[2], A, IO
P0[0], A, I
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C
SDA
Ground connection.
Crystal output (XTALout), I2C SDA, ISSP-SDATA[6]
Optional external clock input (EXTCLK)
Active high external reset with internal pull down
I/O
I
P0[0]
Analog column mux input
17
I/O
I/O
P0[2]
Analog column mux input and column output
18
I/O
I/O
P0[4]
Analog column mux input and column output
19
I/O
I
P0[6]
Analog column mux input
VDD
Supply voltage
Power
A, I, P0[7]
A, IO, P0[5]
A, IO, P0[3]
A, I, P0[1]
SMP
I2CSCL, P1[7]
I2CSDA, P1[5]
P1[3]
I2CSCL, XTALin, P1[1]
VSS
Crystal input (XTALin), I2C SCL, ISSP-SCLK[6]
16
20
Figure 5. CY8C27243 20-pin PSoC Device
LEGEND: A = Analog, I = Input, and O = Output.
Note
6. These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
Document Number: 38-12012 Rev. AD
Page 9 of 69
CY8C27143/CY8C27243
CY8C27443/CY8C27543
CY8C27643
28-pin Part Pinout
Table 4. Pin Definitions – 28-pin PDIP, SSOP, SOIC
Pin No.
Type
Digital
Analog
Pin
Name
Description
1
I/O
I
P0[7]
Analog column mux input
2
I/O
I/O
P0[5]
Analog column mux input and column output
3
I/O
I/O
P0[3]
Analog column mux input and column output
4
I/O
I
P0[1]
Analog column mux input
5
I/O
P2[7]
6
I/O
P2[5]
7
I/O
I
P2[3]
8
I/O
I
P2[1]
Direct switched capacitor block input
SMP
Switch mode pump (SMP) connection to external
components required
9
Power
Direct switched capacitor block input
10
I/O
P1[7]
I2C SCL
11
I/O
P1[5]
I2C SDA
12
I/O
P1[3]
13
I/O
P1[1]
14
Power
Vss
15
I/O
P1[0]
16
I/O
P1[2]
17
I/O
P1[4]
18
I/O
P1[6]
19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PDIP
SSOP
SOIC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
P0[6], A, I
P0[4], A, IO
P0[2], A, IO
P0[0], A, I
P2[6], External VRef
P2[4], External AGND
P2[2], A, I
P2[0], A, I
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2CSDA
Ground connection.
Crystal output (XTALout), I2C SDA,
ISSP-SDATA[7]
Optional external clock input (EXTCLK)
XRES
Active high external reset with internal pull down
I/O
I
P2[0]
Direct switched capacitor block input
21
I/O
I
P2[2]
Direct switched capacitor block input
22
I/O
P2[4]
External analog ground (AGND)
23
I/O
P2[6]
External voltage reference (VREF)
24
I/O
I
P0[0]
Analog column mux input
25
I/O
I/O
P0[2]
Analog column mux input and column output
26
I/O
I/O
P0[4]
Analog column mux input and column output
27
I/O
I
P0[6]
Analog column mux input
VDD
Supply voltage
Power
A, I, P0[7]
A, IO, P0[5]
A, IO, P0[3]
A, I, P0[1]
P2[7]
P2[5]
A, I, P2[3]
A, I, P2[1]
SMP
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
VSS
Crystal input (XTALin), I2C SCL, ISSP-SCLK[7]
20
28
Input
Figure 6. CY8C27443 28-pin PSoC Device
LEGEND: A = Analog, I = Input, and O = Output.
Note
7. These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
Document Number: 38-12012 Rev. AD
Page 10 of 69
CY8C27143/CY8C27243
CY8C27443/CY8C27543
CY8C27643
44-pin Part Pinout
Table 5. Pin Definitions – 44-pin TQFP
Pin Name
Figure 7. CY8C27543 44-pin PSoC Device
SMP connection to external components required
I2C SCL
I2C SDA
Crystal input (XTALin), I2C SCL, ISSP-SCLK[8]
Ground connection.
Crystal output (XTALout), I2C SDA,
ISSP-SDATA[8]
19
I/O
P1[2]
20
I/O
P1[4]
Optional external clock input (EXTCLK)
21
I/O
P1[6]
22
I/O
P3[0]
23
I/O
P3[2]
24
I/O
P3[4]
25
I/O
P3[6]
26
Input
XRES Active high external reset with internal pull down
27
I/O
P4[0]
28
I/O
P4[2]
29
I/O
P4[4]
30
I/O
P4[6]
31
I/O
I
P2[0]
Direct switched capacitor block input
32
I/O
I
P2[2]
Direct switched capacitor block input
33
I/O
P2[4]
External Analog Ground (AGND)
34
I/O
P2[6]
External Voltage Reference (VRef)
35
I/O
I
P0[0]
Analog column mux input
36
I/O
I/O
P0[2]
Analog column mux input and column output
37
I/O
I/O
P0[4]
Analog column mux input and column output
38
I/O
I
P0[6]
Analog column mux input
39
Power
VDD
Supply voltage
40
I/O
I
P0[7]
Analog column mux input
41
I/O
I/O
P0[5]
Analog column mux input and column output
42
I/O
I/O
P0[3]
Analog column mux input and column output
43
I/O
I
P0[1]
Analog column mux input
44
I/O
P2[7]
LEGEND: A = Analog, I = Input, and O = Output.
P2[7]
P0[1], A, I
P0[3], A, IO
P0[5], A, IO
P0[7], A, I
VDD
P0[6], A, I
P0[4], A, IO
P0[2], A, IO
P0[0], A, I
P2[6], External VRef
Direct switched capacitor block input
Direct switched capacitor block input
44
43
42
41
40
39
38
37
36
35
34
P2[5]
P2[3]
P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
P3[1]
P1[7]
P1[5]
P1[3]
P1[1]
Vss
P1[0]
Description
P2[5]
A, I, P2[3]
A, I, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
1
2
3
4
5
6
7
8
9
10
11
TQFP
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Type
Digital
Analog
I/O
I/O
I
I/O
I
I/O
I/O
I/O
I/O
Power
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Power
I/O
33
32
31
30
29
28
27
26
25
24
23
P2[4], External AGND
P2[2], A, I
P2[0], A, I
P4[6]
P4[4]
P4[2]
P4[0]
XRES
P3[6]
P3[4]
P3[2]
P3[1]
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
VSS
I2C SDA, XTALout, P1[0]
P1[2]
EXTCLK, P1[4]
P1[6]
P3[0]
Pin
No.
Note
8. These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
Document Number: 38-12012 Rev. AD
Page 11 of 69
CY8C27143/CY8C27243
CY8C27443/CY8C27543
CY8C27643
48-pin Part Pinout
Table 6. Pin Definitions – 48-pin Part Pinout (SSOP)
Pin
No.
Type
Pin
Digital Analog Name
Description
1
I/O
I
P0[7]
Analog column mux input
2
I/O
I/O
P0[5]
Analog column mux input and column output
3
I/O
I/O
P0[3]
Analog column mux input and column output
4
I/O
I
P0[1]
Analog column mux input
5
I/O
6
I/O
7
I/O
I
P2[3]
Direct switched capacitor block input
8
I/O
I
P2[1]
Direct switched capacitor block input
9
I/O
P4[7]
10
I/O
P4[5]
11
I/O
P4[3]
12
I/O
13
P2[7]
P2[5]
P4[1]
Power
SMP
SMP connection to external components
required
14
I/O
P3[7]
15
I/O
P3[5]
16
I/O
P3[3]
17
I/O
P3[1]
18
I/O
P5[3]
19
I/O
P5[1]
20
I/O
P1[7]
I2C SCL
21
I/O
P1[5]
I2C SDA
22
I/O
P1[3]
23
I/O
P1[1]
24
Power
Crystal Input (XTALin), I2C SCL,
ISSP-SCLK[9]
Vss
Ground connection
25
I/O
P1[0]
Crystal output (XTALout), I2C SDA,
ISSP-SDATA.[9]
26
I/O
P1[2]
27
I/O
P1[4]
28
I/O
P1[6]
29
I/O
P5[0]
30
I/O
P5[2]
31
I/O
P3[0]
32
I/O
P3[2]
33
I/O
P3[4]
34
I/O
35
A, I, P0[7]
A, IO, P0[5]
A, IO, P0[3]
A, I, P0[1]
P2[7]
P2[5]
A, I, P2[3]
A, I, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
P5[1]
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDD
P0[6], A, I
P0[4], A, IO
P0[2], A, IO
P0[0], A, I
P2[6], External VRef
P2[4], External AGND
P2[2], A, I
P2[0], A, I
P4[6]
P4[4]
P4[2]
P4[0]
XRES
P3[6]
P3[4]
P3[2]
P3[0]
P5[2]
P5[0]
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA
Optional external clock input (EXTCLK)
P3[6]
Input
XRES
Active high external reset with internal pull
down
36
I/O
P4[0]
37
I/O
P4[2]
38
I/O
P4[4]
39
I/O
40
I/O
I
P2[0]
41
I/O
I
P2[2]
Direct switched capacitor block input
42
I/O
P2[4]
External analog ground (AGND)
43
I/O
P2[6]
External voltage reference (VRef)
44
I/O
I
P0[0]
Analog column mux input
45
I/O
I/O
P0[2]
Analog column mux input and column output
46
I/O
I/O
P0[4]
Analog column mux input and column output
47
I/O
I
P0[6]
Analog column mux input
VDD
Supply voltage
48
Figure 8. CY8C27643 48-pin PSoC Device
P4[6]
Power
Direct switched capacitor block input
LEGEND: A = Analog, I = Input, and O = Output.
Note
9. These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
Document Number: 38-12012 Rev. AD
Page 12 of 69
CY8C27143/CY8C27243
CY8C27443/CY8C27543
CY8C27643
Table 7. Pin Definitions – 48-pin Part Pinout (QFN)
Description
Analog
I/O
I
P2[3]
Direct switched capacitor block input
2
I/O
I
P2[1]
Direct switched capacitor block input
3
I/O
P4[7]
4
I/O
P4[5]
5
I/O
P4[3]
6
I/O
7
P2[5]
P2[7]
P0[1], A, I
P0[3], A, IO
P0[5], A, IO
P0[7], A, I
Digital
1
P4[1]
Power
SMP
SMP connection to external components
required
8
I/O
P3[7]
9
I/O
P3[5]
10
I/O
P3[3]
11
I/O
P3[1]
12
I/O
P5[3]
13
I/O
P5[1]
14
I/O
P1[7]
I2C SCL
15
I/O
P1[5]
I2C SDA
16
I/O
P1[3]
17
I/O
P1[1]
18
Power
Crystal input (XTALin), I2C SCL,
ISSP-SCLK[11]
Vss
Ground connection.
19
I/O
P1[0]
Crystal output (XTALout), I2C SDA,
ISSP-SDATA[11]
20
I/O
P1[2]
21
I/O
P1[4]
22
I/O
P1[6]
23
I/O
P5[0]
24
I/O
P5[2]
25
I/O
P3[0]
26
I/O
P3[2]
27
I/O
P3[4]
28
I/O
29
Optional external clock input (EXTCLK)
A, I, P2[3]
A, I, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
1
2
3
4
5
6
7
8
9
10
11
12
QFN
(Top View)
36
35
34
33
32
31
30
29
28
27
26
25
P2[4], External AGND
P2[2], A, I
P2[0], A, I
P4[6]
P4[4]
P4[2]
P4[0]
XRES
P3[6]
P3[4]
P3[2]
P3[0]
P3[6]
Input
XRES
Active high external reset with internal pull
down
30
I/O
P4[0]
31
I/O
P4[2]
32
I/O
P4[4]
33
I/O
34
I/O
I
P2[0]
Direct switched capacitor block input
35
I/O
I
P2[2]
Direct switched capacitor block input
36
I/O
P2[4]
External analog ground (AGND)
37
I/O
P2[6]
External voltage reference (VREF)
38
I/O
I
P0[0]
Analog column mux input
39
I/O
I/O
P0[2]
Analog column mux input and column output
40
I/O
I/O
P0[4]
Analog column mux input and column output
41
I/O
I
P0[6]
Analog column mux input
42
Figure 9. CY8C27643 48-pin PSoC Device[10]
VDD
P0[6], A, I
P0[4], A, IO
P0[2], A, IO
P0[0], A, I
P2[6], External VRef
Pin
Name
48
47
46
45
44
43
42
41
40
39
38
37
Type
P5[1] 13
I2C SCL, P1[7] 14
I2C SDA, P1[5] 15
P1[3] 16
I2C SCL, XTALin, P1[1] 17
VSS
18
I2C SDA, XTALout, P1[0] 19
P1[2] 20
EXTCLK, P1[4] 21
P1[6] 22
P5[0] 23
P5[2] 24
Pin
No.
P4[6]
Power
VDD
Supply voltage
43
I/O
I
P0[7]
Analog column mux input
44
I/O
I/O
P0[5]
Analog column mux input and column output
45
I/O
I/O
P0[3]
Analog column mux input and column output
46
I/O
I
P0[1]
Analog column mux input
47
I/O
P2[7]
48
I/O
P2[5]
LEGEND: A = Analog, I = Input, and O = Output.
Notes
10. The QFN package has a center pad that must be connected to ground (Vss).
11. These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Technical Reference Manual for details.
Document Number: 38-12012 Rev. AD
Page 13 of 69
CY8C27143/CY8C27243
CY8C27443/CY8C27543
CY8C27643
56-pin Part Pinout
The 56-pin SSOP part is for the CY8C27002 On-Chip Debug (OCD) PSoC device.
Note This part is only used for in-circuit debugging. It is NOT available for production.
Table 8. Pin Definitions – 56-pin Part Pinout (SSOP)
Pin
No.
Type
Digital Analog
Pin
Name
1
2
3
I/O
I/O
I
I
NC
P0[7]
P0[5]
4
I/O
I
P0[3]
I
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
OCDE
OCDO
SMP
5
6
7
8
9
10
11
12
13
14
15
16
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
OCD
OCD
Power
I
I
I
I
17
18
19
20
I/O
I/O
I/O
I/O
P3[7]
P3[5]
P3[3]
P3[1]
21
I/O
P5[3]
22
23
24
25
26
27
I/O
I/O
I/O
P5[1]
P1[7]
P1[5]
NC
P1[3]
P1[1]
I/O
I/O
28
29
30
31
Power
I/O
VDD
NC
NC
P1[0]
32
33
34
35
36
37
38
39
40
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P1[2]
P1[4]
P1[6]
P5[0]
P5[2]
P3[0]
P3[2]
P3[4]
P3[6]
Description
No connection. Pin must be left floating
Analog column mux input
Analog column mux input and column
output
Analog column mux input and column
output
Analog column mux input
Direct switched capacitor block input
Direct switched capacitor block input
OCD even data I/O
OCD odd data output
SMP connection to required external
components
Figure 10. CY8C27002 56-pin PSoC Device
NC
AI, P0[7]
AIO, P0[5]
AIO, P0[3]
AI, P0[1]
P2[7]
P2[5]
AI, P2[3]
AI, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
OCDE
OCDO
SMP
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
P5[1]
I2C SCL, P1[7]
I2C SDA, P1[5]
NC
P1[3]
SCLK, I2C SCL, XTALIn, P1[1]
VSS
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SSOP
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDD
P0[6], AI
P0[4], AIO
P0[2], AIO
P0[0], AI
P2[6], External VRef
P2[4], External AGND
P2[2], AI
P2[0], AI
P4[6]
P4[4]
P4[2]
P4[0]
CCLK
HCLK
XRES
P3[6]
P3[4]
P3[2]
P3[0]
P5[2]
P5[0]
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALOut, I2C SDA, S
NC
NC
Not for Production
I2C SCL
I2C SDA
No connection. Pin must be left floating
Crystal Input (XTALin), I2C SCL,
ISSP-SCLK[12]
Supply voltage
No connection. Pin must be left floating
No connection. Pin must be left floating
Crystal output (XTALout), I2C SDA,
ISSP-SDATA[12]
Optional external clock input (EXTCLK)
Note
12. These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
Document Number: 38-12012 Rev. AD
Page 14 of 69
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CY8C27643
Table 8. Pin Definitions – 56-pin Part Pinout (SSOP) (continued)
Pin
No.
42
43
44
45
46
47
48
49
50
51
52
53
Type
Digital Analog
OCD
OCD
I/O
I/O
I/O
I/O
I/O
I
I/O
I
I/O
I/O
I/O
I
I/O
I
54
I/O
55
56
I/O
Power
Pin
Name
HCLK
CCLK
P4[0]
P4[2]
P4[4]
P4[6]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
I
P0[4]
I
P0[6]
VDD
Description
OCD high-speed clock output
OCD CPU clock output
Direct switched capacitor block input
Direct switched capacitor block input
External Analog Ground (AGND)
External Voltage Reference (VRef)
Analog column mux input
Analog column mux input and column
output
Analog column mux input and column
output
Analog column mux input
Supply voltage
LEGEND: A = Analog, I = Input, O = Output, and OCD = On-Chip Debug.
Document Number: 38-12012 Rev. AD
Page 15 of 69
CY8C27143/CY8C27243
CY8C27443/CY8C27543
CY8C27643
Register Reference
Register Mapping Tables
This section lists the registers of the CY8C27x43 PSoC device.
For detailed register information, see the PSoC Programmable
System-on-Chip Technical Reference Manual.
The PSoC device has a total register address space of
512 bytes. The register space is referred to as I/O space and is
divided into two banks. The XOI bit in the Flag register (CPU_F)
determines which bank the user is currently in. When the XOI bit
is set, the user is in Bank 1.
Note In the following register mapping tables, blank fields are
reserved and must not be accessed.
Register Conventions
The register conventions specific to this section are listed in the
following table.
Table 9. Register Conventions
Convention
R
Description
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
Table 10. Register Map Bank 0 Table: User Space
INT_CLR3
INT_MSK3
INT_MSK0
INT_MSK1
INT_VC
RES_WDT
DEC_DH
DEC_DL
DEC_CR0
DEC_CR1
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
Access
I2C_CFG
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
Addr
(0,Hex)
RW
#
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
RW
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
# Access is bit specific.
Access
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
ASC12CR0
ASC12CR1
ASC12CR2
ASC12CR3
ASD13CR0
ASD13CR1
ASD13CR2
ASD13CR3
ASD20CR0
ASD20CR1
ASD20CR2
ASD20CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
ASD22CR0
ASD22CR1
ASD22CR2
ASD22CR3
ASC23CR0
ASC23CR1
ASC23CR2
ASC23CR3
Addr
(0,Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
Name
Document Number: 38-12012 Rev. AD
Access
00
RW
01
RW
02
RW
03
RW
04
RW
05
RW
06
RW
07
RW
08
RW
09
RW
0A
RW
0B
RW
0C
RW
0D
RW
0E
RW
0F
RW
10
RW
11
RW
12
RW
13
RW
14
RW
15
RW
16
RW
17
RW
18
19
1A
1B
1C
1D
1E
1F
DBB00DR0
20
#
AMX_IN
DBB00DR1
21
W
DBB00DR2
22
RW
DBB00CR0
23
#
ARF_CR
DBB01DR0
24
#
CMP_CR0
DBB01DR1
25
W
ASY_CR
DBB01DR2
26
RW
CMP_CR1
DBB01CR0
27
#
Blank fields are Reserved and must not be accessed.
Addr
(0,Hex)
Name
Access
Addr
(0,Hex)
Name
PRT0DR
PRT0IE
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
PRT3DR
PRT3IE
PRT3GS
PRT3DM2
PRT4DR
PRT4IE
PRT4GS
PRT4DM2
PRT5DR
PRT5IE
PRT5GS
PRT5DM2
RW
#
RW
#
RW
RW
RW
RW
RW
RW
RC
W
RC
RC
RW
RW
Page 16 of 69
CY8C27143/CY8C27243
CY8C27443/CY8C27543
CY8C27643
Table 10. Register Map Bank 0 Table: User Space (continued)
RW
RW
RW
RW
RW
RW
RW
CPU_F
RW
RW
RW
RW
RW
RW
RW
CPU_SCR1
CPU_SCR0
Access
MUL_X
MUL_Y
MUL_DH
MUL_DL
ACC_DR1
ACC_DR0
ACC_DR3
ACC_DR2
Addr
(0,Hex)
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
A8
A9
AA
AB
AC
AD
AE
AF
RDI0RI
B0
RDI0SYN
B1
RDI0IS
B2
RDI0LT0
B3
RDI0LT1
B4
RDI0RO0
B5
RDI0RO1
B6
B7
RDI1RI
B8
RDI1SYN
B9
RDI1IS
BA
RDI1LT0
BB
RDI1LT1
BC
RDI1RO0
BD
RDI1RO1
BE
BF
# Access is bit specific.
Access
Addr
(0,Hex)
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Name
Access
Addr
(0,Hex)
Name
Access
Addr
(0,Hex)
Name
DCB02DR0
28
#
DCB02DR1
29
W
DCB02DR2
2A
RW
DCB02CR0
2B
#
DCB03DR0
2C
#
DCB03DR1
2D
W
DCB03DR2
2E
RW
DCB03CR0
2F
#
DBB10DR0
30
#
ACB00CR3
DBB10DR1
31
W
ACB00CR0
DBB10DR2
32
RW
ACB00CR1
DBB10CR0
33
#
ACB00CR2
DBB11DR0
34
#
ACB01CR3
DBB11DR1
35
W
ACB01CR0
DBB11DR2
36
RW
ACB01CR1
DBB11CR0
37
#
ACB01CR2
DCB12DR0
38
#
ACB02CR3
DCB12DR1
39
W
ACB02CR0
DCB12DR2
3A
RW
ACB02CR1
DCB12CR0
3B
#
ACB02CR2
DCB13DR0
3C
#
ACB03CR3
DCB13DR1
3D
W
ACB03CR0
DCB13DR2
3E
RW
ACB03CR1
DCB13CR0
3F
#
ACB03CR2
Blank fields are Reserved and must not be accessed.
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
W
W
R
R
RW
RW
RW
RW
RL
#
#
Table 11. Register Map Bank 1 Table: Configuration Space
OSC_GO_EN
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
Access
GDI_O_IN
GDI_E_IN
GDI_O_OU
GDI_E_OU
Addr
(1,Hex)
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
ASC10CR0
80
ASC10CR1
81
ASC10CR2
82
ASC10CR3
83
ASD11CR0
84
ASD11CR1
85
ASD11CR2
86
ASD11CR3
87
ASC12CR0
88
ASC12CR1
89
ASC12CR2
8A
ASC12CR3
8B
ASD13CR0
8C
ASD13CR1
8D
ASD13CR2
8E
ASD13CR3
8F
ASD20CR0
90
ASD20CR1
91
ASD20CR2
92
ASD20CR3
93
ASC21CR0
94
ASC21CR1
95
ASC21CR2
96
ASC21CR3
97
ASD22CR0
98
ASD22CR1
99
ASD22CR2
9A
ASD22CR3
9B
ASC23CR0
9C
ASC23CR1
9D
# Access is bit specific.
Access
Addr
(1,Hex)
Name
Document Number: 38-12012 Rev. AD
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
Access
00
RW
01
RW
02
RW
03
RW
04
RW
05
RW
06
RW
07
RW
08
RW
09
RW
0A
RW
0B
RW
0C
RW
0D
RW
0E
RW
0F
RW
10
RW
11
RW
12
RW
13
RW
14
RW
15
RW
16
RW
17
RW
18
19
1A
1B
1C
1D
Blank fields are Reserved and must not be accessed.
Addr
(1,Hex)
Name
Access
Addr
(1,Hex)
Name
PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
PRT3DM0
PRT3DM1
PRT3IC0
PRT3IC1
PRT4DM0
PRT4DM1
PRT4IC0
PRT4IC1
PRT5DM0
PRT5DM1
PRT5IC0
PRT5IC1
RW
RW
RW
RW
RW
Page 17 of 69
CY8C27143/CY8C27243
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CY8C27643
Table 11. Register Map Bank 1 Table: Configuration Space (continued)
IMO_TR
ILO_TR
BDG_TR
ECO_TR
RW
RW
RW
RW
RW
RW
RW
CPU_F
RW
RW
RW
RW
RW
RW
RW
CPU_SCR1
CPU_SCR0
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
OSC_CR4
OSC_CR3
OSC_CR0
OSC_CR1
OSC_CR2
VLT_CR
VLT_CMP
Addr
(1,Hex)
RW
RW
RW
RW
RW
RW
Name
RW
RW
RW
RW
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
RDI0RI
B0
RDI0SYN
B1
RDI0IS
B2
RDI0LT0
B3
RDI0LT1
B4
RDI0RO0
B5
RDI0RO1
B6
B7
RDI1RI
B8
RDI1SYN
B9
RDI1IS
BA
RDI1LT0
BB
RDI1LT1
BC
RDI1RO0
BD
RDI1RO1
BE
BF
# Access is bit specific.
Access
ASC23CR2
ASC23CR3
Addr
(1,Hex)
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Name
Access
Document Number: 38-12012 Rev. AD
Addr
(1,Hex)
Name
Access
Addr
(1,Hex)
Name
1E
1F
DBB00FN
20
RW
CLK_CR0
DBB00IN
21
RW
CLK_CR1
DBB00OU
22
RW
ABF_CR0
23
AMD_CR0
DBB01FN
24
RW
DBB01IN
25
RW
DBB01OU
26
RW
AMD_CR1
27
ALT_CR0
DCB02FN
28
RW
ALT_CR1
DCB02IN
29
RW
CLK_CR2
DCB02OU
2A
RW
2B
DCB03FN
2C
RW
DCB03IN
2D
RW
DCB03OU
2E
RW
2F
DBB10FN
30
RW
ACB00CR3
DBB10IN
31
RW
ACB00CR0
DBB10OU
32
RW
ACB00CR1
33
ACB00CR2
DBB11FN
34
RW
ACB01CR3
DBB11IN
35
RW
ACB01CR0
DBB11OU
36
RW
ACB01CR1
37
ACB01CR2
DCB12FN
38
RW
ACB02CR3
DCB12IN
39
RW
ACB02CR0
DCB12OU
3A
RW
ACB02CR1
3B
ACB02CR2
DCB13FN
3C
RW
ACB03CR3
DCB13IN
3D
RW
ACB03CR0
DCB13OU
3E
RW
ACB03CR1
3F
ACB03CR2
Blank fields are Reserved and must not be accessed.
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
RW
RW
RW
RW
RW
RW
R
W
W
RW
W
RL
#
#
Page 18 of 69
CY8C27143/CY8C27243
CY8C27443/CY8C27543
CY8C27643
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C27x43 PSoC device. For the most up to date electrical
specifications, confirm that you have the most recent datasheet by going to the web at http://www.cypress.com.
Specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications for devices running at greater
than 12 MHz are valid for –40 °C TA 70 °C and TJ 82 °C.
Figure 11. Voltage versus CPU Frequency
5.25
Vdd Voltage
l id g
Va atin
n
r
pe gio
Re
O
4.75
3.00
93 kHz
12 MHz
CPU Fre que ncy
24 MHz
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Table 12. Absolute Maximum Ratings
Symbol
Description
Min
Typ
Max
Unit
–55
25
+100
°C
–
125
See
package
label
°C
See
package
label
–
72
Hours
Ambient temperature with power applied
–40
–
+85
°C
Supply voltage on VDD relative to Vss
–0.5
–
+6.0
V
DC input voltage
Vss – 0.5
–
VDD + 0.5
V
DC voltage applied to tristate
Vss – 0.5
–
VDD + 0.5
V
Maximum current into any port pin
–25
–
+50
mA
IMAIO
Maximum current into any port pin configured as
analog driver
–50
–
+50
mA
ESD
Electrostatic discharge voltage
2000
–
–
V
LU
Latch-up current
–
–
200
mA
TSTG
Storage temperature
TBAKETEMP
Bake temperature
tBAKETIME
Bake time
TA
VDD
VIO
VIOZ
IMIO
Document Number: 38-12012 Rev. AD
Notes
Higher storage temperatures
reduce data retention time.
Recommended storage
temperature is +25 °C ± 25 °C.
Extended duration storage
temperatures above 65 °C
degrade reliability.
Human body model ESD.
Page 19 of 69
CY8C27143/CY8C27243
CY8C27443/CY8C27543
CY8C27643
Operating Temperature
Table 13. Operating Temperature
Symbol
TA
TJ
Description
Ambient temperature
Junction temperature
Min
–40
–40
Typ
–
–
Max
+85
+100
Unit
°C
°C
Notes
The temperature rise from ambient
to junction is package specific. See
Thermal Impedances on page 50.
The user must limit the power
consumption to comply with this
requirement.
DC Electrical Characteristics
DC Chip-Level Specifications
Table 14 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and
are for design guidance only.
Table 14. DC Chip-Level Specifications
Symbol
VDD
Supply voltage
IDD
Supply current
Description
Min
3.00
–
Typ
–
5
Max
5.25
8
Unit
V
mA
IDD3
Supply current
–
3.3
6.0
mA
ISB
Sleep (Mode) current with POR, LVD, sleep timer,
and WDT.[13]
–
3
6.5
A
ISBH
Sleep (Mode) current with POR, LVD, sleep timer,
and WDT at high temperature.[13]
–
4
25
A
ISBXTL
Sleep (Mode) current with POR, LVD, sleep timer,
WDT, and external crystal.[13]
–
4
7.5
A
ISBXTLH
Sleep (Mode) current with POR, LVD, sleep timer,
WDT, and external crystal at high temperature.[13]
–
5
26
A
VREF
VREF
Reference voltage (Bandgap) for Silicon A [14]
Reference voltage (Bandgap) for Silicon B [14]
1.275
1.280
1.300
1.300
1.325
1.320
V
V
Notes
Conditions are VDD = 5.0 V,
TA = 25 °C, CPU = 3 MHz, SYSCLK
doubler disabled. VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 93.75 kHz.
Conditions are VDD = 3.3 V,
TA = 25 °C, CPU = 3 MHz, SYSCLK
doubler disabled. VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 93.75 kHz.
Conditions are with internal slow speed
oscillator, VDD = 3.3 V,
–40 °C TA 55 °C.
Conditions are with internal slow speed
oscillator, VDD = 3.3 V,
55 °C < TA 85 °C.
Conditions are with properly loaded, 1
µW max, 32.768 kHz crystal.
VDD = 3.3 V, –40 °C TA 55 °C.
Conditions are with properly loaded,
1 W max, 32.768 kHz crystal.
VDD = 3.3 V, 55 °C < TA 85 °C.
Trimmed for appropriate VDD.
Trimmed for appropriate VDD.
Notes
13. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This must be compared with devices that have similar
functions enabled.
14. Refer to the Ordering Information on page 53.
Document Number: 38-12012 Rev. AD
Page 20 of 69
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DC GPIO Specifications
Table 15 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C
TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for
design guidance only.
Table 15. DC GPIO Specifications
Symbol
Description
Pull-up resistor
RPU
Pull-down resistor
RPD
High output level
VOH
Min
4
4
VDD – 1.0
Typ
5.6
5.6
–
Max
8
8
–
Unit
k
k
V
VOL
Low output level
–
–
0.75
V
IOH
High-level source current
10
–
–
mA
IOL
Low-level sink current
25
–
–
mA
VIL
VIH
VH
IIL
CIN
Input low level
Input high level
Input hysterisis
Input leakage (absolute value)
Capacitive load on pins as input
–
2.1
–
–
–
–
–
60
1
3.5
0.8
–
–
10
V
V
mV
nA
pF
COUT
Capacitive load on pins as output
–
3.5
10
pF
Notes
IOH = 10 mA, VDD = 4.75 to 5.25 V
(8 total loads, 4 on even port pins (for
example, P0[2], P1[4]), 4 on odd port pins
(for example, P0[3], P1[5])).
IOL = 25 mA, VDD = 4.75 to 5.25 V (8 total
loads, 4 on even port pins (for example,
P0[2], P1[4]), 4 on odd port pins (for
example, P0[3], P1[5])).
VOH = VDD – 1.0 V, see the limitations of
the total current in the note for VOH
VOL = 0.75 V, see the limitations of the
total current in the note for VOL
VDD = 3.0 to 5.25
VDD = 3.0 to 5.25
Gross tested to 1 A.
Package and pin dependent.
Temp = 25 °C.
Package and pin dependent.
Temp = 25 °C.
DC Operational Amplifier Specifications
Table 16 and Table 17 list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
The operational amplifier is a component of both the analog continuous time PSoC blocks and the analog switched cap PSoC blocks.
The guaranteed specifications are measured in the analog continuous time PSoC block. Typical parameters apply to 5 V at 25 °C and
are for design guidance only.
Table 16. 5-V DC Operational Amplifier Specifications
Symbol
Description
Min
Typ
Max
Units
1.6
1.6
1.6
1.6
1.6
1.6
10
10
10
10
10
10
mV
mV
mV
mV
mV
mV
Notes
VOSOA
Input offset voltage (absolute value)
Power = low, Opamp bias = low
Power = low, Opamp bias = high
Power = medium, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = low
Power = high, Opamp bias = high
–
–
–
–
–
–
TCVOSOA
Average input offset voltage drift
–
4
20
µV/°C
IEBOA
Input leakage current (port 0 analog pins)
–
20
–
pA
Gross tested to 1 µA.
CINOA
Input capacitance (port 0 analog pins)
–
4.5
9.5
pF
Package and pin dependent. Temp = 25 °C
VCMOA
Common mode voltage range
0
–
VDD
V
The common-mode input voltage range is
measured through an analog output buffer.
The specification includes the limitations
imposed by the characteristics of the analog
output buffer.
0.5
–
VDD –
0.5
V
Common mode voltage range (high
power or high Opamp bias)
Document Number: 38-12012 Rev. AD
Page 21 of 69
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CY8C27443/CY8C27543
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Table 16. 5-V DC Operational Amplifier Specifications
Symbol
Description
Min
Typ
Max
Units
CMRROA
Common mode rejection ratio
Power = low, Opamp bias = high
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
60
60
60
–
–
–
–
–
–
dB
dB
dB
GOLOA
Open loop gain
Power = low, Opamp bias = high
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
60
60
80
–
–
–
–
–
–
dB
dB
dB
VDD – 0.2
VDD – 0.2
VDD – 0.5
–
–
–
–
–
–
V
V
V
Low output voltage swing (internal
signals)
Power = low, Opamp bias = high
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
–
–
–
–
–
–
0.2
0.2
0.5
V
V
V
Supply current (including associated
AGND buffer)
Power = low, Opamp bias = low
Power = low, Opamp bias = high
Power = medium, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = low
Power = high, Opamp bias = high
–
–
–
–
–
–
150
300
600
1200
2400
4600
200
400
800
1600
3200
6400
µA
µA
µA
µA
µA
µA
Supply voltage rejection ratio
60
–
–
dB
VOHIGHOA High output voltage swing (internal
signals)
Power = low, Opamp bias = high
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
VOLOWOA
ISOA
PSRROA
Notes
Specification is applicable at both High and
Low opamp bias.
Specification is applicable at High opamp
bias. For Low opamp bias mode, minimum is
60 dB.
Vss VIN (VDD – 2.25) or (VDD – 1.25 V)
VIN VDD.
Table 17. 3.3-V DC Operational Amplifier Specifications
Symbol
Description
Min
Typ
Max
Unit
–
–
–
–
–
–
1.4
1.4
1.4
1.4
1.4
–
10
10
10
10
10
–
mV
mV
mV
mV
mV
mV
Notes
VOSOA
Input offset voltage (absolute value)
Power = low, Opamp bias = low
Power = low, Opamp bias = high
Power = medium, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = low
Power = high, Opamp bias = high
TCVOSOA
Average input offset voltage drift
–
7
40
µV/°C
IEBOA
Input leakage current (port 0 analog pins)
–
20
–
pA
Gross tested to 1µA.
CINOA
Input capacitance (port 0 analog pins)
–
4.5
9.5
pF
Package and pin dependent.
Temp = 25 °C.
VCMOA
Common mode voltage range
0.2
–
VDD – 0.2
V
The common-mode input voltage
range is measured through an analog
output buffer. The specification
includes the limitations imposed by the
characteristics of the analog output
buffer.
CMRROA
Common mode rejection ratio
Power = low, Opamp bias = low
Power = medium, Opamp bias = low
Power = high, Opamp bias = low
50
50
50
–
–
–
–
–
–
dB
dB
dB
Specification is applicable at Low
opamp bias. For High bias mode
(except High Power, High opamp
bias), minimum is 60 dB.
GOLOA
Open loop gain
Power = low, Opamp bias = low
Power = medium, Opamp bias = low
Power = high, Opamp bias = low
60
60
80
–
–
–
–
–
–
dB
dB
dB
Specification is applicable at Low
opamp bias. For High opamp bias
mode (except High Power, High
opamp bias), minimum is 60 dB.
Document Number: 38-12012 Rev. AD
Power = high, Opamp bias = high
setting is not allowed for 3.3 V VDD
operation.
Page 22 of 69
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Table 17. 3.3-V DC Operational Amplifier Specifications (continued)
Symbol
Description
Min
Typ
Max
Unit
VOHIGHOA
High output voltage swing (internal signals)
Power = low, Opamp bias = low
VDD – 0.2
VDD – 0.2
Power = medium, Opamp bias = low
VDD – 0.2
Power = high, Opamp bias = low
–
–
–
–
–
–
V
V
V
VOLOWOA
Low output voltage swing (internal signals)
Power = low, Opamp bias = low
Power = medium, Opamp bias = low
Power = high, Opamp bias = low
–
–
–
0.2
0.2
0.2
V
V
V
ISOA
Supply current (including associated
AGND buffer)
Power = low, Opamp bias = low
Power = low, Opamp bias = high
Power = medium, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = low
Power = high, Opamp bias = high
–
–
–
–
–
–
150
300
600
1200
2400
–
200
400
800
1600
3200
–
µA
µA
µA
µA
µA
µA
Supply voltage rejection ratio
50
80
–
dB
PSRROA
–
–
–
Notes
Power = high, Opamp bias = high
setting is not allowed for 3.3 V VDD
operation.
Power = high, Opamp bias = high
setting is not allowed for 3.3 V VDD
operation.
Power = high, Opamp bias = high
setting is not allowed for 3.3 V VDD
operation.
VSS VIN (VDD – 2.25) or
(VDD – 1.25 V) VIN VDD.
DC Low-Power Comparator Specifications
Table 18 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
apply to 5 V at 25 °C and are for design guidance only.
Table 18. DC Low-Power Comparator Specifications
Symbol
VREFLPC
ISLPC
VOSLPC
Description
Low-power comparator (LPC) reference voltage range
LPC supply current
LPC voltage offset
Min
0.2
–
–
Typ
–
10
2.5
Max
VDD – 1
40
30
Unit
V
A
mV
DC Analog Output Buffer Specifications
Table 19 and Table 20 on page 24 list guaranteed maximum and minimum specifications for the voltage and temperature ranges:
4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V
and 3.3 V at 25 °C and are for design guidance only.
Table 19. 5-V DC Analog Output Buffer Specifications
Symbol
VOSOB
TCVOSOB
VCMOB
ROUTOB
VOHIGHOB
VOLOWOB
Description
Input offset voltage (absolute value)
Power = low, Opamp bias = low
Power = low, Opamp bias = high
Power = high, Opamp bias = low
Power = high, Opamp bias = high
Average input offset voltage drift
Common-mode input voltage range
Output resistance
Power = low
Power = high
High output voltage swing (Load =
32 ohms to VDD/2)
Power = low
Power = high
Low output voltage swing (Load =
32 ohms to VDD/2)
Power = low
Power = high
Document Number: 38-12012 Rev. AD
Min
Typ
Max
Unit
–
–
–
–
–
0.5
3
3
3
3
5
–
19
19
19
19
30
VDD – 1.0
mV
mV
mV
mV
µV/°C
V
–
–
1
1
–
–
0.5 × VDD + 1.3
0.5 × VDD + 1.3
–
–
–
–
–
–
–
V
V
–
–
–
–
0.5 × VDD – 1.3
0.5 × VDD – 1.3
V
V
Notes
Page 23 of 69
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Table 19. 5-V DC Analog Output Buffer Specifications (continued)
Symbol
ISOB
PSRROB
IOMAX
CL
Description
Supply current including opamp
bias cell (no load)
Power = low
Power = high
Supply voltage rejection ratio
Maximum output current
Load capacitance
Min
Typ
Max
Unit
–
–
60
–
–
1.1
2.6
64
40
–
5.1
8.8
–
–
200
mA
mA
dB
mA
pF
Min
Typ
Max
Unit
–
–
–
–
3.2
3.2
6
6
20
20
25
25
mV
mV
mV
mV
–
–
–
–
0.5
9
9
12
12
–
55
55
70
70
VDD – 1.0
µV/°C
µV/°C
µV/°C
µV/°C
V
–
–
1
1
–
–
0.5 × VDD + 1.0
0.5 × VDD + 1.0
–
–
–
–
V
V
–
–
–
–
0.5 × VDD – 1.0
0.5 × VDD – 1.0
V
V
–
–
60
–
0.8
2.0
64
–
2
4.3
–
200
mA
mA
dB
pF
Notes
This specification applies to the
external circuit driven by the
analog output buffer.
Table 20. 3.3-V DC Analog Output Buffer Specifications
Symbol
VOSOB
TCVOSOB
VCMOB
ROUTOB
VOHIGHOB
VOLOWOB
ISOB
PSRROB
CL
Description
Input offset voltage (absolute value)
Power = low, Opamp bias = low
Power = low, Opamp bias = high
Power = high, Opamp bias = low
Power = high, Opamp bias = high
Average input offset voltage drift
Power = low, Opamp bias = low
Power = low, Opamp bias = high
Power = high, Opamp bias = low
Power = high, Opamp bias = high
Common-mode input voltage range
Output resistance
Power = low
Power = high
High output voltage swing
(load = 32 ohms to VDD/2)
Power = low
Power = high
Low output voltage swing
(load = 32 ohms to VDD/2)
Power = low
Power = high
Supply current including opamp
bias cell (no load)
Power = low
Power = high
Supply voltage rejection ratio
Load capacitance
Document Number: 38-12012 Rev. AD
Notes
High power setting is not
recommended.
High power setting is not
recommended.
This specification applies to the
external circuit driven by the
analog output buffer.
Page 24 of 69
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DC Switch Mode Pump Specifications
Table 21 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and
are for design guidance only.
Table 21. DC Switch Mode Pump (SMP) Specifications
Min
Typ
Max
Unit
Notes
VPUMP 5 V
Symbol
5 V output voltage
Description
4.75
5.0
5.25
V
Configured as in Note 15. Average,
neglecting ripple. SMP trip voltage is
set to 5.0 V.
VPUMP 3 V
3 V output voltage
3.00
3.25
3.60
V
Configured as in Note 15. Average,
neglecting ripple. SMP trip voltage is
set to 3.25 V.
IPUMP
Available output current
VBAT = 1.5 V, VPUMP = 3.25 V
VBAT = 1.8 V, VPUMP = 5.0 V
8
5
–
–
–
–
mA
mA
Configured as in Note 15. SMP trip
voltage is set to 3.25 V.
SMP trip voltage is set to 5.0 V.
VBAT5 V
Input voltage range from battery
1.8
–
5.0
V
Configured as in Note 15. SMP trip
voltage is set to 5.0 V.
VBAT3 V
Input voltage range from battery
1.0
–
3.3
V
Configured as in Note 15. SMP trip
voltage is set to 3.25 V.
VBATSTART
Minimum input voltage from battery to start
pump
1.1
–
–
V
Configured as in Note 15.
VPUMP_Line
Line regulation (over VBAT range)
–
5
–
%VO
Configured as in Note 15. VO is the
“VDD Value for PUMP Trip” specified
by the VM[2:0] setting in the DC POR
and LVD Specification, Table 25 on
page 33.
VPUMP_Load
Load regulation
–
5
–
%VO
Configured as in Note 15. VO is the
“VDD Value for PUMP Trip” specified
by the VM[2:0] setting in the DC POR
and LVD Specification, Table 25 on
page 33.
VPUMP_Ripple
Output voltage ripple (depends on
capacitor/load)
–
100
–
mVpp
Configured as in Note 15. Load is
5 mA.
E3
Efficiency
35
50
–
%
Configured as in Note 15. Load is
5 mA. SMP trip voltage is set to
3.25 V.
FPUMP
Switching frequency
–
1.3
–
MHz
DCPUMP
Switching duty cycle
–
50
–
%
Figure 12. Basic Switch Mode Pump Circuit
D1
Vdd
L1
V BAT
+
V PUMP
C1
SMP
Battery
PSoC TM
Vss
Note
15. L1 = 2 mH inductor, C1 = 10 mF capacitor, D1 = Schottky diode. See Figure 12.
Document Number: 38-12012 Rev. AD
Page 25 of 69
CY8C27143/CY8C27243
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DC Analog Reference Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85°C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to
the power of the analog continuous time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Reference control power is high.
Note Avoid using P2[4] for digital signaling when using an analog resource that depends on the Analog Reference. Some coupling
of the digital signal may appear on the AGND.
Table 22. 5-V DC Analog Reference Specifications
Reference
ARF_CR
[5:3]
Reference Power
Settings
Symbol
Reference
RefPower = high
Opamp bias = high
VREFHI
Ref High
RefPower = high
Opamp bias = low
0b000
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
VAGND
AGND
VREFLO
Ref Low
VREFHI
Ref High
VAGND
AGND
VREFLO
Ref Low
VREFHI
Ref High
VAGND
AGND
VREFLO
Ref Low
VREFHI
Ref High
VAGND
AGND
VREFLO
Ref Low
Description
Min
Typ
Max
Unit
VDD/2 + Bandgap
VDD/2 + 1.228
VDD/2 + 1.290
VDD/2 + 1.352
V
VDD/2
VDD/2 – 0.078
VDD/2 – 0.007
VDD/2 + 0.063
V
VDD/2 – Bandgap
VDD/2 – 1.336
VDD/2 – 1.295
VDD/2 – 1.250
V
V
VDD/2 + Bandgap
VDD/2 + 1.224
VDD/2 + 1.293
VDD/2 + 1.356
VDD/2
VDD/2 – 0.056
VDD/2 – 0.005
VDD/2 + 0.043
V
VDD/2 – Bandgap
VDD/2 – 1.338
VDD/2 – 1.298
VDD/2 – 1.255
V
V
VDD/2 + Bandgap
VDD/2 + 1.226
VDD/2 + 1.293
VDD/2 + 1.356
VDD/2
VDD/2 – 0.057
VDD/2 – 0.006
VDD/2 + 0.044
V
VDD/2 – Bandgap
VDD/2 – 1.337
VDD/2 – 1.298
VDD/2 – 1.256
V
VDD/2 + Bandgap
VDD/2 + 1.226
VDD/2 + 1.294
VDD/2 + 1.359
V
VDD/2
VDD/2 – 0.047
VDD/2 – 0.004
VDD/2 + 0.035
V
VDD/2 – Bandgap
VDD/2 – 1.338
VDD/2 – 1.299
VDD/2 – 1.258
V
Note
16. AGND tolerance includes the offsets of the local buffer in the PSoC block.
Document Number: 38-12012 Rev. AD
Page 26 of 69
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Table 22. 5-V DC Analog Reference Specifications (continued)
Reference
ARF_CR
[5:3]
Reference Power
Settings
Symbol
Reference
Description
Min
RefPower = high
Opamp bias = high
VREFHI
Ref High
P2[4] + P2[6] (P2[4]
= VDD/2, P2[6] =
1.3 V)
P2[4] + P2[6] –
0.085
RefPower = high
Opamp bias = low
0b001
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
0b010
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
Typ
Max
P2[4] + P2[6] – P2[4] + P2[6] +
0.016
0.044
Unit
V
VAGND
AGND
VREFLO
Ref Low
P2[4] – P2[6] (P2[4]
= VDD/2, P2[6] =
1.3 V)
P2[4] – P2[6] –
0.022
P2[4] – P2[6] + P2[4] – P2[6] +
0.010
0.055
V
VREFHI
Ref High
P2[4] + P2[6] (P2[4]
= VDD/2, P2[6] =
1.3 V)
P2[4] + P2[6] –
0.077
P2[4] + P2[6] – P2[4] + P2[6] +
0.010
0.051
V
P2[4]
P2[4]
P2[4]
P2[4]
–
VAGND
AGND
VREFLO
Ref Low
P2[4] – P2[6] (P2[4]
= VDD/2, P2[6] =
1.3 V)
P2[4] – P2[6] –
0.022
P2[4] – P2[6] + P2[4] – P2[6] +
0.005
0.039
V
VREFHI
Ref High
P2[4] + P2[6] (P2[4]
= VDD/2, P2[6] =
1.3 V)
P2[4] + P2[6] –
0.070
P2[4] + P2[6] – P2[4] + P2[6] +
0.010
0.050
V
VAGND
AGND
VREFLO
Ref Low
P2[4] – P2[6] (P2[4]
= VDD/2, P2[6] =
1.3 V)
P2[4] – P2[6] –
0.022
P2[4] – P2[6] + P2[4] – P2[6] +
0.005
0.039
V
VREFHI
Ref High
P2[4] + P2[6] (P2[4]
= VDD/2, P2[6] =
1.3 V)
P2[4] + P2[6] –
0.070
P2[4] + P2[6] – P2[4] + P2[6] +
0.007
0.054
V
VAGND
AGND
VREFLO
Ref Low
VREFHI
Ref High
VAGND
AGND
P2[4]
P2[4]
P2[4]
P2[4] – P2[6] (P2[4]
= VDD/2, P2[6] =
1.3 V)
VDD
VDD/2
P2[4]
P2[4]
P2[4]
P2[4] – P2[6] –
0.022
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4] – P2[6] + P2[4] – P2[6] +
0.002
0.032
–
–
–
V
VDD – 0.037
VDD – 0.009
VDD
V
VDD/2 – 0.061
VDD/2 – 0.006
VDD/2 + 0.047
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.007
VSS + 0.028
V
VREFHI
Ref High
VDD
VDD – 0.039
VDD – 0.006
VDD
V
VAGND
AGND
VDD/2 – 0.049
VDD/2 – 0.005
VDD/2 + 0.036
V
VDD/2
VREFLO
Ref Low
VSS
VSS
VSS + 0.005
VSS + 0.019
V
VREFHI
Ref High
VDD
VDD – 0.037
VDD – 0.007
VDD
V
VAGND
AGND
VDD/2 – 0.054
VDD/2 – 0.005
VDD/2 + 0.041
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.006
VSS + 0.024
V
VREFHI
Ref High
VDD
VDD – 0.042
VDD – 0.005
VDD
V
VDD/2 – 0.046
VDD/2 – 0.004
VDD/2 + 0.034
V
VSS
VSS + 0.004
VSS + 0.017
V
VAGND
AGND
VREFLO
Ref Low
Document Number: 38-12012 Rev. AD
VDD/2
VDD/2
VSS
Page 27 of 69
CY8C27143/CY8C27243
CY8C27443/CY8C27543
CY8C27643
Table 22. 5-V DC Analog Reference Specifications (continued)
Reference
ARF_CR
[5:3]
Reference Power
Settings
Symbol
Reference
RefPower = high
Opamp bias = high
VREFHI
Ref High
RefPower = high
Opamp bias = low
0b011
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
0b100
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
Description
3 × Bandgap
Min
Typ
Max
Unit
3.788
3.891
3.986
V
VAGND
AGND
2 × Bandgap
2.500
2.604
3.699
V
VREFLO
Ref Low
Bandgap
1.257
1.306
1.359
V
VREFHI
Ref High
3 × Bandgap
3.792
3.893
3.982
V
VAGND
AGND
2 × Bandgap
2.518
2.602
2.692
V
VREFLO
Ref Low
Bandgap
1.256
1.302
1.354
V
VREFHI
Ref High
3 × Bandgap
3.795
3.894
3.993
V
VAGND
AGND
2 × Bandgap
2.516
2.603
2.698
V
VREFLO
Ref Low
Bandgap
1.256
1.303
1.353
V
VREFHI
Ref High
3 × Bandgap
3.792
3.895
3.986
V
VAGND
AGND
2 × Bandgap
2.522
2.602
2.685
V
VREFLO
Ref Low
Bandgap
VREFHI
Ref High
2 × Bandgap + P2[6]
(P2[6] = 1.3 V)
2 × Bandgap
1.255
1.301
1.350
V
2.495 – P2[6]
2.586 – P2[6]
2.657 – P2[6]
V
VAGND
AGND
2.502
2.604
2.719
V
VREFLO
Ref Low
2 × Bandgap – P2[6]
(P2[6] = 1.3 V)
2.531 – P2[6]
2.611 – P2[6]
2.681 – P2[6]
V
VREFHI
Ref High
2 × Bandgap + P2[6]
(P2[6] = 1.3 V)
2.500 – P2[6]
2.591 – P2[6]
2.662 – P2[6]
V
VAGND
AGND
2.519
2.602
2.693
V
VREFLO
Ref Low
2 × Bandgap – P2[6]
(P2[6] = 1.3 V)
2.530 – P2[6]
2.605 – P2[6]
2.666 – P2[6]
V
VREFHI
Ref High
2 × Bandgap + P2[6]
(P2[6] = 1.3 V)
2.503 – P2[6]
2.592 – P2[6]
2.662 – P2[6]
V
2 × Bandgap
VAGND
AGND
2.517
2.603
2.698
V
VREFLO
Ref Low
2 × Bandgap – P2[6]
(P2[6] = 1.3 V)
2.529 – P2[6]
2.606 – P2[6]
2.665 – P2[6]
V
VREFHI
Ref High
2 × Bandgap + P2[6]
(P2[6] = 1.3 V)
2.505 – P2[6]
2.594 – P2[6]
2.665 – P2[6]
V
VAGND
AGND
VREFLO
Ref Low
Document Number: 38-12012 Rev. AD
2 × Bandgap
2 × Bandgap
2 × Bandgap – P2[6]
(P2[6] = 1.3 V)
2.525
2.602
2.685
V
2.528 – P2[6]
2.603 – P2[6]
2.661 – P2[6]
V
Page 28 of 69
CY8C27143/CY8C27243
CY8C27443/CY8C27543
CY8C27643
Table 22. 5-V DC Analog Reference Specifications (continued)
Reference
ARF_CR
[5:3]
Reference Power
Settings
Symbol
Reference
RefPower = high
Opamp bias = high
VREFHI
Ref High
VAGND
AGND
VREFLO
Ref Low
VREFHI
Ref High
RefPower = high
Opamp bias = low
0b101
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
0b110
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
0b111
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
Description
Min
Typ
Max
Unit
P2[4] + 1.222
P2[4] + 1.290
P2[4] + 1.343
V
P2[4]
P2[4]
P2[4]
–
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.331
P2[4] – 1.295
P2[4] – 1.254
V
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.226
P2[4] + 1.293
P2[4] + 1.347
V
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4]
VAGND
AGND
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4]
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.331
P2[4] – 1.298
P2[4] – 1.259
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.227
P2[4] + 1.294
P2[4] + 1.347
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.331
P2[4] – 1.298
P2[4] – 1.259
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.228
P2[4] + 1.295
P2[4] + 1.349
V
P2[4]
VAGND
AGND
VREFLO
Ref Low
P2[4]
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4]
P2[4]
P2[4]
–
P2[4] – 1.332
P2[4] – 1.299
P2[4] – 1.260
V
VREFHI
Ref High
VAGND
AGND
2 × Bandgap
2.535
2.598
2.644
V
Bandgap
1.227
1.305
1.398
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.009
VSS + 0.038
V
VREFHI
Ref High
2 × Bandgap
2.530
2.598
2.643
V
VAGND
AGND
Bandgap
1.244
1.303
1.370
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.005
VSS + 0.024
V
VREFHI
Ref High
2 × Bandgap
2.532
2.598
2.644
V
Bandgap
1.239
1.304
1.380
V
VSS
VSS + 0.006
VSS + 0.026
V
2.598
2.645
V
V
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
2 × Bandgap
2.528
Bandgap
1.249
1.302
1.362
VSS
VSS + 0.004
VSS + 0.018
V
4.155
4.234
V
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
3.2 × Bandgap
4.041
1.6 × Bandgap
1.998
2.083
2.183
V
VSS
VSS + 0.010
VSS + 0.038
V
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
3.2 × Bandgap
4.047
4.153
4.236
V
VAGND
AGND
1.6 × Bandgap
2.012
2.082
2.157
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.006
VSS + 0.024
V
VREFHI
Ref High
3.2 × Bandgap
4.049
4.154
4.238
V
VAGND
AGND
1.6 × Bandgap
2.008
2.083
2.165
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.006
VSS + 0.026
V
VREFHI
Ref High
3.2 × Bandgap
4.047
4.154
4.238
V
VAGND
AGND
1.6 × Bandgap
2.016
2.081
2.150
V
VREFLO
Ref Low
VSS
VSS + 0.004
VSS + 0.018
V
Document Number: 38-12012 Rev. AD
VSS
Page 29 of 69
CY8C27143/CY8C27243
CY8C27443/CY8C27543
CY8C27643
Table 23. 3.3-V DC Analog Reference Specifications
Reference
ARF_CR
[5:3]
Reference Power
Settings
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
0b000
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
0b001
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
Symbol Reference
VREFHI
Ref High
VAGND
AGND
VREFLO
Description
Min
Typ
Max
Unit
VDD/2 + Bandgap
VDD/2 + 1.225
VDD/2 + 1.292 VDD/2 + 1.361
V
VDD/2
VDD/2 – 0.067
VDD/2 – 0.002 VDD/2 + 0.063
V
Ref Low
VDD/2 – Bandgap
VDD/2 – 1.35
VDD/2 – 1.293 VDD/2 – 1.210
V
VREFHI
Ref High
VDD/2 + Bandgap
VDD/2 + 1.218
VDD/2 + 1.294 VDD/2 + 1.370
V
VAGND
AGND
VDD/2
VDD/2 – 0.038
VDD/2 – 0.001 VDD/2 + 0.035
V
VREFLO
Ref Low
VDD/2 – Bandgap
VDD/2 – 1.329
VDD/2 – 1.296 VDD/2 – 1.259
V
VREFHI
Ref High
VDD/2 + Bandgap
VDD/2 + 1.221
VDD/2 + 1.294 VDD/2 + 1.366
V
VAGND
AGND
VDD/2
VDD/2 – 0.050
VDD/2 – 0.002 VDD/2 + 0.046
V
VREFLO
Ref Low
VDD/2 – Bandgap
VDD/2 – 1.331
VDD/2 – 1.296 VDD/2 – 1.260
V
VREFHI
Ref High
VDD/2 + Bandgap
VDD/2 + 1.226
VDD/2 + 1.295 VDD/2 + 1.365
V
VAGND
AGND
VDD/2
VDD/2 – 0.028
VDD/2 – 0.001 VDD/2 + 0.025
V
VREFLO
Ref Low
VDD/2 – Bandgap
VDD/2 – 1.329
VDD/2 – 1.297 VDD/2 – 1.262
V
VREFHI
Ref High
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] + P2[6] –
0.098
P2[4] + P2[6]
– 0.018
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] – P2[6] –
0.055
P2[4] – P2[6]
+ 0.013
P2[4] – P2[6]
+ 0.086
V
VREFHI
Ref High
P2[4] + P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] + P2[6] –
0.082
P2[4] + P2[6]
– 0.011
P2[4] + P2[6]
+ 0.050
V
P2[4]
P2[4]
P2[4]
–
P2[4]
P2[4] + P2[6]
+ 0.055
VAGND
AGND
VREFLO
Ref Low
P2[4] – P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] – P2[6] –
0.037
P2[4] – P2[6]
+ 0.006
P2[4] – P2[6]
+ 0.054
V
VREFHI
Ref High
P2[4] + P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] + P2[6] –
0.079
P2[4] + P2[6]
– 0.012
P2[4] + P2[6]
+ 0.047
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] – P2[6] –
0.038
P2[4] – P2[6]
+ 0.006
P2[4] – P2[6]
+ 0.057
V
VREFHI
Ref High
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] + P2[6] –
0.080
P2[4] + P2[6]
– 0.008
P2[4] + P2[6]
+ 0.055
V
P2[4]
P2[4]
P2[4]
–
P2[4] – P2[6] –
0.032
P2[4] – P2[6]
+ 0.003
P2[4] – P2[6]
+ 0.042
V
VAGND
AGND
VREFLO
Ref Low
Document Number: 38-12012 Rev. AD
P2[4]
P2[4]
P2[4]
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
Page 30 of 69
CY8C27143/CY8C27243
CY8C27443/CY8C27543
CY8C27643
Table 23. 3.3-V DC Analog Reference Specifications
Reference
ARF_CR
[5:3]
Reference Power
Settings
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
0b010
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
Symbol Reference
VREFHI
Ref High
VAGND
AGND
Description
VDD
VDD/2
Min
Typ
Max
Unit
VDD – 0.06
VDD – 0.010
VDD
V
VDD/2 – 0.05
VDD/2 – 0.002 VDD/2 + 0.040
V
VREFLO
Ref Low
Vss
Vss
Vss + 0.009
Vss + 0.056
V
VREFHI
Ref High
VDD
VDD – 0.060
VDD – 0.006
VDD
V
VAGND
AGND
VREFLO
Ref Low
Vss
Vss
Vss + 0.005
Vss + 0.034
V
VREFHI
Ref High
VDD
VDD – 0.058
VDD – 0.008
VDD
V
VAGND
AGND
VREFLO
Ref Low
Vss
Vss
Vss + 0.007
Vss + 0.046
V
VREFHI
Ref High
VDD
VDD – 0.057
VDD – 0.006
VDD
V
VAGND
AGND
VDD/2
VDD/2 – 0.028
VDD/2
VDD/2 – 0.037
VDD/2
VDD/2 – 0.025
VDD/2 – 0.001 VDD/2 + 0.025
VDD/2 – 0.002 VDD/2 + 0.033
VDD/2 – 0.001 VDD/2 + 0.022
V
V
V
VREFLO
Ref Low
0b011
All power settings.
Not allowed for 3.3 V
–
–
–
Vss
–
Vss + 0.004
–
Vss + 0.030
–
V
–
0b100
All power settings.
Not allowed for 3.3 V
–
–
–
–
–
–
–
VREFHI
Ref High
P2[4] + 1.213
P2[4] + 1.291
P2[4] + 1.367
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
V
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.333
P2[4] – 1.294
P2[4] – 1.208
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.217
P2[4] + 1.294
P2[4] + 1.368
V
P2[4]
P2[4]
P2[4]
V
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
0b101
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
Vss
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4]
VAGND
AGND
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.320
P2[4] – 1.296
P2[4] – 1.261
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.217
P2[4] + 1.294
P2[4] + 1.369
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
V
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.322
P2[4] – 1.297
P2[4] – 1.262
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.219
P2[4] + 1.295
P2[4] + 1.37
V
P2[4]
P2[4]
P2[4]
V
P2[4] – 1.324
P2[4] – 1.297
P2[4] – 1.262
V
VAGND
AGND
VREFLO
Ref Low
Document Number: 38-12012 Rev. AD
P2[4]
P2[4]
P2[4]
P2[4] – Bandgap
(P2[4] = VDD/2)
Page 31 of 69
CY8C27143/CY8C27243
CY8C27443/CY8C27543
CY8C27643
Table 23. 3.3-V DC Analog Reference Specifications
Reference
ARF_CR
[5:3]
Reference Power
Settings
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
0b110
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
0b111
All power settings.
Not allowed for 3.3 V
Symbol Reference
Description
Min
Typ
Max
Unit
2 × Bandgap
2.507
2.598
2.698
V
Bandgap
1.203
1.307
1.424
V
Vss
Vss + 0.012
Vss + 0.067
V
VREFHI
Ref High
VAGND
AGND
VREFLO
Ref Low
Vss
VREFHI
Ref High
2 × Bandgap
2.516
2.598
2.683
V
VAGND
AGND
Bandgap
1.241
1.303
1.376
V
Vss
Vss + 0.007
Vss + 0.040
V
VREFLO
Ref Low
Vss
VREFHI
Ref High
2 × Bandgap
2.510
2.599
2.693
V
VAGND
AGND
Bandgap
1.240
1.305
1.374
V
VREFLO
Ref Low
Vss
Vss
Vss + 0.008
Vss + 0.048
V
VREFHI
Ref High
2 × Bandgap
2.515
2.598
2.683
V
VAGND
AGND
Bandgap
1.258
1.302
1.355
V
VREFLO
Ref Low
–
–
Vss
–
Vss + 0.005
–
Vss + 0.03
–
V
–
Vss
–
DC Analog PSoC Block Specifications
Table 24 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and
are for design guidance only.
Table 24. DC Analog PSoC Block Specifications
Symbol
RCT
CSC
Description
Resistor unit value (continuous time)
Capacitor unit value (switch cap)
Document Number: 38-12012 Rev. AD
Min
–
–
Typ
12.2
80
Max
–
–
Unit
k
fF
Page 32 of 69
CY8C27143/CY8C27243
CY8C27443/CY8C27543
CY8C27643
DC POR and LVD Specifications
Table 25 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and
are for design guidance only.
Note The bits PORLEV and VM in the following table refer to bits in the VLT_CR register. See the PSoC Programmable
System-on-Chip Technical Reference Manual for more information on the VLT_CR register.
Table 25. DC POR and LVD Specifications
Symbol
Description
Min
Typ
Max
Unit
VPPOR0R
VPPOR1R
VPPOR2R
VDD value for PPOR trip (positive ramp)
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
–
–
–
2.91
4.39
4.55
–
–
–
V
V
V
VPPOR0
VPPOR1
VPPOR2
VDD value for PPOR trip (negative ramp)
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
–
–
–
2.82
4.39
4.55
–
–
–
V
V
V
VPH0
VPH1
VPH2
PPOR hysteresis
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
–
–
–
92
0
0
–
–
–
mV
mV
mV
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
VDD value for LVD trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.86
2.96
3.07
3.92
4.39
4.55
4.63
4.72
2.92
3.02
3.13
4.00
4.48
4.64
4.73
4.81
2.98[17]
3.08
3.20
4.08
4.57
4.74[18]
4.82
4.91
V
V
V
V
V
V
V
V
VPUMP0
VPUMP1
VPUMP2
VPUMP3
VPUMP4
VPUMP5
VPUMP6
VPUMP7
VDD value for PUMP trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.96
3.03
3.18
4.11
4.55
4.63
4.72
4.90
3.02
3.10
3.25
4.19
4.64
4.73
4.82
5.00
3.08
3.16
3.32
4.28
4.74
4.82
4.91
5.10
V
V
V
V
V
V
V
V
Notes
VDD must be greater than or equal to
2.5 V during startup, reset from the
XRES pin, or reset from watchdog.
Notes
17. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.
18. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.
Document Number: 38-12012 Rev. AD
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DC Programming Specifications
Table 26 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and
are for design guidance only.
Table 26. DC Programming Specifications
Symbol
VDDP
Description
VDD for programming and erase
Min
4.5
Typ
5
Max
5.5
Unit
V
VDDLV
Low VDD for verify
3
3.1
3.2
V
VDDHV
High VDD for verify
5.1
5.2
5.3
V
VDDIWRITE
Supply voltage for flash write operation
5.25
V
IDDP
VILP
VIHP
IILP
VOLV
VOHV
FlashENPB
Supply current during programming or verify
Input low voltage during programming or verify
Input high voltage during programming or verify
Input current when applying VILP to P1[0] or P1[1]
during programming or verify
Input current when applying VIHP to P1[0] or P1[1]
during programming or verify
Output low voltage during programming or verify
Output high voltage during programming or verify
Flash endurance (per block)
FlashENT
FlashDR
Flash endurance (total)[20]
Flash data retention
IIHP
3
–
–
2.2
–
5
–
–
–
25
0.8
–
0.2
mA
V
V
mA
–
–
1.5
mA
–
VDD – 1.0
50,000[19]
–
–
–
Vss + 0.75
VDD
–
V
V
Cycles
1,800,000
10
–
–
–
–
Cycles
Years
Notes
This specification applies
to the functional
requirements of external
programmer tools.
This specification applies
to the functional
requirements of external
programmer tools.
This specification applies
to the functional
requirements of external
programmer tools.
This specification applies
to this device when it is
executing internal flash
writes.
Driving internal pull-down
resistor.
Driving internal pull-down
resistor.
Erase/write cycles per
block.
Erase/write cycles.
DC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 27. DC I2C Specifications
Parameter
VILI2C[21]
VIHI2C
[21]
Description
Input low level
Input high level
Min
Typ
Max
Units
–
–
0.3 × VDD
V
3.0 V VDD 3.6 V
Notes
–
–
0.25 × VDD
V
4.75 V VDD 5.25 V
0.7 × VDD
–
–
V
3.0 V VDD 5.25 V
Notes
19. The 50,000 cycle flash endurance per block is only guaranteed if the flash is operating within one voltage range. Voltage ranges are 3.0 V to 3.6 V and 4.75 V to 5.25 V.
20. A maximum of 36 × 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36 × 2
blocks of 25,000 maximum cycles each, or 36 × 4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36 × 50,000 and that no single block
ever sees more than 50,000 cycles).
For the full industrial range, you must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.
Refer to the Flash APIs application note Design Aids – Reading and Writing PSoC® Flash – AN2015 for more information.
21. All GPIOs meet the DC GPIO VIL and VIH specifications found in the DC GPIO specifications sections.The I2C GPIO pins also meet the above specs.
Document Number: 38-12012 Rev. AD
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AC Electrical Characteristics
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 28. AC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
Unit
23.4
24
24.6[22]
Notes
MHz
Trimmed. Utilizing factory trim
values.
FIMO
Internal main oscillator (IMO) frequency
FCPU1
CPU frequency (5 V nominal)
0.0914
24
24.6[22]
MHz
Trimmed. Utilizing factory trim
values. SLIMO mode = 0.
FCPU2
CPU frequency (3.3 V nominal)
0.0914
12
12.3[23]
MHz
Trimmed. Utilizing factory trim
values. SLIMO mode = 0.
F48M
Digital PSoC block frequency
0
48
49.2[22, 24]
MHz
Refer to AC Digital Block
Specifications on page 40.
F24M
Digital PSoC block frequency
0
24
24.6[24]
MHz
F32K1
Internal low speed oscillator (ILO)
frequency
15
32
64
kHz
F32K2
External crystal oscillator
–
32.768
–
kHz
Accuracy is capacitor and crystal
dependent. 50% duty cycle.
F32K_U
ILO untrimmed frequency
5
–
100
kHz
After a reset and before the m8c
starts to run, the ILO is not
trimmed. See the System Resets
section of the PSoC Technical
Reference Manual for details on
timing this
FPLL
PLL frequency
–
23.986
–
MHz
Multiple (x732) of crystal
frequency.
tPLLSLEW
PLL lock time
0.5
–
10
ms
tPLLSLEWSLOW
PLL lock time for low gain setting
0.5
–
50
ms
tOS
External crystal oscillator startup to 1%
–
1700
2620
ms
tOSACC
External crystal oscillator startup to
100 ppm
–
2800
3800
ms
tXRST
External reset pulse width
10
–
–
µs
DC24M
24 MHz duty cycle
40
50
60
%
DCILO
ILO duty cycle
20
50
80
%
Step24M
24 MHz trim step size
–
50
–
kHz
tPOWERUP
Time from end of POR to CPU executing
code
–
16
100
ms
Fout48M
48 MHz output frequency
46.8
48.0
49.2[22, 23]
MHz
FMAX
Maximum frequency of signal on row input
or row output.
–
–
12.3
MHz
SRPOWER_UP
Power supply slew rate
–
–
250
V/ms
The crystal oscillator frequency
is within 100 ppm of its final value
by the end of the Tosacc period.
Correct operation assumes a
properly loaded 1 µW maximum
drive level 32.768 kHz crystal.
3.0 V VDD 5.5 V,
–40 °C TA 85 °C.
wer-up from 0 V. See the System
Resets section of the PSoC
Technical Reference Manual.
Trimmed. Utilizing factory trim
values.
VDD slew rate during power-up.
Notes
22. 4.75 V < VDD < 5.25 V.
23. 3.0 V < VDD < 3.6 V. See application note Adjusting PSoC® Trims for 3.3 V and 2.7 V Operation – AN2012 for information on trimming for operation at 3.3 V.
24. See the individual user module datasheets for information on maximum frequencies for user modules.
Document Number: 38-12012 Rev. AD
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Table 28. AC Chip-Level Specifications (continued)
Symbol
tjit_IMO[25]
tjit_PLL
[25]
Min
Typ
Max
Unit
24 MHz IMO cycle-to-cycle jitter (RMS)
Description
–
200
700
ps
N = 32
Notes
24 MHz IMO long term N cycle-to-cycle
jitter (RMS)
–
300
900
24 MHz IMO period jitter (RMS)
–
100
400
24 MHz IMO cycle-to-cycle jitter (RMS)
–
200
800
ps
N = 32
24 MHz IMO long term N cycle-to-cycle
jitter (RMS)
–
300
1200
24 MHz IMO period jitter (RMS)
–
100
700
Figure 13. PLL Lock Timing Diagram
PLL
Enable
TPLLSLEW
24 MHz
FPLL
PLL
Gain
0
Figure 14. PLL Lock for Low Gain Setting Timing Diagram
PLL
Enable
TPLLSLEWLOW
24 MHz
FPLL
PLL
Gain
1
Figure 15. External Crystal Oscillator Startup Timing Diagram
32K
Select
32 kHz
TOS
F32K2
Note
25. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information.
Document Number: 38-12012 Rev. AD
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AC GPIO Specifications
Table 29 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and
are for design guidance only.
Table 29. AC GPIO Specifications
Symbol
FGPIO
tRiseF
tFallF
tRiseS
tFallS
Description
GPIO operating frequency
Rise time, normal strong mode, Cload = 50 pF
Fall time, normal strong mode, Cload = 50 pF
Rise time, slow strong mode, Cload = 50 pF
Fall time, slow strong mode, Cload = 50 pF
Min
0
3
2
10
10
Typ
–
–
–
27
22
Max
12
18
18
–
–
Unit
MHz
ns
ns
ns
ns
Notes
Normal strong mode
VDD = 4.5 to 5.25 V, 10% to 90%
VDD = 4.5 to 5.25 V, 10% to 90%
VDD = 3 to 5.25 V, 10% to 90%
VDD = 3 to 5.25 V, 10% to 90%
Figure 16. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
TRiseS
TFallF
TFallS
AC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Power = high and Opamp bias = high is not supported at 3.3 V.
Table 30. 5-V AC Operational Amplifier Specifications
Symbol
tROA
tSOA
SRROA
SRFOA
BWOA
ENOA
Description
Rising settling time from 80% of V to 0.1% of V (10 pF load, Unity Gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
Falling settling time from 20% of V to 0.1% of V (10 pF load, Unity Gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
Rising slew rate (20% to 80%)(10 pF load, Unity Gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
Falling slew rate (20% to 80%)(10 pF load, Unity Gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
Gain bandwidth product
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
Noise at 1 kHz (Power = medium, Opamp bias = high)
Document Number: 38-12012 Rev. AD
Min
Typ
Max
Unit
–
–
–
–
–
–
3.9
0.72
0.62
s
s
s
–
–
–
–
–
–
5.9
0.92
0.72
s
s
s
0.15
1.7
6.5
–
–
–
–
–
–
V/s
V/s
V/s
0.01
0.5
4.0
–
–
–
–
–
–
V/s
V/s
V/s
0.75
3.1
5.4
–
–
–
–
100
–
–
–
–
MHz
MHz
MHz
nV/rt-Hz
Page 37 of 69
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Table 31. 3.3-V AC Operational Amplifier Specifications
Symbol
tROA
tSOA
SRROA
SRFOA
BWOA
ENOA
Description
Rising settling time from 80% of V to 0.1% of V (10 pF load, Unity Gain)
Power = low, Opamp bias = low
Power = low, Opamp bias = high
Falling settling time from 20% of V to 0.1% of V (10 pF load, Unity Gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Rising slew rate (20% to 80%)(10 pF load, Unity Gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Falling slew rate (20% to 80%)(10 pF load, Unity Gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Gain bandwidth product
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Noise at 1 kHz (Power = medium, Opamp bias = high)
Min
Typ
Max
Units
–
–
–
–
3.92
0.72
s
s
–
–
–
–
5.41
0.72
s
s
0.31
2.7
–
–
–
–
V/s
V/s
0.24
1.8
–
–
–
–
V/s
V/s
0.67
2.8
–
–
–
100
–
–
–
MHz
MHz
nV/rt-Hz
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1 K resistance and the external capacitor.
Figure 17. Typical AGND Noise with P2[4] Bypass
nV/rtHz
10000
0
0.01
0.1
1.0
10
1000
100
0.001
Document Number: 38-12012 Rev. AD
0.01
0.1 Freq (kHz)
1
10
100
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At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high
frequencies, increased power level reduces the noise spectrum level.
Figure 18. Typical Opamp Noise
nV/rtHz
10000
PH_BH
PH_BL
PM_BL
PL_BL
1000
100
10
0.001
0.01
0.1
1
Freq (kHz)
10
100
AC Low-Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical
parameters apply to 5 V at 25 °C and are for design guidance only.
Table 32. AC Low-Power Comparator Specifications
Symbol
tRLPC
Description
LPC response time
Document Number: 38-12012 Rev. AD
Min
–
Typ
–
Max
50
Unit
s
Notes
50 mV overdrive comparator
reference set within VREFLPC.
Page 39 of 69
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AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 33. AC Digital Block Specifications
Function
All functions
Timer [26, 27]
Description
Min
Typ
Max
Unit
VDD 4.75 V
–
–
49.2
MHz
VDD < 4.75 V
–
–
24.6
MHz
No capture, VDD 4.75 V
–
–
49.2
MHz
No capture, VDD < 4.75 V
–
–
24.6
MHz
With capture
–
–
24.6
MHz
50[28]
–
–
ns
MHz
Block input clock frequency
Input clock frequency
Capture pulse width
Counter
Input clock frequency
No enable input, VDD 4.75 V
–
–
49.2
No enable input, VDD < 4.75 V
–
–
24.6
MHz
With enable input
–
–
24.6
MHz
50[28]
–
–
ns
Enable input pulse width
Dead Band
Notes
Kill pulse width
Asynchronous restart mode
20
–
–
ns
Synchronous restart mode
50[28]
–
–
ns
Disable mode
50[28]
–
–
ns
VDD 4.75 V
–
–
49.2
MHz
VDD < 4.75 V
–
–
24.6
MHz
VDD 4.75 V
–
–
49.2
MHz
VDD < 4.75 V
–
–
24.6
MHz
Input clock frequency
CRCPRS
(PRS Mode)
Input clock frequency
CRCPRS
(CRC Mode)
Input clock frequency
–
–
24.6
MHz
SPIM
Input clock frequency
–
–
8.2
MHz
The SPI serial clock (SCLK) frequency is equal to the
input clock frequency divided by 2.
SPIS [29]
Input clock (SCLK) frequency
–
–
4.1
MHz
The input clock is the SPI SCLK in SPIS mode.
Width of SS_negated between
transmissions
50[28]
–
–
ns
VDD 4.75 V, 2 stop bits
–
–
49.2
MHz
VDD 4.75 V, 1 stop bit
–
–
24.6
MHz
VDD < 4.75 V
–
–
24.6
MHz
Transmitter
Receiver
Input clock frequency
Input clock frequency
The baud rate is equal to the input clock frequency
divided by 8.
The baud rate is equal to the input clock frequency
divided by 8.
VDD 4.75 V, 2 stop bits
–
–
49.2
MHz
VDD 4.75 V, 1 stop bit
–
–
24.6
MHz
VDD < 4.75 V
–
–
24.6
MHz
Notes
26. Errata: When operated between 4.75V to 5.25V, the input capture signal cannot be sourced from Row Output signals or the Broadcast clock signals. This problem
has been fixed in silicon Rev B. For more information, see “Errata” on page 61.
27. Errata: When operated between 3.0V to 4.75V, the input capture signal can only be sourced from Row input signal that has been re-synchronized. This problem has
been fixed in silicon Rev B. For more information, see “Errata” on page 61.
28. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
29. Errata: In PSoC, when one output of one SPI Slave block is connected to the input of other SPI slave block, data is shifted correctly but last bit is read incorrectly. For
the workaround and more information related to this problem, see “Errata” on page 61.
Document Number: 38-12012 Rev. AD
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AC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 34. 5-V AC Analog Output Buffer Specifications
Symbol
tROB
tSOB
SRROB
SRFOB
BWOB
BWOB
Description
Rising settling time to 0.1%, 1 V Step, 100 pF load
Power = low
Power = high
Falling settling time to 0.1%, 1 V Step, 100 pF load
Power = low
Power = high
Rising slew rate (20% to 80%), 1 V Step, 100 pF load
Power = low
Power = high
Falling slew rate (80% to 20%), 1 V Step, 100 pF load
Power = low
Power = high
Small signal bandwidth, 20 mVpp, 3 dB BW, 100 pF load
Power = low
Power = high
Large signal bandwidth, 1 Vpp, 3 dB BW, 100 pF load
Power = low
Power = high
Min
Typ
Max
Unit
–
–
–
–
2.5
2.5
s
s
–
–
–
–
2.2
2.2
s
s
0.65
0.65
–
–
–
–
V/s
V/s
0.65
0.65
–
–
–
–
V/s
V/s
0.8
0.8
–
–
–
–
MHz
MHz
300
300
–
–
–
–
kHz
kHz
Min
Typ
Max
Unit
–
–
–
–
3.8
3.8
s
s
–
–
–
–
2.6
2.6
s
s
0.5
0.5
–
–
–
–
V/s
V/s
0.5
0.5
–
–
–
–
V/s
V/s
0.7
0.7
–
–
–
–
MHz
MHz
200
200
–
–
–
–
kHz
kHz
Table 35. 3.3-V AC Analog Output Buffer Specifications
Symbol
tROB
tSOB
SRROB
SRFOB
BWOB
BWOB
Description
Rising settling time to 0.1%, 1 V Step, 100 pF load
Power = low
Power = high
Falling settling time to 0.1%, 1 V Step, 100 pF load
Power = low
Power = high
Rising slew rate (20% to 80%), 1 V Step, 100 pF load
Power = low
Power = high
Falling slew rate (80% to 20%), 1 V Step, 100 pF load
Power = low
Power = high
Small signal bandwidth, 20m Vpp, 3 dB BW, 100 pF load
Power = low
Power = high
Large signal bandwidth, 1 Vpp, 3 dB BW, 100 pF load
Power = low
Power = high
Document Number: 38-12012 Rev. AD
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AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 36. 5-V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Unit
FOSCEXT
Frequency
0.093
–
24.6
MHz
–
High period
20.6
–
5300
ns
–
Low period
20.6
–
–
ns
–
Power-up IMO to switch
150
–
–
s
Table 37. 3.3-V AC External Clock Specifications
Min
Typ
Max
Unit
FOSCEXT
Symbol
Frequency with CPU clock divide by 1[30]
Description
0.093
–
12.3
MHz
FOSCEXT
Frequency with CPU clock divide by 2 or greater[31]
0.186
–
24.6
MHz
–
High period with CPU clock divide by 1
41.7
–
5300
ns
–
Low period with CPU clock divide by 1
41.7
–
–
ns
–
Power-up IMO to switch
150
–
–
s
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 38. AC Programming Specifications
Symbol
tRSCLK
tFSCLK
tSSCLK
tHSCLK
FSCLK
tERASEB
tWRITE
tDSCLK
tDSCLK3
tERASEALL
Description
Rise time of SCLK
Fall time of SCLK
Data setup time to falling edge of SCLK
Data hold time from falling edge of SCLK
Frequency of SCLK
Flash erase time (Block)
Flash block write time
Data out delay from falling edge of SCLK
Data out delay from falling edge of SCLK
Flash erase time (Bulk)
Min
1
1
40
40
0
–
–
–
–
–
Typ
–
–
–
–
–
30
10
–
–
95
Max
20
20
–
–
8
–
–
45
50
–
Unit
ns
ns
ns
ns
MHz
ms
ms
ns
ns
ms
tPROGRAM_HOT
tPROGRAM_COLD
Flash block erase + flash block write time
Flash block erase + flash block write time
–
–
–
–
80[32]
160[32]
ms
ms
Notes
VDD 3.6
3.0 VDD 3.6
Erase all Blocks and
protection fields at
once
0 °C Tj 100 °C
–40 °C Tj 0 °C
Notes
30. Maximum CPU frequency is 12 MHz at 3.3 V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle
requirements.
31. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the
fifty percent duty cycle requirement is met.
32. For the full industrial range, you must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.
Refer to the Flash APIs application note Design Aids – Reading and Writing PSoC® Flash – AN2015 for more information.
Document Number: 38-12012 Rev. AD
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AC I2C Specifications
Table 39 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40°C
TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for
design guidance only.
Table 39. AC Characteristics of the I2C SDA and SCL Pins
Symbol
FSCLI2C
tHDSTAI2C
tLOWI2C
tHIGHI2C
tSUSTAI2C
tHDDATI2C
tSUDATI2C
tSUSTOI2C
tBUFI2C
tSPI2C
Description
SCL clock frequency
Hold time (repeated) start condition. After this period, the first clock
pulse is generated.
Low period of the SCL clock
High period of the SCL clock
Set up time for a repeated start condition
Data hold time
Data set up time
Set up time for stop condition
Bus-free time between a stop and start condition
Pulse width of spikes are suppressed by the input filter.
Standard Mode
Min
Max
0
100
4.0
–
4.7
4.0
4.7
0
250
4.0
4.7
–
–
–
–
–
–
–
–
–
Fast Mode
Min
Max
0
400
0.6
–
1.3
0.6
0.6
0
100[33]
0.6
1.3
0
–
–
–
–
–
–
–
50
Unit
kHz
s
s
s
s
s
ns
s
s
ns
Figure 19. Definition for Timing for Fast/Standard Mode on the I2C Bus
I2C_SDA
TSUDATI2C
THDSTAI2C
TSPI2C
THDDATI2CTSUSTAI2C
TBUFI2C
I2C_SCL
THIGHI2C TLOWI2C
S
START Condition
TSUSTOI2C
Sr
Repeated START Condition
P
S
STOP Condition
Note
33. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This is automatically the
case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Document Number: 38-12012 Rev. AD
Page 43 of 69
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CY8C27443/CY8C27543
CY8C27643
Packaging Information
This section illustrates the packaging specifications for the CY8C27x43 PSoC device, along with the thermal impedances for each
package and the typical package capacitance on crystal pins.
Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of
the emulation tools' dimensions, refer to the emulator pod drawings at http://www.cypress.com/design/MR10161.
Packaging Dimensions
Figure 20. 8-pin (300-Mil) PDIP
51-85075 *D
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Figure 21. 20-pin (210-Mil) SSOP
51-85077 *F
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Figure 22. 20-pin SOIC (0.513 × 0.300 × 0.0932 Inches) Package Outline, 51-85024
51-85024 *F
Figure 23. 28-pin (300-Mil) Molded DIP
51-85014 *G
Document Number: 38-12012 Rev. AD
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Figure 24. 28-pin (210-Mil) SSOP
51-85079 *F
Figure 25. 28-pin SOIC (0.713 × 0.300 × 0.0932 Inches) Package Outline, 51-85026
51-85026 *H
Document Number: 38-12012 Rev. AD
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Figure 26. 44-pin TQFP (10 × 10 × 1.4 mm) A44S Package Outline, 51-85064
51-85064 *G
Figure 27. 48-pin (300-Mil) SSOP
51-85061 *F
Document Number: 38-12012 Rev. AD
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Figure 28. 48-pin QFN 7 × 7 × 1 mm (Sawn Type)
001-13191 *H
Figure 29. 56-pin (300-Mil) SSOP
51-85062 *F
Important Note For information on the preferred dimensions for mounting QFN packages, see the following application note, Design
Guidelines for Cypress Quad Flat No Extended Lead (QFN) Packaged Devices – AN72845 available at http://www.cypress.com.
Document Number: 38-12012 Rev. AD
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Thermal Impedances
Capacitance on Crystal Pins
Table 40. Thermal Impedances per Package
Package
Typical
Table 41. Typical Package Capacitance on Crystal Pins
JA[34]
Package
Package Capacitance
8-pin PDIP
120 °C/W
8-pin PDIP
2.8 pF
20-pin SSOP
116 °C/W
20-pin SSOP
2.6 pF
20-pin SOIC
79 °C/W
20-pin SOIC
2.5 pF
28-pin PDIP
67 °C/W
28-pin PDIP
3.5 pF
28-pin SSOP
95 °C/W
28-pin SSOP
2.8 pF
28-pin SOIC
68 °C/W
28-pin SOIC
2.7 pF
44-pin TQFP
61 °C/W
44-pin TQFP
2.6 pF
48-pin SSOP
69 °C/W
48-pin SSOP
3.3 pF
48-pin QFN[35]
18 °C/W
48-pin QFN
2.3 pF
56-pin SSOP
47 °C/W
56-pin SSOP
3.3 pF
Solder Reflow Specifications
The following table shows the solder reflow temperature limits that must not be exceeded. Thermap ramp rate should 3 °C or lower.
Table 42. Solder Reflow Specifications
Maximum Peak Temperature (TC)[36]
Maximum Time above TC – 5 °C
8-pin PDIP
260 °C
30 seconds
20-pin SSOP
260 °C
30 seconds
20-pin SOIC
260 °C
30 seconds
28-pin PDIP
260 °C
30 seconds
28-pin SSOP
260 °C
30 seconds
28-pin SOIC
260 °C
30 seconds
44-pin TQFP
260 °C
30 seconds
48-pin SSOP
260 °C
30 seconds
48-pin QFN
260 °C
30 seconds
56-pin SSOP
260 °C
30 seconds
Package
Notes
34. TJ = TA + POWER × JA.
35. To achieve the thermal impedance specified for the QFN package, refer to Design Guidelines for Cypress Quad Flat No Extended Lead (QFN) Packaged Devices –
AN72845 available at http://www.cypress.com.
36. Refer to Table 44 on page 53.
Document Number: 38-12012 Rev. AD
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Development Tool Selection
This chapter presents the development tools available for all
current PSoC device families including the CY8C27x43 family.
Software
PSoC Designer
At the core of the PSoC development software suite is PSoC
Designer, used to generate PSoC firmware applications. PSoC
Designer is available free of charge at http://www.cypress.com
and includes a free C compiler.
PSoC Programmer
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can operate
directly from PSoC Designer or PSoC Express. PSoC
Programmer software is compatible with both PSoC ICE-Cube
In-Circuit Emulator and PSoC MiniProg. PSoC programmer is
available free of charge at http://www.cypress.com.
Development Kits
All development kits can be purchased from the Cypress Online
Store.
CY3215-DK Basic Development Kit
The CY3215-DK is for prototyping and development with PSoC
Designer. This kit supports in-circuit emulation and the software
interface lets you to run, halt, and single step the processor and
view the content of specific memory locations. Advance
emulation features also supported through PSoC Designer. The
kit includes:
■
PSoC Designer Software CD
■
ICE-Cube In-Circuit Emulator
■
ICE Flex-Pod for CY8C29x66 Family
■
Cat-5 Adapter
■
Mini-Eval Programming Board
■
110 ~ 240 V Power Supply, Euro-Plug Adapter
■
iMAGEcraft C Compiler
■
ISSP Cable
■
USB 2.0 Cable and Blue Cat-5 Cable
■
2 CY8C29466-24PXI 28-PDIP Chip Samples
Document Number: 38-12012 Rev. AD
Evaluation Tools
All evaluation tools can be purchased from the Cypress Online
Store.
CY3210-MiniProg1
The CY3210-MiniProg1 kit lets you to program PSoC devices via
the MiniProg1 programming unit. The MiniProg is a small,
compact prototyping programmer that connects to the PC via a
provided USB 2.0 cable. The kit includes:
■
MiniProg Programming Unit
■
MiniEval Socket Programming and Evaluation Board
■
28-pin CY8C29466-24PXI PDIP PSoC Device Sample
■
28-pin CY8C27443-24PXI PDIP PSoC Device Sample
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
CY3210-PSoCEval1
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of
breadboarding space to meet all of your evaluation needs. The
kit includes:
■
Evaluation Board with LCD Module
■
MiniProg Programming Unit
■
28-pin CY8C29466-24PXI PDIP PSoC Device Sample (2)
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
CY3214-PSoCEvalUSB
The CY3214-PSoCEvalUSB evaluation kit features a
development board for the CY8C24794-24LFXI PSoC device.
Special features of the board include both USB and capacitive
sensing development and debugging support. This evaluation
board also includes an LCD module, potentiometer, LEDs, an
enunciator and plenty of breadboarding space to meet all of your
evaluation needs. The kit includes:
■
PSoCEvalUSB Board
■
LCD Module
■
MIniProg Programming Unit
■
Mini USB Cable
■
PSoC Designer and Example Projects CD
■
Getting Started Guide
■
Wire Pack
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Device Programmers
All device programmers can be purchased from the Cypress
Online Store.
CY3216 Modular Programmer
The CY3216 Modular Programmer kit features a modular
programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:
CY3207ISSP In-System Serial Programmer (ISSP)
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production-programming environment.
Note CY3207ISSP needs special software and is not compatible
with PSoC Programmer. The kit includes:
■
CY3207 Programmer Unit
■
Modular Programmer Base
■
PSoC ISSP Software CD
■
3 Programming Module Cards
■
110 ~ 240 V Power Supply, Euro-Plug Adapter
■
MiniProg Programming Unit
■
USB 2.0 Cable
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
Accessories (Emulation and Programming)
Table 43. Emulation and Programming Accessories
Part #
Pin Package
Flex-Pod Kit[37]
Foot Kit[38]
CY8C27143-24PXI
8-pin PDIP
CY3250-27XXX
CY3250-8PDIP-FK
CY8C27243-24PVXI
20-pin SSOP
CY3250-27XXX
CY3250-20SSOP-FK
CY8C27243-24SXI
20-pin SOIC
CY3250-27XXX
CY3250-20SOIC-FK
CY8C27443-24PXI
28-pin PDIP
CY3250-27XXX
CY3250-28PDIP-FK
CY8C27443-24PVXI
28-pin SSOP
CY3250-27XXX
CY3250-28SSOP-FK
CY8C27443-24SXI
28-pin SOIC
CY3250-27XXX
CY3250-28SOIC-FK
CY8C27543-24AXI
44-pin TQFP
CY3250-27XXX
CY3250-44TQFP-FK
CY8C27643-24PVXI
48-pin SSOP
CY3250-27XXX
CY3250-48SSOP-FK
CY8C27643-24LTXI
48-pin QFN
CY3250-27XXXQFN
CY3250-48QFN-FK
Adapter[39]
Adapters can be found at
http://www.emulation.com.
Notes
37. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.
38. Foot kit includes surface mount feet that can be soldered to the target PCB.
39. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found
at http://www.emulation.com.
Document Number: 38-12012 Rev. AD
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CY8C27643
Ordering Information
The following table lists the CY8C27x43 PSoC device’s key package features and ordering codes.
Switch Mode
Pump
Temperature
Range
Digital Blocks
(Rows of 4)
Analog Blocks
(Columns of 3)
Digital I/O
Pins
Analog
Inputs
Analog
Outputs
CY8C27143-24PXI
16 K
256
No
–40 °C to +85 °C
8
12
6
4
4
No
20-pin (210-Mil) SSOP
CY8C27243-24PVXI
16 K
256
Yes
–40 °C to +85 °C
8
12
16
8
4
Yes
20-pin (210-Mil) SSOP
(Tape and Reel)
CY8C27243-24PVXIT
16 K
256
Yes
–40 °C to +85 °C
8
12
16
8
4
Yes
20-pin (300-Mil) SOIC
CY8C27243-24SXI
16 K
256
Yes
–40 °C to +85 °C
8
12
16
8
4
Yes
20-pin (300-Mil) SOIC
(Tape and Reel)
CY8C27243-24SXIT
16 K
256
Yes
–40 °C to +85 °C
8
12
16
8
4
Yes
28-pin (300-Mil) DIP
CY8C27443-24PXI
16 K
256
Yes
–40 °C to +85 °C
8
12
24
12
4
Yes
28-pin (210-Mil) SSOP
CY8C27443-24PVXI
16 K
256
Yes
–40 °C to +85 °C
8
12
24
12
4
Yes
28-pin (210-Mil) SSOP
(Tape and Reel)
CY8C27443-24PVXIT
16 K
256
Yes
–40 °C to +85 °C
8
12
24
12
4
Yes
28-pin (300-Mil) SOIC
CY8C27443-24SXI
16 K
256
Yes
–40 °C to +85 °C
8
12
24
12
4
Yes
28-pin (300-Mil) SOIC
(Tape and Reel)
CY8C27443-24SXIT
16 K
256
Yes
–40 °C to +85 °C
8
12
24
12
4
Yes
44-pin TQFP
CY8C27543-24AXI
16 K
256
Yes
–40 °C to +85 °C
8
12
40
12
4
Yes
44-pin TQFP
(Tape and Reel)
CY8C27543-24AXIT
16 K
256
Yes
–40 °C to +85 °C
8
12
40
12
4
Yes
48-pin (300-Mil) SSOP
CY8C27643-24PVXI
16 K
256
Yes
–40 °C to +85 °C
8
12
44
12
4
Yes
48-pin (300-Mil) SSOP
(Tape and Reel)
CY8C27643-24PVXIT
16 K
256
Yes
–40 °C to +85 °C
8
12
44
12
4
Yes
48-pin (7 × 7 × 1 mm) QFN
(Sawn)
CY8C27643-24LTXI
16 K
256
Yes
–40 °C to +85 °C
8
12
44
12
4
Yes
48-pin (7 × 7 × 1 mm) QFN
(Sawn)
CY8C27643-24LTXIT
16 K
256
Yes
–40 °C to +85 °C
8
12
44
12
4
Yes
56-pin OCD SSOP
CY8C27002-24PVXI[40] 16 K
256
Yes
–40 °C to +85 °C
8
12
44
14
4
Yes
Package
XRES Pin
RAM
(Bytes)
8-pin (300-Mil) DIP
Ordering
Code
Flash
(Bytes)
Table 44. CY8C27x43 PSoC Device Key Features and Ordering Information
Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).
Note
40. This part may be used for in-circuit debugging. It is NOT available for production.
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Ordering Code Definitions
CY 8 C 27 xxx-24xx
Package Type:
PX = PDIP Pb-free
SX = SOIC Pb-free
PVX = SSOP Pb-free
LFX/LKX/LTX /LQX/LCX= QFN Pb-free
AX = TQFP Pb-free
Thermal Rating:
C = Commercial
I = Industrial
E = Extended
Speed: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress
Document Number: 38-12012 Rev. AD
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Acronyms
Table 45 lists the acronyms that are used in this document.
Table 45. Acronyms Used in this Datasheet
Acronym
AC
Description
Acronym
Description
alternating current
MIPS
ADC
analog-to-digital converter
OCD
on-chip debug
API
application programming interface
PCB
printed circuit board
complementary metal oxide semiconductor
PDIP
plastic dual-in-line package
central processing unit
PGA
programmable gain amplifier
CMOS
CPU
CRC
CT
DAC
DC
million instructions per second
cyclic redundancy check
PLL
phase-locked loop
continuous time
POR
power on reset
digital-to-analog converter
PPOR
precision power on reset
direct current
PRS
DTMF
dual-tone multi-frequency
PSoC
Programmable System-on-Chip
ECO
external crystal oscillator
PWM
pulse width modulator
electrically erasable programmable read-only
memory
QFN
quad flat no leads
general purpose I/O
RTC
real time clock
in-circuit emulator
SAR
successive approximation
EEPROM
GPIO
ICE
pseudo-random sequence
IDE
integrated development environment
SC
switched capacitor
ILO
internal low speed oscillator
SMP
switch mode pump
IMO
internal main oscillator
SOIC
small-outline integrated circuit
I/O
input/output
SPI
serial peripheral interface
IrDA
infrared data association
SRAM
static random access memory
ISSP
in-system serial programming
SROM
supervisory read only memory
LCD
liquid crystal display
SSOP
shrink small-outline package
LED
light-emitting diode
TQFP
thin quad flat pack
LPC
low power comparator
UART
universal asynchronous reciever /
transmitter
LVD
low voltage detect
USB
universal serial bus
MAC
multiply-accumulate
WDT
watchdog timer
MCU
microcontroller unit
XRES
external reset
Reference Documents
CY8CPLC20, CY8CLED16P01, CY8C29X66,CY8C27X43, CY8C24X94, CY8C24X23, CY8C24X23A,CY8C22X13, CY8C21X34,
CY8C21X34B, CY8C21X23,CY7C64215, CY7C603XX, CY8CNP1XX, and CYWUSB6953 PSoC(R) Programmable System-on-chip
Technical Reference Manual (TRM) (001-14463)
PSoC® 1 - Reading and Writing Flash – AN2015 (001-40459)
Design Guidelines for Cypress Quad Flat No Extended Lead (QFN) Packaged Devices – AN72845 available at
http://www.cypress.com.
Document Number: 38-12012 Rev. AD
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Document Conventions
Units of Measure
Table 46 lists the unit sof measures.
Table 46. Units of Measure
Symbol
dB
°C
fF
pF
kHz
MHz
rt-Hz
k
µA
mA
nA
pA
µs
Unit of Measure
decibels
degree Celsius
femto farad
picofarad
kilohertz
megahertz
root hertz
kilohm
ohm
microampere
milliampere
nanoampere
pikoampere
microsecond
Symbol
ms
ns
ps
µV
mV
mVpp
nV
V
µW
W
mm
ppm
%
Unit of Measure
millisecond
nanosecond
picosecond
microvolts
millivolts
millivolts peak-to-peak
nanovolts
volts
microwatts
watt
millimeter
parts per million
percent
Numeric Conventions
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’).
Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended
lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are decimal.
Glossary
active high
1. A logic signal having its asserted state as the logic 1 state.
2. A logic signal having the logic 1 state as the higher voltage of the two states.
analog blocks
The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks.
These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more.
analog-to-digital
(ADC)
A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts
a voltage to a digital number. The digital-to-analog (DAC) converter performs the reverse operation.
Application
programming
interface (API)
A series of software routines that comprise an interface between a computer application and lower level services
and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that create
software applications.
asynchronous
A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal.
Bandgap
reference
A stable voltage reference design that matches the positive temperature coefficient of VT with the negative
temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference.
bandwidth
1. The frequency range of a message or information processing system measured in hertz.
2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is
sometimes represented more specifically as, for example, full width at half maximum.
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Glossary (continued)
bias
1. A systematic deviation of a value from a reference value.
2. The amount by which the average of a set of values departs from a reference value.
3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to
operate the device.
block
1. A functional unit that performs a single function, such as an oscillator.
2. A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or
an analog PSoC block.
buffer
1. A storage area for data that is used to compensate for a speed difference, when transferring data from one
device to another. Usually refers to an area reserved for IO operations, into which data is read, or from which
data is written.
2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received
from an external device.
3. An amplifier used to lower the output impedance of a system.
bus
1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing
patterns.
2. A set of signals performing a common function and carrying similar data. Typically represented using vector
notation; for example, address[7:0].
3. One or more conductors that serve as a common connection for a group of related devices.
clock
The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to
synchronize different logic blocks.
comparator
An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy
predetermined amplitude requirements.
compiler
A program that translates a high level language, such as C, into machine language.
configuration
space
In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to ‘1’.
crystal oscillator
An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less
sensitive to ambient temperature than other circuit components.
cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear feedback shift
check (CRC)
register. Similar calculations may be used for a variety of other purposes such as data compression.
data bus
A bi-directional set of signals used by a computer to convey information from a memory location to the central
processing unit and vice versa. More generally, a set of signals used to convey data between digital functions.
debugger
A hardware and software system that allows you to analyze the operation of the system under development. A
debugger usually allows the developer to step through the firmware one step at a time, set break points, and
analyze memory.
dead band
A period of time when neither of two or more signals are in their active state or in transition.
digital blocks
The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator,
pseudo-random number generator, or SPI.
digital-to-analog
(DAC)
A device that changes a digital signal to an analog signal of corresponding magnitude. The analog-to-digital (ADC)
converter performs the reverse operation.
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Glossary (continued)
duty cycle
The relationship of a clock period high time to its low time, expressed as a percent.
emulator
Duplicates (provides an emulation of) the functions of one system with a different system, so that the second
system appears to behave like the first system.
External Reset
(XRES)
An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop
and return to a pre-defined state.
Flash
An electrically programmable and erasable, non-volatile technology that provides you the programmability and
data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is
OFF.
Flash block
The smallest amount of Flash ROM space that may be programmed at one time and the smallest amount of Flash
space that may be protected. A Flash block holds 64 bytes.
frequency
The number of cycles or events per unit of time, for a periodic function.
gain
The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually
expressed in dB.
I2C
A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an Inter-Integrated
Circuit. It is used to connect low-speed peripherals in an embedded system. The original system was created in
the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building
control electronics. I2C uses only two bi-directional pins, clock and data, both running at +5V and pulled high with
resistors. The bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode.
ICE
The in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging
device activity in a software environment (PSoC Designer).
input/output (I/O) A device that introduces data into or extracts data from a system.
interrupt
A suspension of a process, such as the execution of a computer program, caused by an event external to that
process, and performed in such a way that the process can be resumed.
interrupt service
routine (ISR)
A block of code that normal code execution is diverted to when the M8C receives a hardware interrupt. Many
interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends
with the RETI instruction, returning the device to the point in the program where it left normal program execution.
jitter
1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on
serial data streams.
2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between
successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles.
low-voltage detect A circuit that senses VDD and provides an interrupt to the system when VDD falls lower than a selected threshold.
(LVD)
M8C
An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by
interfacing to the Flash, SRAM, and register space.
master device
A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in
width, the master device is the one that controls the timing for data exchanges between the cascaded devices
and an external interface. The controlled device is called the slave device.
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Glossary (continued)
microcontroller
An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a
microcontroller typically includes memory, timing circuits, and IO circuitry. The reason for this is to permit the
realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This
in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for
general-purpose computation as is a microprocessor.
mixed-signal
The reference to a circuit containing both analog and digital techniques and components.
modulator
A device that imposes a signal on a carrier.
noise
1. A disturbance that affects a signal and that may distort the information carried by the signal.
2. The random variations of one or more characteristics of any entity such as voltage, current, or data.
oscillator
A circuit that may be crystal controlled and is used to generate a clock frequency.
parity
A technique for testing transmitting data. Typically, a binary digit is added to the data to make the sum of all the
digits of the binary data either always even (even parity) or always odd (odd parity).
Phase-locked
loop (PLL)
An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference
signal.
pinouts
The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their
physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between
schematic and PCB design (both being computer generated files) and may also involve pin names.
port
A group of pins, usually eight.
Power on reset
(POR)
A circuit that forces the PSoC device to reset when the voltage is lower than a pre-set level. This is a type of
hardware reset.
PSoC®
Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-on-Chip™ is a trademark
of Cypress.
PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology.
pulse width
An output in the form of duty cycle which varies as a function of the applied measurand
modulator (PWM)
RAM
An acronym for random access memory. A data-storage device from which data can be read out and new data
can be written in.
register
A storage device with a specific capacity, such as a bit or byte.
reset
A means of bringing a system back to a know state. See hardware reset and software reset.
ROM
An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot
be written in.
serial
1. Pertaining to a process in which all events occur one after the other.
2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or
channel.
settling time
The time it takes for an output signal or value to stabilize after the input has changed from one value to another.
Document Number: 38-12012 Rev. AD
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Glossary (continued)
shift register
A memory storage device that sequentially shifts a word either left or right to output a stream of serial data.
slave device
A device that allows another device to control the timing for data exchanges between two devices. Or when
devices are cascaded in width, the slave device is the one that allows another device to control the timing of data
exchanges between the cascaded devices and an external interface. The controlling device is called the master
device.
SRAM
An acronym for static random access memory. A memory device where you can store and retrieve data at a high
rate of speed. The term static is used because, after a value is loaded into an SRAM cell, it remains unchanged
until it is explicitly altered or until power is removed from the device.
SROM
An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate
circuitry, and perform Flash operations. The functions of the SROM may be accessed in normal user code,
operating from Flash.
stop bit
A signal following a character or block that prepares the receiving device to receive the next character or block.
synchronous
1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal.
2. A system whose operation is synchronized by a clock signal.
tri-state
A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any
value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit,
allowing another output to drive the same net.
UART
A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits.
user modules
Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower
level Analog and Digital PSoC Blocks. User Modules also provide high level API (Application Programming
Interface) for the peripheral function.
user space
The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal
program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during
the initialization phase of the program.
VDD
A name for a power net meaning "voltage drain." The most positive power supply signal. Usually 5 V or 3.3 V.
VSS
A name for a power net meaning "voltage source." The most negative power supply signal.
watchdog timer
A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time.
Document Number: 38-12012 Rev. AD
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Errata
This section describes the errata for CY8C27143, CY8C27243, CY8C27443, CY8C27543, and CY8C27643 devices. Details include
errata trigger conditions, scope of impact, available workaround, and silicon revision applicability. Contact your local Cypress Sales
Representative if you have questions.
In Production
Part Numbers Affected
Part Number
CY8C27143
CY8C27243
CY8C27443
CY8C27543
CY8C27643
Qualification Status
CY8C27XXX Rev. B – In Production
Errata Summary
The following table defines the errata applicability to available devices.
Items
Part Number
Silicon Revision
Fix Status
1. Reading from chained SPI slaves does not All parts affected
give correct results.
B
No silicon fix planned.
Workaround is required.
2. Internal Main Oscillator (IMO) Tolerance
Deviation at Temperature Extremes.
B
No silicon fix planned.
Workaround is required.
All devices
1. Reading from chained SPI slaves does not give correct results.
■
Problem Definition
When multiple Digital Communication Blocks are configured as SPI Slave devices and one SPI’s output (MISO) is connected to
the input (MOSI) of the second SPI, the serial data will be correctly forwarded, but reading the results from the DCBxxDR2 register
in the second device will result in the last bit shifted in being incorrect.
■
Parameters Affected
NA
■
Trigger Condition
Connection of the output of one PSoC SPI slave to the input of another PSoC SPI slave.
■
Scope of Impact
PSoC end user designs incorporating SPI configurations with multiple Digital Communication Blocks configured as SPI Slave
devices with one SPI output (MISO) connected to the input (MOSI) of the second SPI.
■
Workaround
This solution requires the use of an additional digital block configured as a PWM8 set for a 50% duty cycle. The same clock is
routed to the PWM8, as goes to the two SPI slaves. The PWM8 User Module is parameterized to have a Period of 15 (so that it
divides by 16) and a pulse width of 8 (with CompType set to “Less Than Or Equal” (so that it has a “1” pulse width of 8 clocks and
a “0” pulse width of 8 clocks). The output of the PWM8 is connected to the Slave Select (/SS) of each SPI slave. One of these
connections is direct. The other connection is inverted using the row output LUT. This configuration will “ping pong” the two SPIs
so that each one receives alternating bytes. This solution works especially well in cases where the two SPI slaves are being used
to implement a 16-bit shift register, the following method has worked.
■
Fix Status
There are no fixes planned. The workaround listed above should be used.
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2. Internal Main Oscillator (IMO) Tolerance Deviation at Temperature Extremes.
■
Problem Definition
Asynchronous Digital Communications Interfaces may fail framing beyond 0 to 70 °C. This problem does not affect end-product
usage between 0 and 70 °C.
■
Parameters Affected
The IMO frequency tolerance. The worst case deviation when operated below 0°C and above +70°C and within the upper and
lower datasheet temperature range is ±5%.
■
Trigger Condition(s)
The asynchronous Rx/Tx clock source IMO frequency tolerance may deviate beyond the data sheet limit of ± 2.5% when operated
beyond the temperature range of 0 to +70 °C.
■
Scope of Impact
This problem may affect UART, IrDA, and FSK implementations.
■
Workaround
Implement a quartz crystal stabilized clock source on at least one end of the asynchronous digital communications interface.
■
Fix Status
There are no fixes planned. The workaround listed above should be used.
Document Number: 38-12012 Rev. AD
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Not in Production
Part Numbers Affected
Part Number
CY8C27143
CY8C27243
CY8C27443
CY8C27543
CY8C27643
Qualification Status
CY8C27X43 Rev. A – Not in production
Errata Summary
The following table defines the errata applicability to available devices.
Items
Part Number
Silicon Revision
Fix Status
1. The Timer Capture Input signal is limited to
re-synchronized Row Inputs or Analog
Comparator bus inputs when operating over
4.75 V.
All parts affected
A
Fix confirmed in Silicon Rev B
2. The Timer Capture Inputs are limited to
re-synchronized Row Inputs when operating
at less than 4.75 V.
All parts affected
A
Fix confirmed in Silicon Rev B
3. The I2C_CFG, I2C_SCR, and I2C_MSCR
registers have some restrictions as to the
CPU frequency that must be in effect when
these registers are written.
All parts affected
A
Fix confirmed in Silicon Rev B
1. The Timer Capture Input signal is limited to re-synchronized Row Inputs or Analog Comparator bus inputs when operating
over 4.75 V.
■
Problem Definition
When the device is operating at 4.75 V to 5.25 V, the Input Capture signal source for a digital block operating in Timer mode is
limited to either a Row Input signal that has been re-synchronized, or an Analog Comparator bus input. The Row Output signals,
or the Broadcast clock signals, cannot be used as a source for the Timer Capture signal.
■
Parameters Affected
NA
■
Trigger Condition(S)
Device operating with VCC between 4.75 V to 5.25 V.
■
Scope of Impact
Digital blocks operating in timer mode and user modules relying on the timer's output are affected by this errata element.
■
Workaround
To connect the Input Capture signal to the output of another block in the same row, run the output of that block to a Row Output,
then to a Global Output, then back to a Global Input, then a Row Input, where the signal can be resynchronized. When connecting
the Input Capture signal to an output of a block in a different row, the connection will naturally follow the path of Global Output, to
Global Input, then to Row Input.
■
Fix Status
Fix in silicon rev B
Document Number: 38-12012 Rev. AD
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2. The Timer Capture Inputs are limited to re-synchronized Row Inputs when operating at less than 4.75 V.
■
Problem Definition
When the device is operating at 3.0 V to 4.75 V, the Input Capture signal source for a digital block operating in Timer mode is limited
to a Row Input signal that has been re-synchronized. Maximum width is 16-bits Timer Capture less than 4.75 V. The Row Output
signals, Analog Comparator input signals, or the Broadcast Clock signals cannot be used as a source for the Timer Capture signal.
■
Parameters Affected
NA
■
Trigger Condition(S)
Device operating with VCC between 3.0 V to 4.75 V.
■
Scope of Impact
Digital blocks operating in timer mode and user modules relying on the timer's output are affected by this errata element.
■
Workaround
To connect the input capture signal to the output of another block, run the output of that block to a row output, then to a global
output, back to a global input, then a row input, where the signal can be re-synchronized.
To connect an analog comparator bus signal to an input capture, this signal must be routed to pass through a re-synchronizer. The
only way this can be accomplished is to route the analog comparator on an analog output bus to connect with an I/O pin. This will
use up the resource of the analog output bus, and even though this bus is designed for analog signals, the digital signal from the
Analog Comparator operates correctly when transmitted on this bus. After the signal reaches the pin, it is converted back to a digital
signal and is communicated back to the digital array using the global input bus for that pin. To make this connection, the port pin
must be setup with the global input bus enabled. To enable this configuration within PSoC Designer™, first turn ON the analog
output, and then enable the global input.
Figure 30. Resynchronized
■
Fix Status
Fix in silicon rev B
3. The I2C_CFG, I2C_SCR, and I2C_MSCR registers have some restrictions as to the CPU frequency that must be in effect
when these registers are written.
■
Problem Definition
The CPU frequency must be set to one of the recommended values just prior to a write to these registers and can be immediately
set back to the original operating frequency in the instruction just following the register write. A write instruction to these registers
occurring at a CPU frequency that is not recommended could result in unpredictable behavior. The table below lists the possible
selections of the CPU memory for writes to the I2C_CFG, I2C_SCR, and I2C_MSCR registers, and it highlights the particular
settings that are recommended (Rec) and not recommended (NR).
Document Number: 38-12012 Rev. AD
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I2C_SCR Write and
I2C_MSCR Write
I2C_CFG Write
24 MHz
12 MHz
6 MHz
3 MHz
1.5 MHz
375 K
180 K
93 K
24 MHz
NR
NR
NR
NR
NR
NR
NR
NR
12 MHz
NR
NR
Rec
Rec
Rec
Rec
NR
NR
6 MHz
NR
Rec
Rec
NR
NR
Rec
NR
NR
3 MHz
NR
Rec
NR
Rec
Rec
Rec
Rec
Rec
1.5 MHz
NR
Rec
NR
Rec
Rec
Rec
Rec
Rec
375 K
NR
Rec
NR
Rec
Rec
Rec
Rec
Rec
180 K
NR
Rec
NR
Rec
Rec
Rec
Rec
Rec
93 K
NR
Rec
NR
Rec
Rec
Rec
Rec
Rec
■
Parameters Affected
NA
■
Trigger Condition(S)
See the mentioned table for CPU settings which trigger false writes.
■
Scope of Impact
I2C operation is affected by this Errata element.
■
Workaround
The I2CHW User Module is designed to implement the recommended combination of register write frequencies. This user module
has a parameter that must be set by users of CY8C27x43 Silicon Revision A devices. When this parameter is set, the user module
code temporarily changes the CPU frequency to the recommended values when writing to the affected registers. Users of PSoC
Designer should download and install the PSoC Designer 4.1 Service Pack 1 which is available on the web at
http://www.cypress.com/psoc.
■
Fix Status
Fix in silicon rev B.
Document Number: 38-12012 Rev. AD
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Document History Page
Document Title: CY8C27143/CY8C27243/CY8C27443/CY8C27543/CY8C27643, PSoC® Programmable System-on-Chip™
Document Number: 38-12012
Revision
ECN
Origin of
Change
Submission
Date
Description of Change
**
127087
New Silicon.
7/01/2003
New document (Revision **).
*A
128780
Engineering
and NWJ
7/29/2003
New electrical spec additions, fix of Core Architecture links, corrections to
some text, tables, drawings, and format.
*B
128992
NWJ
8/14/2003
Interrupt controller table fixed, refinements to Electrical Spec section and
Register chapter.
*C
129283
NWJ
8/28/2003
Significant changes to the Electrical Specifications section.
*D
129442
NWJ
9/09/2003
Changes made to Electrical Spec section. Added 20/28-Lead SOIC packages
and pinouts.
*E
130129
NWJ
10/13/2003
Revised document for Silicon Revision A.
*F
130651
NWJ
10/28/2003
Refinements to Electrical Specification section and I2C chapter.
*G
131298
NWJ
11/18/2003
Revisions to GDI, RDI, and Digital Block chapters. Revisions to AC Digital
Block Spec and miscellaneous register changes.
*H
229416
SFV
See ECN
New data sheet format and organization. Reference the PSoC Programmable
System-on-Chip Technical Reference Manual for additional information. Title
change.
*I
247529
SFV
See ECN
Added Silicon B information to this data sheet.
*J
355555
HMT
See ECN
Add DS standards, update device table, swap 48-pin SSOP 45 and 46, add
Reflow Peak Temp. table. Add new color and logo. Re-add pinout ISSP
notation. Add URL to preferred dimensions for mounting MLF packages.
Update Transmitter and Receiver AC Digital Block Electrical Specifications.
*K
523233
HMT
See ECN
Add Low Power Comparator (LPC) AC/DC electrical spec. tables. Add new
Dev. Tool section. Add CY8C20x34 to PSoC Device Characteristics table.
Add OCD pinout and package diagram. Add ISSP note to pinout tables.
Update package diagram revisions. Update typical and recommended
Storage Temperature per industrial specs. Update CY branding and QFN
convention. Update copyright and trademarks.
*L
2545030
YARA
07/29/2008
Added note to DC Analog Reference Specification table and Ordering
Information.
*M
2696188
DPT / PYRS
04/22/2009
Changed title from “CY8C27143, CY8C27243, CY8C27443, CY8C27543,
and CY8C27643 PSoC Mixed Signal Array Final data sheet” to “CY8C27143,
CY8C27243, CY8C27443, CY8C27543, CY8C27643 PSoC® Programmable
System-on-Chip™”. Updated data sheet template.
Added 48-Pin QFN (Sawn) package outline diagram and Ordering information details for CY8C27643-24LTXI and CY8C27643-24LTXIT parts
*N
2762501
MAXK
09/11/2009
Updated DC GPIO, AC Chip-Level, and AC Programming Specifications as
follows:
Modified TWRITE specification.
Replaced TRAMP (time) specification with SRPOWER_UP (slew rate)
specification.
Added note [9] to Flash Endurance specification.
Added IOH, IOL, DCILO, F32K_U, TPOWERUP, TERASEALL, TPROGRAM_HOT,
and TPROGRAM_COLD specifications.
*O
2811860
ECU
11/20/2009
Added Contents page. In the Ordering Information table, added 48 Sawn QFN
(LTXI) to the Silicon B parts. Updated 28-Pin package drawing (51-85014)
Document Number: 38-12012 Rev. AD
Page 66 of 69
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Document History Page (continued)
Document Title: CY8C27143/CY8C27243/CY8C27443/CY8C27543/CY8C27643, PSoC® Programmable System-on-Chip™
Document Number: 38-12012
Revision
ECN
Origin of
Change
Submission
Date
Description of Change
*P
2899847
NJF / HMI
03/26/10
Added CY8C27643-24LKXI and CY8C27643-24LTXI to Emulation and
Programming Accessories on page 52.
Updated Cypress website links.
Added TBAKETEMP and TBAKETIME parameters in Absolute Maximum Ratings
on page 19.
Updated AC electrical specs.
Updated Note in Packaging Information on page 44.
Updated package diagrams.
Updated Thermal Impedances, Solder Reflow Specifications, and Capacitance on Crystal Pins.
Removed Third Party Tools and Build a PSoC Emulator into your Board.
Updated Ordering Code Definitions on page 54.
Updated Ordering Information table.
Updated links in Sales, Solutions, and Legal Information.
*Q
2949177
ECU
06/10/2010
*R
3032514
NJF
09/17/10
Added PSoC Device Characteristics table.
Added DC I2C Specifications table.
Added F32K_U max limit.
Added Tjit_IMO specification, removed existing jitter specifications.
Updated Analog reference tables.
Updated Units of Measure, Acronyms, Glossary, and References sections.
Updated solder reflow specifications.
No specific changes were made to AC Digital Block Specifications table and
I2C Timing Diagram. They were updated for clearer understanding.
Updated Figure 13 since the labelling for y-axis was incorrect.
Template and styles update.
*S
3092470
GDK
11/22/10
Removed the following pruned parts from the data sheet.
CY8C27643-24LFXIT
CY8C27643-24LFXI
*T
3180303
HMI
02/23/2011
Updated Packaging Information.
*U
3378917
GIR
09/28/2011
The text “Pin must be left floating” is included under Description of NC pin in
Table 8 on page 14.
Updated Table 42 on page 50 for improved clarity.
Removed Footnote # 31 and its reference under Table 42 on page 50.
Removed inactive part CY8C27643-24LKXI from Table 43 on page 52.
*V
3525102
UVS
02/14/2012
Updated 48-pin sawn QFN package revision. No technical update.
*W
3598316
LURE /
XZNG
04/24/2012
Changed the PWM description string from “8- to 32-bit” to “8- and 16-bit”.
*X
3959251
GVH
04/09/2013
Updated Packaging Information:
spec 51-85014 – Changed revision from *F to *G.
spec 51-85061 – Changed revision from *E to *F.
spec 001-13191 – Changed revision from *F to *G.
spec 51-85062 – Changed revision from *E to *F.
Added Errata.
*Y
3997627
GVH
05/11/2013
Updated Packaging Information:
spec 51-85026 – Changed revision from *F to *G.
Updated Errata.
Document Number: 38-12012 Rev. AD
Updated content to match current style guide and data sheet template.
No technical updates
Page 67 of 69
CY8C27143/CY8C27243
CY8C27443/CY8C27543
CY8C27643
Document History Page (continued)
Document Title: CY8C27143/CY8C27243/CY8C27443/CY8C27543/CY8C27643, PSoC® Programmable System-on-Chip™
Document Number: 38-12012
Revision
ECN
Origin of
Change
Submission
Date
*Z
4066294
GVH
07/17/2013
Description of Change
Added Errata footnotes (Note 1, 2, 3, 26, 27, 29).
Updated PSoC Functional Overview:
Updated Digital System:
Added Note 1, 2 and referred the same notes in “Timers (8- to 32-bit)”.
Added Note 3 and referred the same note in “SPI slave and master (up to
two)”.
Updated Electrical Specifications:
Updated AC Electrical Characteristics:
Updated AC Digital Block Specifications:
Added Note 26, 27 and referred the same notes in “Timer” parameter.
Added Note 29 and referred the same note in “SPIS” parameter.
Updated to new template.
AA
4416806
ASRI
07/09/2014
Replaced references of “Application Notes for Surface Mount Assembly of
Amkor’s MicroLeadFrame (MLF) Packages” with “Design Guidelines for
Cypress Quad Flat No Extended Lead (QFN) Packaged Devices – AN72845”
in all instances across the document.
Added More Information.
Added PSoC Designer.
Removed “Getting Started”.
Updated Packaging Information:
spec 51-85024 – Changed revision from *E to *F.
spec 51-85026 – Changed revision from *G to *H.
spec 51-85064 – Changed revision from *E to *F.
Updated Reference Documents:
Removed references of spec 001-17397 and spec 001-14503 as these specs
are obsolete.
AB
4507916
ASRI
09/19/2014
Updated Errata.
AC
5974213
VKVK
11/23/2017
Updated Packaging Information:
spec 51-85075 – Changed revision from *C to *D.
spec 51-85077 – Changed revision from *E to *F.
spec 51-85079 – Changed revision from *E to *F.
spec 51-85064 – Changed revision from *F to *G.
spec 001-13191 – Changed revision from *G to *H.
Updated to new template.
AD
6014099
VKVK
01/04/2018
Updated to new template.
Completing Sunset Review.
Document Number: 38-12012 Rev. AD
Page 68 of 69
CY8C27143/CY8C27243
CY8C27443/CY8C27543
CY8C27643
Sales, Solutions, and Legal Information
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closest to you, visit us at Cypress Locations.
PSoC® Solutions
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PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
Cypress Developer Community
Community | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2003-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 38-12012 Rev. AD
Revised January 4, 2018
Page 69 of 69
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