CY8C3446LTI-075

PRELIMINARY PSoC® 3: CY8C34 Family Data Sheet Programmable System-on-Chip (PSoC®) General Description With its unique array of configurable blocks, PSoC® 3 is a true system level solution providing MCU, memory, analog, and digital peripheral functions in a single chip. The CY8C34 family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals. The CY8C34 family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The CY8C34 family is also a high performance configurable digital system with some part numbers including interfaces such as USB, multi-master I2C, and CAN. In addition to communication interfaces, the CY8C34 family has an easy to configure logic array, flexible routing to all I/O pins, and a high performance single cycle 8051 microprocessor core. Designers can easily create system level designs using a rich library of prebuilt components and boolean primitives using PSoC® Creator™, a hierarchical schematic design entry tool. The CY8C34 family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates. Features „ Single cycle 8051 CPU core ‡ ‡ ‡ ‡ ‡ ‡ ‡ DC to 50 MHz operation Multiply and divide instructions Flash program memory, up to 64 KB, 100,000 write cycles, 20 years retention, multiple security features Up to 8 KB flash ECC or configuration storage Up to 8 KB SRAM memory Up to 2 KB EEPROM memory, 1M cycles, 20 years retention 24 channel DMA with multilayer AHB bus access • Programmable chained descriptors and priorities • High bandwidth 32-bit transfer support „ Low voltage, ultra low power ‡ ‡ ‡ ‡ Wide operating voltage range: 0.5V to 5.5V High efficiency boost regulator from 0.5V input to 1.8V-5.0V output 0.8 mA at 3 MHz, 1.2 mA at 6 MHz, 6.6 mA at 50 MHz Low power modes including: • 1 µA sleep mode with real time clock and low voltage detect (LVD) interrupt • 200 nA hibernate mode with RAM retention „ Versatile I/O system 28 to 72 I/O (62 GPIO, 8 SIO, 2 USBIO[1]) ‡ Any GPIO to any digital or analog peripheral routability [1] ‡ LCD direct drive from any GPIO, up to 46x16 segments ® [4] ‡ CapSense support from any GPIO ‡ 1.2V to 5.5V I/O interface voltages, up to 4 domains ‡ Maskable, independent IRQ on any pin or port ‡ Schmitt trigger TTL inputs ‡ All GPIO configurable as open drain high/low, pull up/down, High-Z, or strong output ‡ Configurable GPIO pin state at power on reset (POR) ‡ 25 mA sink on SIO „ Digital peripherals ‡ 16 to 24 programmable PLD based Universal Digital Blocks [1] ‡ Full CAN 2.0b 16 RX, 8 TX buffers [1] ‡ Full-speed (FS) USB 2.0 12 Mbps using internal oscillator ‡ Up to four 16-bit configurable timer, counter, and PWM blocks ‡ Library of standard peripherals ‡ • 8, 16, 24, and 32-bit timers, counters, and PWMs • SPI, UART, I2C • Many others available in catalog ‡ Library of advanced peripherals • Cyclic Redundancy Check (CRC) • Pseudo Random Sequence (PRS) generator • LIN Bus 2.0 • Quadrature decoder „ Analog peripherals (1.71V ≤ Vdda ≤ 5.5V) ‡ 1.024V±0.9% internal voltage reference across -40°C to +85°C (14 ppm/°C) ‡ Configurable Delta-Sigma ADC with 12-bit resolution • Programmable gain stage: x0.25 to x16 • 12-bit mode, 192 ksps, 70 dB SNR, 1 bit INL/DNL ‡ Two 8-bit, 8 Msps IDACs or 1 Msps VDACs ‡ Four comparators with 75 ns response time ‡ Two uncommitted opamps with 25 mA drive capability ‡ Two configurable multifunction analog blocks. Example configurations are PGA, TIA, Mixer, and Sample and Hold ‡ CapSense support „ Programming, debug, and trace JTAG (4 wire), Serial Wire Debug (SWD) (2 wire), and Single Wire Viewer (SWV) interfaces ‡ 8 address and 1 data breakpoint ‡ 4 KB instruction trace buffer 2 ‡ Bootloader programming supportable through I C, SPI, UART, USB, and other interfaces „ Precision, programmable clocking ‡ 3 to 24 MHz internal oscillator over full temperature and voltage range ‡ 4 to 33 MHz crystal oscillator for crystal PPM accuracy ‡ Internal PLL clock generation up to 50 MHz ‡ 32.768 kHz watch crystal oscillator ‡ Low power internal oscillator at 1, 33, and 100 kHz „ Temperature and packaging ‡ -40°C to +85°C degrees industrial temperature ‡ 48-pin SSOP, 48-pin QFN, 68-pin QFN, and 100-pin TQFP package options ‡ Note 1. This feature on select devices only. See Ordering Information on page 92 for details. Cypress Semiconductor Corporation Document Number: 001-53304 Rev. *F • 198 Champion Court • , San Jose CA 95134-1709 • 408-943-2600 Revised June 24, 2010 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data Content Overview 1. ARCHITECTURAL OVERVIEW ......................................... 3 2. PINOUTS ............................................................................. 5 3. PIN DESCRIPTIONS ......................................................... 10 4. CPU ................................................................................... 11 4.1 8051 CPU ................................................................. 11 4.2 Addressing Modes .................................................... 11 4.3 Instruction Set .......................................................... 11 4.4 DMA and PHUB ....................................................... 15 4.5 Interrupt Controller ................................................... 17 5. MEMORY .......................................................................... 18 5.1 Static RAM ............................................................... 18 5.2 Flash Program Memory ............................................ 18 5.3 Flash Security ........................................................... 18 5.4 EEPROM .................................................................. 18 5.5 External Memory Interface ....................................... 18 5.6 Memory Map ............................................................ 19 6. SYSTEM INTEGRATION .................................................. 21 6.1 Clocking System ....................................................... 21 6.2 Power System .......................................................... 25 6.3 Reset ........................................................................ 28 6.4 I/O System and Routing ........................................... 29 7. DIGITAL SUBSYSTEM ..................................................... 35 7.1 Example Peripherals ................................................ 35 7.2 Universal Digital Block .............................................. 39 7.3 UDB Array Description ............................................. 42 7.4 DSI Routing Interface Description ............................ 43 7.5 CAN .......................................................................... 44 7.6 USB .......................................................................... 46 7.7 Timers, Counters, and PWMs .................................. 47 7.8 I2C ............................................................................ 47 8. ANALOG SUBSYSTEM .................................................... 48 8.1 Analog Routing ......................................................... 49 8.2 Delta-Sigma ADC ..................................................... 51 8.3 Comparators ............................................................. 52 8.4 Opamps .................................................................... 53 Document Number: 001-53304 Rev. *F 8.5 Programmable SC/CT Blocks .................................. 53 8.6 LCD Direct Drive ...................................................... 55 8.7 CapSense ................................................................. 56 8.8 Temp Sensor ............................................................ 56 8.9 DAC .......................................................................... 56 8.10 Up/Down Mixer ....................................................... 56 8.11 Sample and Hold .................................................... 57 9. PROGRAMMING, DEBUG INTERFACES, RESOURCES .................................................................... 57 9.1 JTAG Interface ......................................................... 58 9.2 Serial Wire Debug Interface ..................................... 58 9.3 Debug Features ........................................................ 58 9.4 Trace Features ......................................................... 58 9.5 Single Wire Viewer Interface .................................... 58 9.6 Programming Features ............................................. 58 9.7 Device Security ........................................................ 58 10. DEVELOPMENT SUPPORT ........................................... 59 10.1 Documentation ....................................................... 59 10.2 Online ..................................................................... 59 10.3 Tools ....................................................................... 59 11. ELECTRICAL SPECIFICATIONS ................................... 60 11.1 Absolute Maximum Ratings .................................... 60 11.2 Device Level Specifications .................................... 61 11.3 Power Regulators ................................................... 64 11.4 Inputs and Outputs ................................................. 66 11.5 Analog Peripherals ................................................. 70 11.6 Digital Peripherals .................................................. 79 11.7 Memory .................................................................. 82 11.8 PSoC System Resources ....................................... 87 11.9 Clocking .................................................................. 89 12. ORDERING INFORMATION ........................................... 92 12.1 Part Numbering Conventions ................................. 94 13. PACKAGING ................................................................... 95 14. REVISION HISTORY ...................................................... 98 15. SALES, SOLUTIONS, AND LEGAL INFORMATION .. 101 Page 2 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data 1. Architectural Overview Introducing the CY8C34 family of ultra low power, flash Programmable System-on-Chip (PSoC®) devices, part of a scalable 8-bit PSoC 3 and 32-bit PSoC® 5 platform. The CY8C34 family provides configurable blocks of analog, digital, and interconnect circuitry around a CPU subsystem. The combination of a CPU with a very flexible analog subsystem, digital subsystem, routing, and I/O enables a high level of integration in a wide variety of consumer, industrial, and medical applications. Figure 1-1. Simplified Block Diagram Analog Interconnect Quadrature Decoder UDB UDB UDB UDB I2C Slave Sequencer Usage Example for UDB IMO Universal Digital Block Array (24 x UDB) 8- Bit Timer 16- Bit PWM UDB 8- Bit SPI UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB FS USB 2.0 4x Timer Counter PWM 12- Bit SPI UDB Master/ Slave UDB UDB 8- Bit Timer Logic UDB UDB I2C CAN 2.0 16- Bit PRS Logic UDB UDB UART UDB UDB USB PHY D+ D- GPIOs GPIOs Clock Tree 32.768 KHz ( Optional) DIGITAL SYSTEM SYSTEM WIDE RESOURCES Xtal Osc SIO 4- 33 MHz ( Optional) GPIOs Digital Interconnect 12- Bit PWM RTC Timer SYSTEM BUS GPIOs EEPROM EMIF SRAM CPU SYSTEM 8051 or Cortex M3 CPU Interrupt Controller Program Debug & Trace PHUB DMA FLASH ILO Program& Debug GPIOs MEMORY SYSTEM WDT and Wake Boundary Scan Clocking System GPIOs SIOs ANALOG SYSTEM Power Management System LCD Direct Drive ADC POR and LVD 1.8V LDO SMP 3 per Opamp 2 x SC/ CT Blocks (TIA, PGA, Mixer etc) Temperature Sensor 1x Del Sig ADC 2 x DAC + 4x CMP - GPIOs 1.71 to 5.5V Sleep Power + 2x Opamp - CapSense 0. 5 to 5.5V ( Optional) Document Number: 001-53304 Rev. *F Page 3 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data „ Nonvolatile Subsystem All GPIO pins can route analog signals into and out of the device using the internal analog bus. This allows the device to interface up to 62 discrete analog signals. The heart of the analog subsystem is a fast, accurate, configurable Delta-Sigma ADC with these features: „ Programming, Debug, and Test Subsystem „ Less than 100 µV offset „ Inputs and Outputs „ A gain error of 0.2% „ Clocking „ Integral Non Linearity (INL) less than 1 LSB „ Power „ Differential Non Linearity (DNL) less than 1 LSB „ Digital Subsystem „ Signal-to-noise ratio (SNR) better than 70 dB (Delta-Sigma) in Figure 1-1 illustrates the major components of the CY8C34 family. They are: „ 8051 CPU Subsystem „ Analog Subsystem PSoC’s digital subsystem provides half of its unique configurability. It connects a digital signal from any peripheral to any pin through the Digital System Interconnect (DSI). It also provides functional flexibility through an array of small, fast, low power Universal Digital Blocks (UDBs). PSoC Creator provides a library of pre-built and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM, AND, OR, and so on) that are mapped to the UDB array. The designer can also easily create a digital circuit using boolean primitives by means of graphical design entry. Each UDB contains Programmable Array Logic (PAL)/Programmable Logic Device (PLD) functionality, together with a small state machine engine to support a wide variety of peripherals. In addition to the flexibility of the UDB array, PSoC also provides configurable digital blocks targeted at specific functions. For the CY8C34 family these blocks can include four 16-bit timer, counter, and PWM blocks; I2C slave, master, and multi-master; Full-Speed USB; and Full CAN 2.0b. For more details on the peripherals see the “Example Peripherals” section on page 35 of this data sheet. For information on UDBs, DSI, and other digital blocks, see the “Digital Subsystem” section on page 35 of this data sheet. PSoC’s analog subsystem is the second half of its unique configurability. All analog performance is based on a highly accurate absolute voltage reference with less than 0.9% error over temperature and voltage. The configurable analog subsystem includes: „ Analog muxes „ Comparators „ Voltage references „ Analog-to-Digital Converter (ADC) „ Digital-to-Analog Converters (DACs) Document Number: 001-53304 Rev. *F 12-bit mode This converter addresses a wide variety of precision analog applications including some of the most demanding sensors. Two high speed voltage or current DACs support 8-bit output signals at update rate of 8 Msps in current DAC (IDAC) and 1 Msps in voltage DAC (VDAC). They can be routed out of any GPIO pin. You can create higher resolution voltage PWM DAC outputs using the UDB array. This can be used to create a pulse width modulated (PWM) DAC of up to 10 bits, at up to 48 kHz. The digital DACs in each UDB support PWM, PRS, or delta-sigma algorithms with programmable widths. In addition to the ADC and DACs, the analog subsystem provides multiple: „ Uncommitted opamps „ Configurable Switched Capacitor/Continuous Time (SC/CT) blocks. These support: ‡ Transimpedance amplifiers ‡ Programmable gain amplifiers ‡ Mixers ‡ Other similar analog components See the “Analog Subsystem” section on page 48 of this data sheet for more details. PSoC’s 8051 CPU subsystem is built around a single cycle pipelined 8051 8-bit processor running at up to 50 MHz. The CPU subsystem includes a programmable nested vector interrupt controller, DMA controller, and RAM. PSoC’s nested vector interrupt controller provides low latency by allowing the CPU to vector directly to the first address of the interrupt service routine, bypassing the jump instruction required by other architectures. The DMA controller enables peripherals to exchange data without CPU involvement. This allows the CPU to run slower (saving power) or use those CPU cycles to improve the performance of firmware algorithms. The single cycle 8051 CPU runs ten times faster than a standard 8051 processor. The processor speed itself is configurable allowing active power consumption to be tuned for specific applications. Page 4 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data PSoC’s nonvolatile subsystem consists of flash, byte-writeable EEPROM, and nonvolatile configuration options. It provides up to 64 KB of on-chip flash. The CPU can reprogram individual blocks of flash, enabling boot loaders. The designer can enable an Error Correcting Code (ECC) for high reliability applications. A powerful and flexible protection model secures the user's sensitive information, allowing selective memory block locking for read and write protection. Up to 2 KB of byte-writable EEPROM is available on-chip to store application data. Additionally, selected configuration options such as boot speed and pin drive mode are stored in nonvolatile memory. This allows settings to activate immediately after power on reset (POR). The three types of PSoC I/O are extremely flexible. All I/Os have many drive modes that are set at POR. PSoC also provides up to four I/O voltage domains through the Vddio pins. Every GPIO has analog I/O, LCD drive[1], CapSense[4], flexible interrupt generation, slew rate control, and digital I/O capability. The SIOs on PSoC allow Voh to be set independently of Vddio when used as outputs. When SIOs are in input mode they are high impedance. This is true even when the device is not powered or when the pin voltage goes above the supply voltage. This makes the SIO ideally suited for use on an I2C bus where the PSoC may not be powered when other devices on the bus are. The SIO pins also have high current sink capability for applications such as LED drives. The programmable input threshold feature of the SIO can be used to make the SIO function as a general purpose analog comparator. For devices with Full-Speed USB the USB physical interface is also provided (USBIO). When not using USB these pins may also be used for limited digital functionality and device programming. All the features of the PSoC I/Os are covered in detail in the “I/O System and Routing” section on page 29 of this data sheet. The PSoC device incorporates flexible internal clock generators, designed for high stability and factory trimmed for high accuracy. The Internal Main Oscillator (IMO) is the master clock base for the system, and has 1% accuracy at 3 MHz. The IMO can be configured to run from 3 MHz up to 24 MHz. Multiple clock derivatives can be generated from the main clock frequency to meet application needs. The device provides a PLL to generate system clock frequencies up to 50 MHz from the IMO, external crystal, or external reference clock. It also contains a separate, very low power Internal Low Speed Oscillator (ILO) for the sleep and watchdog timers. A 32.768 kHz external watch crystal is also supported for use in Real Time Clock (RTC) applications. The clocks, together with programmable clock dividers, provide the flexibility to integrate most timing requirements. The CY8C34 family supports a wide supply operating range from 1.71 to 5.5V. This allows operation from regulated supplies such as 1.8 ± 5%, 2.5V ±10%, 3.3V ± 10%, or 5.0V ± 10%, or directly Document Number: 001-53304 Rev. *F from a wide range of battery types. In addition, it provides an integrated high efficiency synchronous boost converter that can power the device from supply voltages as low as 0.5V. This enables the device to be powered directly from a single battery or solar cell. In addition, the designer can use the boost converter to generate other voltages required by the device, such as a 3.3V supply for LCD glass drive. The boost’s output is available on the Vboost pin, allowing other devices in the application to be powered from the PSoC. PSoC supports a wide range of low power modes. These include a 200 nA hibernate mode with RAM retention and a 1 µA sleep mode with real time clock (RTC). In the second mode the optional 32.768 kHz watch crystal runs continuously and maintains an accurate RTC. Power to all major functional blocks, including the programmable digital and analog peripherals, can be controlled independently by firmware. This allows low power background processing when some peripherals are not in use. This, in turn, provides a total device current of only 1.2 mA when the CPU is running at 6 MHz or 0.8 mA running at 3 MHz. The details of the PSoC power modes are covered in the “Power System” section on page 25 of this data sheet. PSoC uses JTAG (4 wire) or Serial Wire Debug (SWD) (2 wire) interfaces for programming, debug, and test. The 1-wire Single Wire Viewer (SWV) may also be used for “printf” style debugging. By combining SWD and SWV, the designer can implement a full debugging interface with just three pins. Using these standard interfaces enables the designer to debug or program the PSoC with a variety of hardware solutions from Cypress or third party vendors. PSoC supports on-chip break points and 4 KB instruction and data race memory for debug. Details of the programming, test, and debugging interfaces are discussed in the “Programming, Debug Interfaces, Resources” section on page 57 of this data sheet. 2. Pinouts The Vddio pin that supplies a particular set of pins is indicated by the black lines drawn on the pinout diagrams in Figure 2-1 through Figure 2-4. Using the Vddio pins, a single PSoC can support multiple interface voltage levels, eliminating the need for off-chip level shifters. Each Vddio may sink up to 100 mA total to its associated I/O pins and opamps. On the 68 pin and 100 pin devices each set of Vddio associated pins may sink up to 100 mA. The 48 pin device may sink up to 100 mA total for all Vddio0 plus Vddio2 associated I/O pins and 100 mA total for all Vddio1 plus Vddio3 associated I/O pins. Page 5 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data Figure 2-1. 48-Pin SSOP Part Pinout (SIO) P12[2] (SIO) P12[3] (OpAmp2out, GPIO) P0[0] (OpAmp0out, GPIO) P0[1] (OpAmp0+, GPIO) P0[2] (OpAmp0-/Extref0, GPIO) P0[3] Vddio0 (OpAmp2+, GPIO) P0[4] (OpAmp2-, GPIO) P0[5] (IDAC0, GPIO) P0[6] (IDAC2, GPIO) P0[7] Vccd Vssd Vddd (GPIO) P2[3] (GPIO) P2[4] Vddio2 (GPIO) P2[5] (GPIO) P2[6] (GPIO) P2[7] Vssb Ind Vboost Vbat 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Lines show Vddio to IO supply association SSOP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Vdda Vssa Vcca P15[3] (GPIO, kHz XTAL: Xi) P15[2] (GPIO, kHz XTAL: Xo) P12[1] (SIO, I2C1: SDA) P12[0] (SIO, I2C1: SCL) Vddio3 P15[1] (GPIO, MHz XTAL: Xi) P15[0] (GPIO, MHz XTAL: Xo) Vccd Vssd Vddd [2] P15[7] (USBIO, D-, SWDCK) [2] P15[6] (USBIO, D+, SWDIO) P1[7] (GPIO) P1[6] (GPIO) Vddio1 P1[5] (GPIO, nTRST) P1[4] (GPIO, TDI) P1[3] (GPIO, TDO, SWV) P1[2] (GPIO, configurable XRES) P1[1] (GPIO, TCK, SWDCK) P1[0] (GPIO, TMS, SWDIO) (GPIO) P2[6] (GPIO) P2[7] 1 2 Vssb Ind Vb Vbat (GPIO, TMS, SWDIO) P1[0] (GPIO, TCK, SWDCK) P1[1] (GPIO, Configurable XRES) P1[2] (GPIO, TDO, SWV) P1[3] (GPIO, TDI) P1[4] (GPIO, nTRST) P1[5] 3 4 5 6 QFN ( Top View) 36 35 34 33 32 31 30 29 28 27 26 25 P0[3] (OpAmp0-/Extref0, GPIO) P0[2] (OpAmp0+, GPIO) P0[1] (OpAmp0out, GPIO) P0[0] (OpAmp2out, GPIO) P12[3] (SIO) P12[2] (SIO) Vdda Vssa Vcca P15[3] (GPIO, kHz XTAL: Xi) P15[2] (GPIO, kHz XTAL: Xo) P12[1] (SIO, I2C1: SDA) (GPIO) P1[6] (GPIO) P1[7] [2] (USBIO, D+, SWDIO) P15[6] [2] (USBIO, D-, SWDCK) P15[7] Vddd Vssd Vccd (GPIO, MHz XTAL: Xo) P15[0] (GPIO, MHz XTAL: Xi) P15[1] Vddio3 (SIO, I2C1: SCL) P12[0] Vddio1 Document Number: 001-53304 Rev. *F Lines show Vddio to I/O supply association 13 14 15 16 17 18 19 20 21 22 23 24 7 8 9 10 11 12 42 41 40 39 38 37 48 47 46 45 44 43 P2[5] (GPIO) Vddio2 P2[4] (GPIO) P2[3] (GPIO) Vddd Vssd Vccd P0[7] (IDAC2, GPIO) P0[6] (IDAC0, GPIO) P0[5] (OpAmp2-, GPIO) P0[4] (OpAmp2+, GPIO) Vddio0 Figure 2-2. 48-Pin QFN Part Pinout[3] Page 6 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data 55 54 53 52 58 57 56 P15[5] (GPOI) P15[4] (GPIO) Vddd Vssd Vccd P0[7] (GPIO, IDAC2) P0[6] (GPIO, IDAC0) P0[5] (GPIO, OpAmp2-) P0[4] (GPIO, OpAmp2+) Vddio0 51 50 Lines show Vddio to IO supply association QFN 28 29 30 31 32 33 34 (MHz XTAL: Xi, GPIO) P15[1] (GPIO) P3[0] (GPIO) P3[1] (Extref1, GPIO) P3[2] (GPIO) P3[3] (GPIO) P3[4] (GPIO) P3[5] (Top View) 18 19 20 21 22 23 24 25 26 27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 (GPIO) P1[6] (GPIO) P1[7] (SIO) P12[6] (SIO) P12[7] [2] (USBIO, D+, SWDIO) P15[6] [2] (USBIO, D-, SWDCK) P15[7] Vddd Vssd Vccd (MHz XTAL: Xo, GPIO) P15[0] (GPIO) P2[6] (GPIO) P2[7] (I2C0: SCL, SIO) P12[4] (I2C0: SDA, SIO) P12[5] Vssb Ind Vboost Vbat Vssd XRES (TMS, SWDIO, GPIO) P1[0] (TCK, SWDCK, GPIO) P1[1] (configurable XRES, GPIO) P1[2] (TDO, SWV, GPIO) P1[3] (TDI, GPIO) P1[4] (nTRST, GPIO) P1[5] Vddio1 66 65 64 63 62 61 60 59 68 67 P2[5] (GPIO) Vddio2 P2[4] (GPIO) P2[3] (GPIO) P2[2] (GPIO) P2[1] (GPIO) P2[0] (GPIO) Figure 2-3. 68-Pin QFN Part Pinout[3] 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 P0[3] (GPIO, OpAmp0-/Extref0) P0[2] (GPIO, OpAmp0+) P0[1] (GPIO, OpAmp0out) P0[0] (GPIO, OpAmp2out) P12[3] (SIO) P12[2] (SIO) Vssd Vdda Vssa Vcca P15[3] (GPIO, kHz XTAL: Xi) P15[2] (GPIO, kHz XTAL: Xo) P12[1] (SIO, I2C1: SDA) P12[0] (SIO, 12C1: SCL) P3[7] (GPIO) P3[6] (GPIO) Vddio3 Notes 2. Pins are No Connect (NC) on devices without USB. NC means that the pin has no electrical connection. The pin can be left floating or tied to a supply voltage or ground. 3. The center pad on the QFN package should be connected to digital ground (Vssd) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal. Document Number: 001-53304 Rev. *F Page 7 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data 77 76 P4[5] (GPIO) P4[4] (GPIO) P4[3] (GPIO) P4[2] (GPIO) P0[7] (GPIO, IDAC2) P0[6] (GPIO, IDAC0) P0[5] (GPIO, OpAmp2-) P0[4] (GPIO, OpAmp2+) 87 86 85 84 83 82 81 80 79 78 90 89 88 P15[4] (GPIO) P6[3] (GPIO) P6[2] (GPIO) P6[1] (GPIO) P6[0] (GPIO) Vddd Vssd Vccd P4[7] (GPIO) P4[6] (GPIO) 98 97 96 95 94 93 92 91 75 74 Lines show Vddio to IO supply association TQFP 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 Vddio0 P0[3] (GPIO, OpAmp0-/Extref0) P0[2] (GPIO, OpAmp0+) P0[1] (GPIO, OpAmp0out) P0[0] (GPIO, OpAmp2out) P4[1] (GPIO) P4[0] (GPIO) P12[3] (SIO) P12[2] (SIO) Vssd Vdda Vssa Vcca NC NC NC NC NC NC P15[3] (GPIO, kHz XTAL: Xi) P15[2] (GPIO, kHz XTAL: Xo) P12[1] (SIO, I2C1: SDA) P12[0] (SIO, I2C1: SCL) P3[7] (GPIO) P3[6] (GPIO) [2] (GPIO) P3[5] Vddio3 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 (USBIO, D-, SWDCK) P15[7] Vddd Vssd Vccd NC NC (MHz XTAL: Xo, GPIO) P15[0] (MHz XTAL: Xi, GPIO) P15[1] (GPIO) P3[0] (GPIO) P3[1] (Extref1, GPIO) P3[2] (GPIO) P3[3] (GPIO) P3[4] 54 53 52 51 26 27 28 29 30 31 32 33 34 35 (TCK, SWDCK, GPIO) P1[1] (configurable XRES, GPIO) P1[2] (TDO, SWV, GPIO) P1[3] (TDI, GPIO) P1[4] (nTRST, GPIO) P1[5] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Vddio1 (GPIO) P1[6] (GPIO) P1[7] (SIO) P12[6] (SIO) P12[7] (GPIO) P5[4] (GPIO) P5[5] (GPIO) P5[6] (GPIO) P5[7] [2] (USBIO, D+, SWDIO) P15[6] (GPIO) P2[5] (GPIO) P2[6] (GPIO) P2[7] (I2C0: SCL, SIO) P12[4] (I2C0: SDA, SIO) P12[5] (GPIO) P6[4] (GPIO) P6[5] (GPIO) P6[6] (GPIO) P6[7] Vssb Ind Vboost Vbat Vssd XRES (GPIO) P5[0] (GPIO) P5[1] (GPIO) P5[2] (GPIO) P5[3] (TMS, SWDIO, GPIO) P1[0] 100 99 Vddio2 P2[4] (GPIO) P2[3] (GPIO) P2[2] (GPIO) P2[1] (GPIO) P2[0] (GPIO) P15[5] (GPIO) Figure 2-4. 100-Pin TQFP Part Pinout Document Number: 001-53304 Rev. *F Page 8 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data Figure 2-5 and Figure 2-6 show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal analog performance on a 2-layer board. on page 25. The trace between the two Vccd pins should be as short as possible. „ The two pins labeled Vssd must be connected together. „ The two pins labeled Vddd must be connected together. „ The two pins labeled Vccd must be connected together, with capacitance added, as shown in Figure 2-5 and Power System Figure 2-5. Example Schematic for 100-Pin TQFP Part with Power Connections Vddd Vddd C1 1uF Vccd Vssd Vssd 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 C6 0.1uF C2 0.1uF Vddd Vssd Vddd Vddd U2 CY8C55xx Vdda Vddd Vddio0 OA0-, REF0, P0[3] OA0+, P0[2] OA0out, P0[1] OA2out, P0[0] P4[1] P4[0] SIO, P12[3] SIO, P12[2] Vssd Vdda Vssa Vcca NC NC NC NC NC NC kHzXin, P15[3] kHzXout, P15[2] SIO, P12[1] SIO, P12[0] OA3out, P3[7] OA1out, P3[6] Vddio1 P1[6] P1[7] P12[6], SIO P12[7], SIO P5[4] P5[5] P5[6] P5[7] USB D+, P15[6] USB D-, P15[7] Vddd Vssd Vccd NC NC P15[0], MHzXout P15[1], MHzXin P3[0], IDAC1 P3[1], IDAC3 P3[2], OA3-, REF1 P3[3], OA3+ P3[4], OA1P3[5], OA1+ Vddio3 Vssd P2[5] P2[6] P2[7] P12[4], SIO P12[5], SIO P6[4] P6[5] P6[6] P6[7] Vssb Ind Vboost Vbat Vssd XRES P5[0] P5[1] P5[2] P5[3] P1[0], SWIO, TMS P1[1], SWDIO, TCK P1[2] P1[3], SWV, TDO P1[4], TDI P1[5], nTRST Vddd P32 Vccd Vssd Vssd Vddd C12 0.1uF 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 C8 0.1uF C17 1uF Vssd Vssa Vssd Vssd Vdda Vssa Vcca Vdda C9 1uF C10 0.1uF Vssa Vddd 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Vssd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Vddio2 P2[4] P2[3] P2[2] P2[1] P2[0] P15[5] P15[4] P6[3] P6[2] P6[1] P6[0] Vddd Vssd Vccd P4[7] P4[6] P4[5] P4[4] P4[3] P4[2] IDAC2, P0[7] IDAC0, P0[6] OA2-, P0[5] OA2+, P0[4] Vssd C11 0.1uF C13 10uF, 6.3V C14 0.1uF Vssd C15 1uF C16 0.1uF Vssa Vssa Vssd Note The two Vccd pins must be connected together with as short a trace as possible. A trace under the device is recommended, as shown in Figure 2-6. Document Number: 001-53304 Rev. *F Page 9 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data Figure 2-6. Example PCB Layout for 100-Pin TQFP Part for Optimal Analog Performance Vssa Vddd Vssd Vdda Vssa Plane Vssd Plane 3. Pin Descriptions SWDCK. Serial Wire Debug Clock programming and debug port connection. IDAC0, IDAC2. Low resistance output pin for high current DACs (IDAC). SWDIO. Serial Wire Debug Input and Output programming and debug port connection. OpAmp0out, OpAmp2out. High current output of uncommitted opamp[4]. Extref0, Extref1. External reference input to the analog system. OpAmp0-, OpAmp2-. Inverting input to uncommitted opamp. OpAmp0+, OpAmp2+. Noninverting opamp. input to uncommitted GPIO. General purpose I/O pin provides interfaces to the CPU, digital peripherals, analog peripherals, interrupts, LCD segment drive, and CapSense[4]. I2C I2C0: SCL, I2C1: SCL. SCL line providing wake from sleep on an address match. Any I/O pin can be used for I2C SCL if wake from sleep is not required. I2C0: SDA, I2C1: SDA. I2C SDA line providing wake from sleep on an address match. Any I/O pin can be used for I2C SDA if wake from sleep is not required. Ind. Inductor connection to boost pump. kHz XTAL: Xo, kHz XTAL: Xi. 32.768 kHz crystal oscillator pin. MHz XTAL: Xo, MHz XTAL: Xi. 4 to 33 MHz crystal oscillator pin. nTRST. Optional JTAG Test Reset programming and debug port connection to reset the JTAG connection. SIO. Special I/O provides interfaces to the CPU, digital peripherals and interrupts with a programmable high threshold voltage, analog comparator, high sink current, and high impedance state when the device is unpowered. SWV. Single Wire Viewer debug output. TCK. JTAG Test Clock programming and debug port connection. TDI. JTAG Test Data In programming and debug port connection. TDO. JTAG Test Data Out programming and debug port connection. TMS. JTAG Test Mode Select programming and debug port connection. USBIO, D+. Provides D+ connection directly to a USB 2.0 bus. May be used as a digital I/O pin. Pins are No Connect (NC) on devices without USB.[2] USBIO, D-. Provides D- connection directly to a USB 2.0 bus. May be used as a digital I/O pin. Pins are No Connect (NC) on devices without USB.[2] Vboost. Power sense connection to boost pump. Vbat. Battery supply to boost pump. Vcca. Output of analog core regulator and input to analog core. Requires a 1 µF capacitor to Vssa. Regulator output not for external use. Vccd. Output of digital core regulator and input to digital core. The two Vccd pins must be shorted together, with the trace between them as short as possible, and a 1 µF capacitor to Vssd; see Power System on page 25. Regulator output not for external use. Note 4. GPIOs with OpAmp outputs are not recommended for use with CapSense. Document Number: 001-53304 Rev. *F Page 10 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data Vdda. Supply for all analog peripherals and analog core regulator. Vdda must be the highest voltage present on the device. All other supply pins must be less than or equal to Vdda. Vddd. Supply for all digital peripherals and digital core regulator. Vddd must be less than or equal to Vdda. Vssa. Ground for all analog peripherals. Vssb. Ground connection for boost pump. Vssd. Ground for all digital logic and I/O pins. Vddio0, Vddio1, Vddio2, Vddio3. Supply for I/O pins. See pinouts for specific I/O pin to Vddio mapping. Each Vddio must be tied to a valid operating voltage (1.71V to 5.5V), and must be less than or equal to VDDA. If the I/O pins associated with Vddio0, Vddio2 or Vddio3 are not used then that Vddio should be tied to ground (Vssd or Vssa). XRES (and configurable XRES). External reset pin. Active low with internal pullup. In 48-pin SSOP parts, P1[2] is configured as XRES. In all other parts the pin is configured as a GPIO. 4.2 Addressing Modes The following addressing modes are supported by the 8051: „ Direct Addressing: The operand is specified by a direct 8-bit address field. Only the internal RAM and the SFRs can be accessed using this mode. „ Indirect Addressing: The instruction specifies the register which contains the address of the operand. The registers R0 or R1 are used to specify the 8-bit address, while the Data Pointer (DPTR) register is used to specify the 16-bit address. „ Register Addressing: Certain instructions access one of the registers (R0-R7) in the specified register bank. These instructions are more efficient because there is no need for an address field. „ Register Specific Instructions: Some instructions are specific to certain registers. For example, some instructions always act on the accumulator. In this case, there is no need to specify the operand. „ Immediate Constants: Some instructions carry the value of the constants directly instead of an address. 4. CPU 4.1 8051 CPU The CY8C34 devices use a single cycle 8051 CPU, which is fully compatible with the original MCS-51 instruction set. The CY8C34 family uses a pipelined RISC architecture, which executes most instructions in 1 to 2 cycles to provide peak performance of up to 24 MIPS with an average of 2 cycles per instruction. The single cycle 8051 CPU runs ten times faster than a standard 8051 processor. „ Indexed Addressing: This type of addressing can be used only for a read of the program memory. This mode uses the Data Pointer as the base and the accumulator value as an offset to read a program memory. „ Bit Addressing: In this mode, the operand is one of 256 bits. 4.3 Instruction Set The 8051 instruction set is highly optimized for 8-bit handling and Boolean operations. The types of instructions supported include: The 8051 CPU subsystem includes these features: „ Arithmetic instructions „ Single cycle 8051 CPU „ Logical instructions „ Up to 64 kB of flash memory, up to 2 kB of EEPROM, and up „ Data transfer instructions to 8 kB of SRAM „ Programmable nested vector interrupt controller „ Direct Memory Access (DMA) controller „ Peripheral HUB (PHUB) „ External Memory Interface (EMIF) Document Number: 001-53304 Rev. *F „ Boolean instructions „ Program branching instructions 4.3.1 Instruction Set Summary 4.3.1.1 Arithmetic Instructions Arithmetic instructions support the direct, indirect, register, immediate constant, and register specific instructions. Arithmetic modes are used for addition, subtraction, multiplication, division, increment, and decrement operations. lists the different arithmetic instructions. Page 11 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data Table 4-1. Arithmetic Instructions Mnemonic Description Bytes Cycles 1 1 ADD A,Rn Add register to accumulator ADD A,Direct Add direct byte to accumulator 2 2 ADD A,@Ri Add indirect RAM to accumulator 1 2 ADD A,#data Add immediate data to accumulator 2 2 ADDC A,Rn Add register to accumulator with carry 1 1 ADDC A,Direct Add direct byte to accumulator with carry 2 2 ADDC A,@Ri Add indirect RAM to accumulator with carry 1 2 ADDC A,#data Add immediate data to accumulator with carry 2 2 SUBB A,Rn Subtract register from accumulator with borrow 1 1 SUBB A,Direct Subtract direct byte from accumulator with borrow 2 2 SUBB A,@Ri Subtract indirect RAM from accumulator with borrow 1 2 SUBB A,#data Subtract immediate data from accumulator with borrow 2 2 INC A Increment accumulator 1 1 INC Rn Increment register 1 2 INC Direct Increment direct byte 2 3 INC @Ri Increment indirect RAM 1 3 DEC A Decrement accumulator 1 1 DEC Rn Decrement register 1 2 DEC Direct Decrement direct byte 2 3 DEC @Ri Decrement indirect RAM 1 3 INC DPTR Increment data pointer 1 1 MUL Multiply accumulator and B 1 2 DIV Divide accumulator by B 1 6 DAA Decimal adjust accumulator 1 3 4.3.1.2 Logical Instructions The logical instructions perform Boolean operations such as AND, OR, XOR on bytes, rotate of accumulator contents, and swap of nibbles in an accumulator. The Boolean operations on the bytes are performed on the bit-by-bit basis. shows the list of logical instructions and their description. Table 4-2. Logical Instructions Mnemonic Description Bytes Cycles ANL A,Rn AND register to accumulator 1 1 ANL A,Direct AND direct byte to accumulator 2 2 ANL A,@Ri AND indirect RAM to accumulator 1 2 ANL A,#data AND immediate data to accumulator 2 2 ANL Direct, A AND accumulator to direct byte 2 3 ANL Direct, #data AND immediate data to direct byte 3 3 ORL A,Rn OR register to accumulator 1 1 ORL A,Direct OR direct byte to accumulator 2 2 ORL A,@Ri OR indirect RAM to accumulator 1 2 Document Number: 001-53304 Rev. *F Page 12 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data Table 4-2. Logical Instructions (continued) Bytes Cycles ORL A,#data Mnemonic OR immediate data to accumulator Description 2 2 ORL Direct, A OR accumulator to direct byte 2 3 ORL Direct, #data OR immediate data to direct byte 3 3 XRL A,Rn XOR register to accumulator 1 1 XRL A,Direct XOR direct byte to accumulator 2 2 XRL A,@Ri XOR indirect RAM to accumulator 1 2 XRL A,#data XOR immediate data to accumulator 2 2 XRL Direct, A XOR accumulator to direct byte 2 3 XRL Direct, #data XOR immediate data to direct byte 3 3 CLR A Clear accumulator 1 1 CPL A Complement accumulator 1 1 RL A Rotate accumulator left 1 1 RLC A Rotate accumulator left through carry 1 1 RR A Rotate accumulator right 1 1 RRC A Rotate accumulator right though carry 1 1 SWAP A Swap nibbles within accumulator 1 1 4.3.1.3 Data Transfer Instructions 4.3.1.4 Boolean Instructions The data transfer instructions are of three types: the core RAM, xdata RAM, and the look up tables. The core RAM transfer includes transfer between any two core RAM locations or SFRs. These instructions can use direct, indirect, register, and immediate addressing. The xdata RAM transfer includes only the transfer between the accumulator and the xdata RAM location. It can use only indirect addressing. The look up tables involve nothing but the read of program memory using the Indexed addressing mode. Table 4-3 lists the various data transfer instructions available. The 8051 core has a separate bit addressable memory location. It has 128 bits of bit addressable RAM and a set of SFRs that are bit addressable. The instruction set includes the whole menu of bit operations such as move, set, clear, toggle, OR, and AND instructions and the conditional jump instructions. Table 4-4 lists the available Boolean instructions. Table 4-3. Data Transfer Instructions Mnemonic Description Bytes Cycles MOV A,Rn Move register to accumulator 1 1 MOV A,Direct Move direct byte to accumulator 2 2 MOV A,@Ri Move indirect RAM to accumulator 1 2 MOV A,#data Move immediate data to accumulator 2 2 MOV Rn,A Move accumulator to register 1 1 MOV Rn,Direct Move direct byte to register 2 3 MOV Rn, #data Move immediate data to register 2 2 MOV Direct, A Move accumulator to direct byte 2 2 MOV Direct, Rn Move register to direct byte 2 2 MOV Direct, Direct Move direct byte to direct byte 3 3 MOV Direct, @Ri Move indirect RAM to direct byte 2 3 MOV Direct, #data Move immediate data to direct byte 3 3 MOV @Ri, A Move accumulator to indirect RAM 1 2 Document Number: 001-53304 Rev. *F Page 13 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data Table 4-3. Data Transfer Instructions (continued) Bytes Cycles MOV @Ri, Direct Mnemonic Move direct byte to indirect RAM Description 2 3 MOV @Ri, #data Move immediate data to indirect RAM 2 2 MOV DPTR, #data16 Load data pointer with 16 bit constant 3 3 MOVC A, @A+DPTR Move code byte relative to DPTR to accumulator 1 5 MOVC A, @A + PC Move code byte relative to PC to accumulator 1 4 MOVX A,@Ri Move external RAM (8 bit) to accumulator 1 3 MOVX A, @DPTR Move external RAM (16 bit) to accumulator 1 2 MOVX @Ri, A Move accumulator to external RAM (8 bit) 1 4 MOVX @DPTR, A Move accumulator to external RAM (16 bit) 1 3 PUSH Direct Push direct byte onto stack 2 3 POP Pop direct byte from stack 2 2 Direct XCH A, Rn Exchange register with accumulator 1 2 XCH A, Direct Exchange direct byte with accumulator 2 3 XCH A, @Ri Exchange indirect RAM with accumulator 1 3 Exchange low order indirect digit RAM with accumulator 1 3 Bytes Cycles XCHD A, @Ri Table 4-4. Boolean Instructions Mnemonic Description CLR C Clear carry 1 1 CLR bit Clear direct bit 2 3 SETB C Set carry 1 1 SETB bit Set direct bit 2 3 CPL C Complement carry 1 1 CPL bit Complement direct bit 2 3 ANL C, bit AND direct bit to carry 2 2 ANL C, /bit AND complement of direct bit to carry 2 2 ORL C, bit OR direct bit to carry 2 2 ORL C, /bit OR complement of direct bit to carry 2 2 MOV C, bit Move direct bit to carry 2 2 MOV bit, C Move carry to direct bit 2 3 JC Jump if carry is set 2 3 JNC rel rel Jump if no carry is set 2 3 JB Jump if direct bit is set 3 5 JNB bit, rel Jump if direct bit is not set 3 5 JBC bit, rel Jump if direct bit is set and clear bit 3 5 bit, rel Document Number: 001-53304 Rev. *F Page 14 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data 4.3.1.5 Program Branching Instructions The 8051 supports a set of conditional and unconditional jump instructions that help to modify the program execution flow. Table 4-5 shows the list of jump instructions. Table 4-5. Jump Instructions Mnemonic Description Bytes Cycles ACALL addr11 Absolute subroutine call 2 4 LCALL addr16 Long subroutine call 3 4 RET Return from subroutine 1 4 RETI Return from interrupt 1 4 AJMP addr11 Absolute jump 2 3 LJMP addr16 Long jump 3 4 SJMP rel Short jump (relative address) 2 3 JMP @A + DPTR Jump indirect relative to DPTR 1 5 JZ rel Jump if accumulator is zero 2 4 JNZ rel Jump if accumulator is nonzero 2 4 CJNE A,Direct, rel Compare direct byte to accumulator and jump if not equal 3 5 CJNE A, #data, rel Compare immediate data to accumulator and jump if not equal 3 4 CJNE Rn, #data, rel Compare immediate data to register and jump if not equal 3 4 CJNE @Ri, #data, rel Compare immediate data to indirect RAM and jump if not equal 3 5 DJNZ Rn,rel Decrement register and jump if not zero 2 4 DJNZ Direct, rel Decrement direct byte and jump if not zero 3 5 NOP No operation 1 1 4.4 DMA and PHUB 4.4.1 PHUB Features The PHUB and the DMA controller are responsible for data transfer between the CPU and peripherals, and also data transfers between peripherals. The PHUB and DMA also control device configuration during boot. The PHUB consists of: „ CPU and DMA controller are both bus masters to the PHUB „ A central hub that includes the DMA controller, arbiter, and „ Simultaneous CPU and DMA access to peripherals located on router „ Multiple spokes that radiate outward from the hub to most peripherals There are two PHUB masters: the CPU and the DMA controller. Both masters may initiate transactions on the bus. The DMA channels can handle peripheral communication without CPU intervention. The arbiter in the central hub determines which DMA channel is the highest priority if there are multiple requests. Document Number: 001-53304 Rev. *F „ Eight Multi-layer AHB Bus parallel access paths (spokes) for peripheral access different spokes „ Simultaneous DMA source and destination burst transactions on different spokes „ Supports 8, 16, 24, and 32-bit addressing and data Table 4-6. PHUB Spokes and Peripherals PHUB Spokes 0 Peripherals SRAM 1 IOs, PICU, EMIF 2 PHUB local configuration, Power manager, Clocks, IC, SWV, EEPROM, Flash programming interface 3 Analog interface and trim, Decimator 4 USB, CAN, I2C, Timers, Counters, and PWMs 5 Reserved 6 UDBs group 1 7 UDBs group 2 Page 15 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data 4.4.2 DMA Features 4.4.4 Transaction Modes Supported „ 24 DMA channels The flexible configuration of each DMA channel and the ability to chain multiple channels allow the creation of both simple and complex use cases. General use cases include, but are not limited to: „ Each channel has one or more Transaction Descriptors (TDs) to configure channel behavior. Up to 128 total TDs can be defined „ TDs can be dynamically updated 4.4.4.1 Simple DMA „ Eight levels of priority per channel In a simple DMA case, a single TD transfers data between a source and sink (peripherals or memory location). „ Any digitally routable signal, the CPU, or another DMA channel, 4.4.4.2 Auto Repeat DMA can trigger a transaction „ Each channel can generate up to two interrupts per transfer „ Transactions can be stalled or canceled „ Supports transaction size of infinite or 1 to 64k bytes „ TDs may be nested and/or chained for complex transactions 4.4.3 Priority Levels The CPU always has higher priority than the DMA controller when their accesses require the same bus resources. Due to the system architecture, the CPU can never starve the DMA. DMA channels of higher priority (lower priority number) may interrupt current DMA transfers. In the case of an interrupt, the current transfer is allowed to complete its current transaction. To ensure latency limits when multiple DMA accesses are requested simultaneously, a fairness algorithm guarantees an interleaved minimum percentage of bus bandwidth for priority levels 2 through 7. Priority levels 0 and 1 do not take part in the fairness algorithm and may use 100% of the bus bandwidth. If a tie occurs on two DMA requests of the same priority level, a simple round robin method is used to evenly share the allocated bandwidth. The round robin allocation can be disabled for each DMA channel, allowing it to always be at the head of the line. Priority levels 2 to 7 are guaranteed the minimum bus bandwidth shown in Table 4-7 after the CPU and DMA priority levels 0 and 1 have satisfied their requirements. Table 4-7. Priority Levels Auto repeat DMA is typically used when a static pattern is repetitively read from system memory and written to a peripheral. This is done with a single TD that chains to itself. 4.4.4.3 Ping Pong DMA A ping pong DMA case uses double buffering to allow one buffer to be filled by one client while another client is consuming the data previously received in the other buffer. In its simplest form, this is done by chaining two TDs together so that each TD calls the opposite TD when complete. 4.4.4.4 Circular DMA Circular DMA is similar to ping pong DMA except it contains more than two buffers. In this case there are multiple TDs; after the last TD is complete it chains back to the first TD. 4.4.4.5 Scatter Gather DMA In the case of scatter gather DMA, there are multiple noncontiguous sources or destinations that are required to effectively carry out an overall DMA transaction. For example, a packet may need to be transmitted off of the device and the packet elements, including the header, payload, and trailer, exist in various noncontiguous locations in memory. Scatter gather DMA allows the segments to be concatenated together by using multiple TDs in a chain. The chain gathers the data from the multiple locations. A similar concept applies for the reception of data onto the device. Certain parts of the received data may need to be scattered to various locations in memory for software processing convenience. Each TD in the chain specifies the location for each discrete element in the chain. Priority Level % Bus Bandwidth 0 100.0 4.4.4.6 Packet Queuing DMA 1 100.0 2 50.0 3 25.0 Packet queuing DMA is similar to scatter gather DMA but specifically refers to packet protocols. With these protocols, there may be separate configuration, data, and status phases associated with sending or receiving a packet. 4 12.5 5 6.2 6 3.1 7 1.5 When the fairness algorithm is disabled, DMA access is granted based solely on the priority level; no bus bandwidth guarantees are made. Document Number: 001-53304 Rev. *F For instance, to transmit a packet, a memory mapped configuration register can be written inside a peripheral, specifying the overall length of the ensuing data phase. The CPU can set up this configuration information anywhere in system memory and copy it with a simple TD to the peripheral. After the configuration phase, a data phase TD (or a series of data phase TDs) can begin (potentially using scatter gather). When the data phase TD(s) finish, a status phase TD can be invoked that reads some memory mapped status information from the peripheral and copies it to a location in system memory specified by the CPU for later inspection. Multiple sets of configuration, data, and status phase “subchains” can be strung together to create larger chains that transmit multiple packets in this way. A similar concept exists in the opposite direction to receive the packets. Page 16 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data 4.4.4.7 Nested DMA One TD may modify another TD, as the TD configuration space is memory mapped similar to any other peripheral. For example, a first TD loads a second TD’s configuration and then calls the second TD. The second TD moves data as required by the application. When complete, the second TD calls the first TD, which again updates the second TD’s configuration. This process repeats as often as necessary. Table 4-8. Interrupt Vector Table # Fixed Function DMA UDB 0 LVD phub_termout0[0] udb_intr[0] 1 ECC phub_termout0[1] udb_intr[1] 2 Reserved phub_termout0[2] udb_intr[2] 3 Sleep (Pwr Mgr) phub_termout0[3] udb_intr[3] 4.5 Interrupt Controller 4 PICU[0] phub_termout0[4] udb_intr[4] The interrupt controller provides a mechanism for hardware resources to change program execution to a new address, independent of the current task being executed by the main code. The interrupt controller provides enhanced features not found on original 8051 interrupt controllers: 5 PICU[1] phub_termout0[5] udb_intr[5] 6 PICU[2] phub_termout0[6] udb_intr[6] 7 PICU[3] phub_termout0[7] udb_intr[7] 8 PICU[4] phub_termout0[8] udb_intr[8] „ 32 interrupt vectors 9 PICU[5] phub_termout0[9] udb_intr[9] „ Jumps directly to ISR anywhere in code space with dynamic vector addresses „ Multiple sources for each vector „ Flexible interrupt to vector matching „ Each interrupt vector is independently enabled or disabled 10 PICU[6] phub_termout0[10] udb_intr[10] 11 PICU[12] phub_termout0[11] udb_intr[11] 12 PICU[15] phub_termout0[12] udb_intr[12] 13 Comparators Combined phub_termout0[13] udb_intr[13] 14 Switched Caps Combined phub_termout0[14] udb_intr[14] 15 I2C phub_termout0[15] udb_intr[15] „ Each interrupt can be dynamically assigned one of eight priorities „ Eight level nestable interrupts 16 CAN phub_termout1[0] udb_intr[16] „ Multiple I/O interrupt vectors 17 Timer/Counter0 phub_termout1[1] udb_intr[17] 18 Timer/Counter1 phub_termout1[2] udb_intr[18] 19 Timer/Counter2 phub_termout1[3] udb_intr[19] 20 Timer/Counter3 phub_termout1[4] udb_intr[20] 21 USB SOF Int phub_termout1[5] udb_intr[21] „ Software can send interrupts „ Software can clear pending interrupts When an interrupt is pending, the current instruction is completed and the program counter is pushed onto the stack. Code execution then jumps to the program address provided by the vector. After the ISR is completed, a RETI instruction is executed and returns execution to the instruction following the previously interrupted instruction. To do this the RETI instruction pops the program counter from the stack. If the same priority level is assigned to two or more interrupts, the interrupt with the lower vector number is executed first. Each interrupt vector may choose from three interrupt sources: Fixed Function, DMA, and UDB. The fixed function interrupts are direct connections to the most common interrupt sources and provide the lowest resource cost connection. The DMA interrupt sources provide direct connections to the two DMA interrupt sources provided per DMA channel. The third interrupt source for vectors is from the UDB digital routing array. This allows any digital signal available to the UDB array to be used as an interrupt source. Fixed function interrupts and all interrupt sources may be routed to any interrupt vector using the UDB interrupt source connections. Document Number: 001-53304 Rev. *F 22 USB Arb Int phub_termout1[6] udb_intr[22] 23 USB Bus Int phub_termout1[7] udb_intr[23] 24 USB Endpoint[0] phub_termout1[8] udb_intr[24] 25 USB Endpoint Data phub_termout1[9] udb_intr[25] 26 Reserved phub_termout1[10] udb_intr[26] 27 Reserved phub_termout1[11] udb_intr[27] 28 Reserved phub_termout1[12] udb_intr[28] 29 Decimator Int phub_termout1[13] udb_intr[29] 30 PHUB Error Int phub_termout1[14] udb_intr[30] 31 EEPROM Fault Int phub_termout1[15] udb_intr[31] Page 17 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data 5. Memory 5.1 Static RAM CY8C34 Static RAM (SRAM) is used for temporary data storage. Up to 8 KB of SRAM is provided and can be accessed by the 8051 or the DMA controller. See the “Memory Map” section on page 19. Simultaneous access of SRAM by the 8051 and the DMA controller is possible if different 4 KB blocks are accessed. 5.2 Flash Program Memory Flash memory in PSoC devices provides nonvolatile storage for user firmware, user configuration data, bulk data storage, and optional ECC data. The main flash memory area contains up to 64 KB of user program space. Up to an additional 8 KB of flash space is available for Error Correcting Codes (ECC). If ECC is not used this space can store device configuration data and bulk user data. User code may not be run out of the ECC flash memory section. ECC can correct one bit error and detect two bit errors per 8 bytes of firmware memory; an interrupt can be generated when an error is detected. Flash is read in units of rows; each row is 9 bytes wide with 8 bytes of data and 1 byte of ECC data. When a row is read, the data bytes are copied into an 8-byte instruction buffer. The CPU fetches its instructions from this buffer, for improved CPU performance. Flash programming is performed through a special interface and preempts code execution out of flash. The flash programming interface performs flash erasing, programming and setting code protection levels. Flash In System Serial Programming (ISSP), typically used for production programming, is possible through both the SWD and JTAG interfaces. In-system programming, typically used for bootloaders, is also possible using serial interfaces such as I2C, USB, UART, and SPI, or any communications protocol. 5.3 Flash Security All PSoC devices include a flexible flash protection model that prevents access and visibility to on-chip flash memory. This prevents duplication or reverse engineering of proprietary code. Flash memory is organized in blocks, where each block contains 256 bytes of program or data and 32 bytes of ECC or configuration data. A total of up to 256 blocks are provided on 64 KB flash devices. The device offers the ability to assign one of four protection levels to each row of flash. Table 5-1 lists the protection modes available. Flash protection levels can only be changed by performing a complete flash erase. The Full Protection and Field Upgrade settings disable external access (through a debugging tool such as PSoC Creator, for example). If your application requires code update through a boot loader, then use the Field Upgrade setting. Use the Unprotected setting only when no security is needed in your application. The PSoC device also offers an advanced security feature called Device Security which permanently disables all test, programming, and debug ports, protecting your application from external access (see the “Device Security” section on page 58). For more information on how to take full advantage of the security features in PSoC, see the PSoC 3 TRM. Document Number: 001-53304 Rev. *F Table 5-1. Flash Protection Protection Setting Allowed Not Allowed Unprotected External read and write + internal read and write Factory Upgrade External write + internal read and write External read Field Upgrade Internal read and write External read and write Full Protection Internal read External read and write + internal write Disclaimer Note the following details of the flash code protection features on Cypress devices. Cypress products meet the specifications contained in their particular Cypress data sheets. Cypress believes that its family of products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress, that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Cypress is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress are committed to continuously improving the code protection features of our products. 5.4 EEPROM PSoC EEPROM memory is a byte addressable nonvolatile memory. The CY8C34 has up to 2 KB of EEPROM memory to store user data. Reads from EEPROM are random access at the byte level. Reads are done directly; writes are done by sending write commands to an EEPROM programming interface. CPU code execution can continue from flash during EEPROM writes. EEPROM is erasable and writeable at the row level. The EEPROM is divided into 128 rows of 16 bytes each. The CPU can not execute out of EEPROM. There is no ECC hardware associated with EEPROM. If ECC is required it must be handled in firmware. 5.5 External Memory Interface CY8C34 provides an External Memory Interface (EMIF) for connecting to external memory devices. The connection allows read and write accesses to external memories. The EMIF operates in conjunction with UDBs, I/O ports, and other hardware to generate external memory address and control signals. Figure 5-1 is the EMIF block diagram. The EMIF supports synchronous and asynchronous memories. The CY8C34 supports only one type of external memory device at a time. External memory can be accessed via the 8051 xdata space; up to 24 address bits can be used. See “xdata Space” section on page 21. The memory can be 8 or 16 bits wide. Page 18 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data Figure 5-1. EMIF Block Diagram Address Signals External_ MEM_ ADDR[23:0] IO PORTs Data Signals External_ MEM_ DATA[15:0] IO PORTs Control Signals IO PORTs Data, Address, and Control Signals IO IF PHUB Data, Address, and Control Signals Control DSI Dynamic Output Control UDB DSI to Port Data, Address, and Control Signals EM Control Signals Other Control Signals EMIF 5.6 Memory Map The CY8C34 8051 memory map is very similar to the MCS-51 memory map. 5.6.1 Code Space The CY8C34 8051 code space is 64 KB. Only main flash exists in this space. See the “Flash Program Memory” section on page 18. 5.6.2 Internal Data Space The CY8C34 8051 internal data space is 384 bytes, compressed within a 256-byte space. This space consists of 256 bytes of RAM (in addition to the SRAM mentioned in “Static RAM” on page 18) and a 128-byte space for Special Function Registers (SFRs). See Figure 5-2. The lowest 32 bytes are used for 4 banks of registers R0-R7. The next 16 bytes are bit-addressable. Document Number: 001-53304 Rev. *F Figure 5-2. 8051 Internal Data Space 0x00 0x1F 0x20 0x2F 0x30 0x7F 0x80 0xFF 4 Banks, R0-R7 Each Bit Addressable Area Lower Core RAM Shared with Stack Space (direct and indirect addressing) Upper Core RAM Shared with Stack Space (indirect addressing) SFR Special Function Registers (direct addressing) Page 19 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data In addition to the register or bit address modes used with the lower 48 bytes, the lower 128 bytes can be accessed with direct or indirect addressing. With direct addressing mode, the upper 128 bytes map to the SFRs. With indirect addressing mode, the upper 128 bytes map to RAM. Stack operations use indirect addressing; the 8051 stack space is 256 bytes. See the “Addressing Modes” section on page 11 5.6.3 SFRs The Special Function Register (SFR) space provides access to frequently accessed registers. The memory map for the SFR memory space is shown in Table 5-2. Table 5-2. SFR Map Address 0/8 0xF8 SFRPRT15DR 0xF0 B 0xE8 SFRPRT12DR 0xE0 ACC 1/9 SFRPRT15PS 2/A 3/B 4/C 5/D 6/E 7/F SFRPRT15SEL SFRPRT12SEL SFRPRT12PS MXAX SFRPRT6PS SFRPRT6SEL 0xD8 SFRPRT6DR 0xD0 PSW 0xC8 SFRPRT5DR SFRPRT5PS SFRPRT5SEL 0xC0 SFRPRT4DR SFRPRT4PS SFRPRT4SEL 0xB0 SFRPRT3DR SFRPRT3PS SFRPRT3SEL 0xA8 IE 0xA0 P2AX 0xB8 SFRPRT1SEL 0x98 SFRPRT2DR SFRPRT2PS 0x90 SFRPRT1DR SFRPRT1PS SFRPRT0PS SFRPRT0SEL SFRPRT0DR SP DPL0 0x88 0x80 SFRPRT2SEL DPX0 The CY8C34 family provides the standard set of registers found on industry standard 8051 devices. In addition, the CY8C34 devices add SFRs to provide direct access to the I/O ports on the device. The following sections describe the SFRs added to the CY8C34 family. XData Space Access SFRs The 8051 core features dual DPTR registers for faster data transfer operations. The data pointer select SFR, DPS, selects which data pointer register, DPTR0 or DPTR1, is used for the following instructions: DPH0 DPX1 DPL1 DPH1 DPS During a MOVX instruction using the R0 or R1 register, the most significant byte of the address is always equal to the contents of MXAX, and the next most significant byte is always equal to the contents of P2AX. I/O Port SFRs The I/O ports provide digital input sensing, output drive, pin interrupts, connectivity for analog inputs and outputs, LCD, and access to peripherals through the DSI. Full information on I/O ports is found in “I/O System and Routing” on page 29. „ MOVX A, @DPTR I/O ports are linked to the CPU through the PHUB and are also available in the SFRs. Using the SFRs allows faster access to a limited set of I/O port registers, while using the PHUB allows boot configuration and access to all I/O port registers. „ MOVC A, @A+DPTR Each SFR supported I/O port provides three SFRs: „ JMP @A+DPTR „ SFRPRTxDR sets the output data state of the port (where x is „ MOVX @DPTR, A „ INC DPTR „ MOV DPTR, #data16 The extended data pointer SFRs, DPX0, DPX1, MXAX, and P2AX, hold the most significant parts of memory addresses during access to the xdata space. These SFRs are used only with the MOVX instructions. During a MOVX instruction using the DPTR0/DPTR1 register, the most significant byte of the address is always equal to the contents of DPX0/DPX1. Document Number: 001-53304 Rev. *F port number and includes ports 0-6, 12 and 15). „ The SFRPRTxSEL selects whether the PHUB PRTxDR register or the SFRPRTxDR controls each pin’s output buffer within the port. If a SFRPRTxSEL[y] bit is high, the corresponding SFRPRTxDR[y] bit sets the output state for that pin. If a SFRPRTxSEL[y] bit is low, the corresponding PRTxDR[y] bit sets the output state of the pin (where y varies from 0 to 7). „ The SFRPRTxPS is a read only register that contains pin state values of the port pins. Page 20 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data 6. System Integration 5.6.3.1 xdata Space The 8051 xdata space is 24-bit, or 16 MB in size. The majority of this space is not “external”—it is used by on-chip components. See Table 5-3. External, that is, off-chip, memory can be accessed using the EMIF. See External Memory Interface. Table 5-3. XDATA Data Address Map Address Range Purpose 0x00 0000 - 0x00 1FFF SRAM 0x00 4000 - 0x00 42FF Clocking, PLLs, and oscillators 0x00 4300 - 0x00 43FF Power management 0x00 4400 - 0x00 44FF Interrupt controller 0x00 4500 - 0x00 45FF Ports interrupt control 0x00 4700 - 0x00 47FF System performance controller 0x00 4900 - 0x00 49FF I2C controller 0x00 4E00 - 0x00 4EFF Decimator 0x00 4F00 - 0x00 4FFF Fixed timer/counter/PWMs 0x00 5000 - 0x00 51FF General purpose I/Os 0x00 5300 - 0x00 530F Output port select register 0x00 5400 - 0x00 54FF External Memory Interface control registers 0x00 5800 - 0x00 5FFF Analog Subsystem interface 0x00 6000 - 0x00 60FF USB controller 0x00 6400 - 0x00 6FFF UDB configuration 0x00 7000 - 0x00 7FFF PHUB configuration 0x00 8000 - 0x00 8FFF EEPROM 0x00 A000 - 0x00 A400 CAN 0x01 0000 - 0x01 FFFF Digital Interconnect configuration 0x03 0000 - 0x03 01FF Reserved 0x05 0220 - 0x05 02F0 Debug controller 0x08 0000 - 0x08 1FFF Flash ECC bytes 0x80 0000 - 0xFF FFFF External Memory Interface 6.1 Clocking System The clocking system generates, divides, and distributes clocks throughout the PSoC system. For the majority of systems, no external crystal is required. The IMO and PLL together can generate up to a 50 MHz clock, accurate to ±1% over voltage and temperature. Additional internal and external clock sources allow each design to optimize accuracy, power, and cost. All of the system clock sources can be used to generate other clock frequencies in the 16-bit clock dividers and UDBs for anything the user wants, for example a UART baud rate generator. Clock generation and distribution is automatically configured through the PSoC Creator IDE graphical interface. This is based on the complete system’s requirements. It greatly speeds the design process. PSoC Creator allows designers to build clocking systems with minimal input. The designer can specify desired clock frequencies and accuracies, and the software locates or builds a clock that meets the required specifications. This is possible because of the programmability inherent PSoC. Key features of the clocking system include: „ Seven general purpose clock sources 3 to 24 MHz IMO, ±1% at 3 MHz 4 to 33 MHz External Crystal Oscillator (MHzECO) ‡ Clock doubler provides a doubled clock frequency output for the USB block, see USB Clock Domain on page 24 ‡ DSI signal from an external I/O pin or other logic ‡ 24 to 50 MHz fractional Phase-Locked Loop (PLL) sourced from IMO, MHzECO, or DSI ‡ Clock Doubler ‡ 1 kHz, 33 kHz, 100 kHz ILO for Watch Dog Timer (WDT) and Sleep Timer ‡ 32.768 kHz External Crystal Oscillator (kHzECO) for Real Time Clock (RTC) ‡ ‡ „ IMO has a USB mode that auto locks to the USB bus clock requiring no external crystal for USB. (USB equipped parts only) „ Independently sourced clock in all clock dividers „ Eight 16-bit clock dividers for the digital system „ Four 16-bit clock dividers for the analog system „ Dedicated 16-bit divider for the bus clock „ Dedicated 4-bit divider for the CPU clock „ Automatic clock configuration in PSoC Creator Document Number: 001-53304 Rev. *F Page 21 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data Table 6-1. Oscillator Summary Source IMO MHzECO Fmin 3 MHz 4 MHz Tolerance at Fmin ±1% over voltage and temperature Crystal dependent Fmax 24 MHz 33 MHz Tolerance at Fmax ±4% Crystal dependent DSI PLL Doubler ILO 0 MHz 24 MHz 12 MHz 1 kHz Input dependent Input dependent Input dependent -50%, +100% 50 MHz 50 MHz 48 MHz 100 kHz Input dependent Input dependent Input dependent -55%, +100% kHzECO 32 kHz Crystal dependent 32 kHz Crystal dependent Startup Time 10 µs max 5 ms typ, max is crystal dependent Input dependent 250 µs max 1 µs max 15 ms max in lowest power mode 500 ms typ, max is crystal dependent Figure 6-1. Clocking Subsystem 3-24 MHz IMO 4-33 MHz ECO External IO or DSI 0-50 MHz 32 kHz ECO 1,33,100 kHz ILO 12-48 MHz Doubler CPU Clock CPU Clock Divider 4 bit 24-50 MHz PLL System Clock Mux Bus Clock Bus Clock Divider 16 bit Digital Clock Divider 16 bit Digital Clock Divider 16 bit Analog Clock Divider 16 bit s k e w Digital Clock Divider 16 bit Digital Clock Divider 16 bit Analog Clock Divider 16 bit s k e w Digital Clock Divider 16 bit Digital Clock Divider 16 bit Analog Clock Divider 16 bit s k e w Digital Clock Divider 16 bit Digital Clock Divider 16 bit Analog Clock Divider 16 bit s k e w 7 7 6.1.1 Internal Oscillators 6.1.1.2 Clock Doubler 6.1.1.1 Internal Main Oscillator The clock doubler outputs a clock at twice the frequency of the input clock. The doubler works for input frequency ranges of 6 to 24 MHz (providing 12 to 48 MHz at the output). It can be configured to use a clock from the IMO, MHzECO, or the DSI (external pin). The doubler is typically used to clock the USB. In most designs the IMO is the only clock source required, due to its ±1% accuracy. The IMO operates with no external components and outputs a stable clock. A factory trim for each frequency range is stored in the device. With the factory trim, tolerance varies from ±1% at 3 MHz, up to ±4% at 24 MHz. The IMO, in conjunction with the PLL, allows generation of CPU and system clocks up to the device's maximum frequency (see Phase-Locked Loop). The IMO provides clock outputs at 3, 6, 12, and 24 MHz. Document Number: 001-53304 Rev. *F 6.1.1.3 Phase-Locked Loop The PLL allows low frequency, high accuracy clocks to be multiplied to higher frequencies. This is a tradeoff between higher clock frequency and accuracy and, higher power consumption and increased startup time. Page 22 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data The PLL block provides a mechanism for generating clock frequencies based upon a variety of input sources. The PLL outputs clock frequencies in the range of 24 to 50 MHz. Its input and feedback dividers supply 4032 discrete ratios to create almost any desired system clock frequency. The accuracy of the PLL output depends on the accuracy of the PLL input source. The most common PLL use is to multiply the IMO clock at 3 MHz, where it is most accurate to generate the CPU and system clocks up to the device’s maximum frequency. The PLL achieves phase lock within 250 µs (verified by bit setting). It can be configured to use a clock from the IMO, MHzECO or DSI (external pin). The PLL clock source can be used until lock is complete and signaled with a lock bit. The lock signal can be routed through the DSI to generate an interrupt. Disable the PLL before entering low power modes. 6.1.1.4 Internal Low Speed Oscillator The ILO provides clock frequencies for low power consumption, including the watchdog timer, and sleep timer. The ILO generates up to three different clocks: 1 kHz, 33 kHz, and 100 kHz. The 1 kHz clock (CLK1K) is typically used for a background ‘heartbeat’ timer. This clock inherently lends itself to low power supervisory operations such as the watchdog timer and long sleep intervals using the central timewheel (CTW). The central timewheel is a 1 kHz, free running, 13-bit counter clocked by the ILO. The central timewheel is always enabled except in hibernate mode and when the CPU is stopped during debug on chip mode. It can be used to generate periodic interrupts for timing purposes or to wake the system from a low power mode. Firmware can reset the central timewheel. Systems that require accurate timing should use the Real Time Clock capability instead of the central timewheel. The 100 kHz clock (CLK100K) works as a low power system clock to run the CPU. It can also generate time intervals such as fast sleep intervals using the fast timewheel. “Phase-Locked Loop” section on page 22). The GPIO pins connecting to the external crystal and capacitors are fixed. MHzECO accuracy depends on the crystal chosen. Figure 6-2. MHzECO Block Diagram The MHzECO provides high frequency, high precision clocking using an external crystal (see Figure 6-2). It supports a wide variety of crystal types, in the range of 4 to 33 MHz. When used in conjunction with the PLL, it can generate CPU and system clocks up to the device's maximum frequency (see Document Number: 001-53304 Rev. *F 4 – 33 MHz crystal External Components Capacitors 6.1.2.2 32.768 kHz ECO The 32.768 kHz External Crystal Oscillator (32kHzECO) provides precision timing with minimal power consumption using an external 32.768 kHz watch crystal (see Figure 6-3). The 32kHzECO also connects directly to the sleep timer and provides the source for the Real Time Clock (RTC). The RTC uses a 1 second interrupt to implement the RTC functionality in firmware. The oscillator works in two distinct power modes. This allows users to trade off power consumption with noise immunity from neighboring circuits. The GPIO pins connected to the external crystal and capacitors are fixed. Figure 6-3. 32kHzECO Block Diagram 32 kHz Crystal Osc The 33 kHz clock (CLK33K) comes from a divide-by-3 operation on CLK100K. This output can be used as a reduced accuracy version of the 32.768 kHz ECO clock with no need for a crystal. 6.1.2.1 MHz External Crystal Oscillator Xo (Pin P15[0]) Xi (Pin P15[1]) The fast timewheel is a 100 kHz, 5-bit counter clocked by the ILO that can also be used to wake the system. The fast timewheel settings are programmable, and the counter automatically resets when the terminal count is reached. This enables flexible, periodic wakeups of the CPU at a higher rate than is allowed using the central timewheel. The fast timewheel can generate an optional interrupt each time the terminal count is reached. 6.1.2 External Oscillators XCLK_MHZ 4 - 33 MHz Crystal Osc Xi (Pin P15[3]) External Components XCLK32K Xo (Pin P15[2]) 32 kHz crystal Capacitors Page 23 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data 6.1.2.3 Digital System Interconnect The DSI provides routing for clocks taken from external clock oscillators connected to I/O. The oscillators can also be generated within the device in the digital system and Universal Digital Blocks. While the primary DSI clock input provides access to all clocking resources, up to eight other DSI clocks (internally or externally generated) may be routed directly to the eight digital clock dividers. This is only possible if there are multiple precision clock sources. 6.1.3 Clock Distribution All seven clock sources are inputs to the central clock distribution system. The distribution system is designed to create multiple high precision clocks. These clocks are customized for the design’s requirements and eliminate the common problems found with limited resolution prescalers attached to peripherals. The clock distribution system generates several types of clock trees. „ The system clock is used to select and supply the fastest clock in the system for general system clock requirements and clock synchronization of the PSoC device. „ Bus Clock 16-bit divider uses the system clock to generate the system's bus clock used for data transfers. Bus clock is the source clock for the CPU clock divider. clock sources for any purpose. Examples include baud rate generators, accurate PWM periods, and timer clocks, and many others. If more than eight digital clock dividers are required, the Universal Digital Blocks (UDBs) and fixed function Timer/Counter/PWMs can also generate clocks. „ Four 16-bit clock dividers generate clocks for the analog system components that require clocking, such as ADC and mixers. The analog clock dividers include skew control to ensure that critical analog events do not occur simultaneously with digital switching events. This is done to reduce analog system noise. Each clock divider consists of an 8-input multiplexer, a 16-bit clock divider (divide by 2 and higher) that generates ~50% duty cycle clocks, system clock resynchronization logic, and deglitch logic. The outputs from each digital clock tree can be routed into the digital system interconnect and then brought back into the clock system as an input, allowing clock chaining of up to 32 bits. 6.1.4 USB Clock Domain The USB clock domain is unique in that it operates largely asynchronously from the main clock network. The USB logic contains a synchronous bus interface to the chip, while running on an asynchronous clock to process USB data. The USB logic requires a 48 MHz frequency. This frequency can be generated from different sources, including DSI clock at 48 MHz or doubled value of 24 MHz from internal oscillator, DSI signal, or crystal oscillator. „ Eight fully programmable 16-bit clock dividers generate digital system clocks for general use in the digital system, as configured by the design’s requirements. Digital system clocks can generate custom clocks derived from any of the seven Document Number: 001-53304 Rev. *F Page 24 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data 6.2 Power System The power system consists of separate analog, digital, and I/O supply pins, labeled Vdda, Vddd, and Vddiox, respectively. It also includes two internal 1.8V regulators that provide the digital (Vccd) and analog (Vcca) supplies for the internal core logic. The output pins of the regulators (Vccd and Vcca) and the Vddio pins must have capacitors connected as shown in Figure 6-4. The two Vccd pins must be shorted together, with as short a trace as possible, and connected to a 1 µF ±10% X5R capacitor. The power system also contains a sleep regulator, an I2C regulator, and a hibernate regulator. Figure 6-4. PSoC Power System 1 µF Vddio2 Vddd Vddd I/ O Supply Vssd Vccd Vddio2 Vddio0 0.1µF 0.1µF I/ O Supply Vddio0 0.1µF I2C Regulator Sleep Regulator Digital Domain Vdda Vdda Vcca Analog Regulator Digital Regulators Vssd 0.1µF 1 µF . Vssa Analog Domain 0.1µF I/O Supply Vddio3 Vddd Vssd I/O Supply Vccd Vddio1 Hibernate Regulator 0.1µF 0.1µF Vddio1 Vddd Vddio3 Note The two Vccd pins must be connected together with as short a trace as possible. A trace under the device is recommended, as shown in Figure 2-6. 6.2.1 Power Modes „ Hibernate PSoC 3 devices have four different power modes, as shown in Table 6-2 and Table 6-3. The power modes allow a design to easily provide required functionality and processing power while simultaneously minimizing power consumption and maximizing battery life in low power and portable devices. Active is the main processing mode. Its functionality is configurable. Each power controllable subsystem is enabled or disabled by using separate power configuration template registers. In alternate active mode, fewer subsystems are enabled, reducing power. In sleep mode most resources are disabled regardless of the template settings. Sleep mode is optimized to provide timed sleep intervals and Real Time Clock functionality. The lowest power mode is hibernate, which retains register and SRAM state, but no clocks, and allows wakeup only from I/O pins. Figure 6-5 illustrates the allowable transitions between power modes. PSoC 3 power modes, in order of decreasing power consumption are: „ Active „ Alternate Active „ Sleep Document Number: 001-53304 Rev. *F Page 25 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data Table 6-2. Power Modes Power Modes Description Entry Condition Wakeup Source Active Clocks Regulator Active Primary mode of operation, all Wakeup, reset, peripherals available (program- manual register entry mable) Any interrupt Any (programmable) All regulators available. Digital and analog regulators can be disabled if external regulation used. Alternate Active Manual register Similar to Active mode, and is entry typically configured to have fewer peripherals active to reduce power. One possible configuration is to turn off the CPU and flash, and run peripherals at full speed Any interrupt Any (programmable) All regulators available. Digital and analog regulators can be disabled if external regulation used. Sleep All subsystems automatically disabled Comparator, ILO/kHzECO PICU, I2C, RTC, CTW, LVD Both digital and analog regulators buzzed. Digital and analog regulators can be disabled if external regulation used. Hibernate Manual register All subsystems automatically entry disabled Lowest power consuming mode with all peripherals and internal regulators disabled, except hibernate regulator is enabled Configuration and memory contents retained PICU Only hibernate regulator active. Manual register entry Table 6-3. Power Modes Wakeup Time and Power Consumption Sleep Modes Wakeup Time Current (typ) Active - Alternate Active Code Execution Digital Resources Analog Resources Clock Sources Available Wakeup Sources Reset Sources 1.2 mA[1] Yes All All All - All - TBD User defined All All All - All 3.6V. Document Number: 001-53304 Rev. *F Vbat 22 µF Vssb Vssa Vssd The boost converter can be operated in two different modes: active and standby. Active mode is the normal mode of operation where the boost regulator actively generates a regulated output voltage. In standby mode, most boost functions are disabled, thus reducing power consumption of the boost circuit. The converter can be configured to provide low power, low current regulation in the standby mode. The external 32 kHz crystal can be used to generate inductor boost pulses on the rising and falling edge of the clock when the output voltage is less than the programmed value. This is called automatic thump mode (ATM). The boost typically draws 200 µA in active mode and 12 µA in standby mode. The boost operating modes must be used in conjunction with chip power modes to minimize the total chip power consumption. Table 6-4 lists the boost power modes available in different chip power modes. Table 6-4. Chip and Boost Power Modes Compatibility Chip Power Modes Boost Power Modes Chip -Active mode Boost can be operated in either active or standby mode. Chip -Sleep mode Boost can be operated in either active or standby mode. However, it is recommended to operate boost in standby mode for low power consumption Chip-Hibernate mode Boost can only be operated in active mode. However, it is recommended not to use boost in chip hibernate mode due to high current consumption in boost active mode The switching frequency can be set to 100 kHz, 400 kHz, 2 MHz, or 32 kHz to optimize efficiency and component cost. The 100 kHz, 400 kHz, and 2 MHz switching frequencies are generated using oscillators internal to the boost converter block. When the 32 kHz switching frequency is selected, the clock is derived from a 32 kHz external crystal oscillator. The 32 kHz external clock is primarily intended for boost standby mode. If the boost converter is not used in a given application, tie the Vbat, Vssb, and Vboost pins to ground and leave the Ind pin unconnected. Page 27 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data 6.3 Reset CY8C34 has multiple internal and external reset sources available. The reset sources are: „ Power source monitoring - The analog and digital power voltages, Vdda, Vddd, Vcca, and Vccd are monitored in several different modes during power up, active mode, and sleep mode (buzzing). If any of the voltages goes outside predetermined ranges then a reset is generated. The monitors are programmable to generate an interrupt to the processor under certain conditions before reaching the reset thresholds. „ External - The device can be reset from an external source by pulling the reset pin (XRES) low. The XRES pin includes an internal pull up to Vddio1. Vddd, Vdda, and Vddio1 must all have voltage applied before the part comes out of reset. „ Watchdog timer - A watchdog timer monitors the execution of instructions by the processor. If the watchdog timer is not reset by firmware within a certain period of time, the watchdog timer generates a reset. „ Software - The device can be reset under program control. Figure 6-7. Resets Vddd Vdda corresponding internal regulators. The trip level is not precise. It is set to approximately 1 volt, which is below the lowest specified operating voltage but high enough for the internal circuits to be reset and to hold their reset state. The monitor generates a reset pulse that is at least 100 ns wide. It may be much wider if one or more of the voltages ramps up slowly. To save power the IPOR circuit is disabled when the internal digital supply is stable. Voltage supervision is then handed off to the precise low voltage reset (PRES) circuit. When the voltage is high enough for PRES to release, the IMO starts. „ PRES - Precise Low Voltage Reset This circuit monitors the outputs of the analog and digital internal regulators after power up. The regulator outputs are compared to a precise reference voltage. The response to a PRES trip is identical to an IPOR reset. In normal operating mode, the program cannot disable the digital PRES circuit. The analog regulator can be disabled, which also disables the analog portion of the PRES. The PRES circuit is disabled automatically during sleep and hibernate modes, with one exception: During sleep mode the regulators are periodically activated (buzzed) to provide supervisory services and to reduce wakeup time. At these times the PRES circuit is also buzzed to allow periodic voltage monitoring. „ ALVI, DLVI, AHVI - Analog/Digital Low Voltage Interrupt, Analog High Voltage Interrupt Power Voltage Level Monitors Processor Interrupt Reset Pin External Reset Reset Controller System Reset Interrupt circuits are available to detect when Vdda and Vddd go outside a voltage range. For AHVI, Vdda is compared to a fixed trip level. For ALVI and DLVI, Vdda and Vddd are compared to trip levels that are programmable, as listed in Table 6-5. ALVI and DLVI can also be configured to generate a device reset instead of an interrupt. Table 6-5. Analog/Digital Low Voltage Interrupt, Analog High Voltage Interrupt Watchdog Timer Interrupt Supply A reset status register holds the source of the most recent reset or power voltage monitoring interrupt. The program may examine this register to detect and report exception conditions. This register is cleared after a power on reset. 6.3.1 Reset Sources Available Trip Accuracy Settings DLVI VDDD 1.71V-5.5V 1.70V-5.45V in 250 mV increments ±2% ALVI VDDA 1.71V-5.5V 1.70V-5.45V in 250 mV increments ±2% AHVI VDDA 1.71V-5.5V 5.75V ±2% Software Reset Register The term device reset indicates that the processor as well as analog and digital peripherals and registers are reset. Normal Voltage Range The monitors are disabled until after IPOR. During sleep mode these circuits are periodically activated (buzzed). If an interrupt occurs during buzzing then the system first enters its wake up sequence. The interrupt is then recognized and may be serviced. 6.3.1.1 Power Voltage Level Monitors „ IPOR - Initial Power on Reset At initial power on, IPOR monitors the power voltages Vddd and Vdda, both directly at the pins and at the outputs of the Document Number: 001-53304 Rev. *F Page 28 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data 6.3.1.2 Other Reset Sources „ XRES - External Reset PSoC 3 has either a single GPIO pin that is configured as an external reset or a dedicated XRES pin. Either the dedicated XRES pin or the GPIO pin, if configured, holds the part in reset while held active (low). The response to an XRES is the same as to an IPOR reset. The external reset is active low. It includes an internal pull up resistor. XRES is active during sleep and hibernate modes. „ SRES - Software Reset A reset can be commanded under program control by setting a bit in the software reset register. This is done either directly by the program or indirectly by DMA access. The response to a SRES is the same as after an IPOR reset. Another register bit exists to disable this function. „ DRES - Digital Logic Reset A logic signal can be routed from the UDBs or other digital peripheral source through the DSI to the Configurable XRES pin, P1[2], to generate a hardware-controlled reset. The pin must be placed in XRES mode. The response to a DRES is the same as after an IPOR reset. „ WRES - Watchdog Timer Reset The watchdog reset detects when the software program is no longer being executed correctly. To indicate to the watchdog timer that it is running correctly, the program must periodically reset the timer. If the timer is not reset before a user-specified amount of time, then a reset is generated. Note IPOR disables the watchdog function. The program must enable the watchdog function at an appropriate point in the code by setting a register bit. When this bit is set, it cannot be cleared again except by an IPOR power on reset event. 6.4 I/O System and Routing PSoC I/Os are extremely flexible. Every GPIO has analog and digital I/O capability. All I/Os have a large number of drive modes, which are set at POR. PSoC also provides up to four individual I/O voltage domains through the Vddio pins. There are two types of I/O pins on every device; those with USB provide a third type. Both General Purpose I/O (GPIO) and Special I/O (SIO) provide similar digital functionality. The primary differences are their analog capability and drive strength. Devices that include USB also provide two USBIO pins that support specific USB functionality as well as limited GPIO capability. All I/O pins are available for use as digital inputs and outputs for both the CPU and digital peripherals. In addition, all I/O pins can Document Number: 001-53304 Rev. *F generate an interrupt. The flexible and advanced capabilities of the PSoC I/O, combined with any signal to any pin routability, greatly simplify circuit design and board layout. All GPIO pins can be used for analog input, CapSense[4], and LCD segment drive, while SIO pins are used for voltages in excess of Vdda and for programmable output voltages. „ Features supported by both GPIO and SIO: User programmable port reset state Separate I/O supplies and voltages for up to four groups of I/O ‡ Digital peripherals use DSI to connect the pins ‡ Input or output or both for CPU and DMA ‡ Eight drive modes ‡ Every pin can be an interrupt source configured as rising edge, falling edge or both edges. If required, level sensitive interrupts are supported through the DSI ‡ Dedicated port interrupt vector for each port ‡ Slew rate controlled digital output drive mode ‡ Access port control and configuration registers on either port basis or pin basis ‡ Separate port read (PS) and write (DR) data registers to avoid read modify write errors ‡ Special functionality on a pin by pin basis ‡ ‡ „ Additional features only provided on the GPIO pins: LCD segment drive on LCD equipped devices CapSense[4] ‡ Analog input and output capability ‡ Continuous 100 µA clamp current capability ‡ Standard drive strength down to 1.7V ‡ ‡ „ Additional features only provided on SIO pins: Higher drive strength than GPIO Hot swap capability (5V tolerance at any operating Vdd) ‡ Programmable and regulated high input and output drive levels down to 1.2V ‡ No analog input, CapSense, or LCD capability ‡ Over voltage tolerance up to 5.5V ‡ SIO can act as a general purpose analog comparator ‡ ‡ „ USBIO features: Full speed USB 2.0 compliant I/O Highest drive strength for general purpose use ‡ Input, output, or both for CPU and DMA ‡ Input, output, or both for digital peripherals ‡ Digital output (CMOS) drive mode ‡ Each pin can be an interrupt source configured as rising edge, falling edge, or both edges ‡ ‡ Page 29 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data Figure 6-8. GPIO Block Diagram Digital Input Path Naming Convention ‘x’ = Port Number ‘y’ = Pin Number PRT[x]CTL PRT[x]DBL_SYNC_IN PRT[x]PS Digital System Input PICU[x]INTTYPE[y] Input Buffer Disable PICU[x]INTSTAT Interrupt Logic Pin Interrupt Signal PICU[x]INTSTAT Digital Output Path PRT[x]SLW PRT[x]SYNC_OUT Vddio Vddio PRT[x]DR 0 In Digital System Output 1 Vddio PRT[x]BYP Drive Logic PRT[x]DM2 PRT[x]DM1 PRT[x]DM0 Bidirectional Control PRT[x]BIE Analog Slew Cntl PIN OE 1 0 1 Capsense Global Control 0 1 CAPS[x]CFG1 Switches PRT[x]AG Analog Global Enable PRT[x]AMUX Analog Mux Enable LCD Display Data PRT[x]LCD_COM_SEG Logic & MUX PRT[x]LCD_EN LCD Bias Bus Document Number: 001-53304 Rev. *F 5 Page 30 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data Figure 6-9. SIO Input/Output Block Diagram Digital Input Path PRT[x]SIO_HYST_EN PRT[x]SIO_DIFF Reference Level PRT[x]DBL_SYNC_IN Naming Convention ‘x’ = Port Number ‘y’ = Pin Number Buffer Thresholds PRT[x]PS Digital System Input PICU[x]INTTYPE[y] Input Buffer Disable PICU[x]INTSTAT Interrupt Logic Pin Interrupt Signal PICU[x]INTSTAT Digital Output Path Reference Level PRT[x]SIO_CFG PRT[x]SLW PRT[x]SYNC_OUT PRT[x]DR Driver Vhigh 0 Digital System Output In 1 PRT[x]BYP Drive Logic PRT[x]DM2 PRT[x]DM1 PRT[x]DM0 Bidirectional Control PRT[x]BIE Slew Cntl PIN OE Figure 6-10. USBIO Block Diagram Digital Input Path Naming Convention ‘x’ = Port Number ‘y’ = Pin Number USB Receiver Circuitry PRT[x]DBL_SYNC_IN USBIO_CR1[0,1] Digital System Input PICU[x]INTTYPE[y] PICU[x]INTSTAT Interrupt Logic Pin Interrupt Signal PICU[x]INTSTAT Digital Output Path PRT[x]SYNC_OUT D+ pin only USBIO_CR1[7] USB or I/O USB SIE Control for USB Mode USBIO_CR1[4,5] Digital System Output PRT[x]BYP Vddd Vddd Vddd Vddd 0 In 1 Drive Logic 5k 1.5k PIN USBIO_CR1[2] USBIO_CR1[3] USBIO_CR1[6] Document Number: 001-53304 Rev. *F D+ 1.5k D+D- 5k Open Drain Page 31 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data if bypass mode is selected. Note that the actual I/O pin voltage is determined by a combination of the selected drive mode and the load at the pin. For example, if a GPIO pin is configured for resistive pull up mode and driven high while the pin is floating, the voltage measured at the pin is a high logic state. If the same GPIO pin is externally tied to ground then the voltage unmeasured at the pin is a low logic state. 6.4.1 Drive Modes Each GPIO and SIO pin is individually configurable into one of the eight drive modes listed in Table 6-6. Three configuration bits are used for each pin (DM[2:0]) and set in the PRTxDM[2:0] registers. Figure 6-11 depicts a simplified pin view based on each of the eight drive modes. Table 6-6 shows the I/O pin’s drive state based on the port data register value or digital array signal Figure 6-11. Drive Mode Vddio DR PS 0. Pin High Impedance Analog DR PS 1. Pin High Impedance Digital DR PS Pin 4. Open Drain, Drives Low DR PS 2. Resistive Pull Up Pin 3. Resistive Pull Down Vddio Pin 5. Open Drain, Drives High DR PS Pin Vddio DR PS Vddio Vddio DR PS DR PS Pin 6. Strong Drive Pin 7. Resistive Pull Up and Down Table 6-6. Drive Modes Diagram Drive Mode PRTxDM2 PRTxDM1 PRTxDM0 PRTxDR = 1 PRTxDR = 0 0 High impedence analog 0 0 0 High-Z High-Z 1 High Impedance digital 0 0 1 High-Z High-Z 2 Resistive pull up 0 1 0 Res High (5K) Strong Low 3 Resistive pull down 0 1 1 Strong High Res Low (5K) 4 Open drain, drives low 1 0 0 High-Z Strong Low 5 Open drain, drive high 1 0 1 Strong High High-Z 6 Strong drive 1 1 0 Strong High Strong Low 7 Resistive pull up and pull down 1 1 1 Res High (5K) Res Low (5K) „ High Impedance Analog The default reset state with both the output driver and digital input buffer turned off. This prevents any current from flowing in the I/O’s digital input buffer due to a floating voltage. This state is recommended for pins that are floating or that support an analog voltage. High impedance analog pins do not provide digital input functionality. Document Number: 001-53304 Rev. *F To achieve the lowest chip current in sleep modes, all I/Os must either be configured to the high impedance analog mode, or have their pins driven to a power supply rail by the PSoC device or by external circuitry. „ High Impedance Digital The input buffer is enabled for digital signal input. This is the standard high impedance (HiZ) state recommended for digital inputs. Page 32 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data „ Resistive Pull Up or Resistive Pull Down Resistive pull up or pull down, respectively, provides a series resistance in one of the data states and strong drive in the other. Pins can be used for digital input and output in these modes. Interfacing to mechanical switches is a common application for these modes. „ Open Drain, Drives High and Open Drain, Drives Low Open drain modes provide high impedance in one of the data states and strong drive in the other. Pins can be used for digital input and output in these modes. A common application for these modes is driving the I2C bus signal lines. „ Strong Drive Provides a strong CMOS output drive in either high or low state. This is the standard output mode for pins. Strong Drive mode pins must not be used as inputs under normal circumstances. This mode is often used to drive digital output signals or external FETs. „ Resistive Pull Up and Pull Down Similar to the resistive pull up and resistive pull down modes except the pin is always in series with a resistor. The high data state is pull up while the low data state is pull down. This mode is most often used when other signals that may cause shorts can drive the bus. 6.4.2 Pin Registers Registers to configure and interact with pins come in two forms that may be used interchangeably. All I/O registers are available in the standard port form, where each bit of the register corresponds to one of the port pins. This register form is efficient for quickly reconfiguring multiple port pins at the same time. I/O registers are also available in pin form, which combines the eight most commonly used port register bits into a single register for each pin. This enables very fast configuration changes to individual pins with a single register write. 6.4.3 Bidirectional Mode High speed bidirectional capability allows pins to provide both the high impedance digital drive mode for input signals and a second user selected drive mode such as strong drive (set using PRTxDM[2:0] registers) for output signals on the same pin, based on the state of an auxiliary control bus signal. The bidirectional capability is useful for processor busses and communications interfaces such as the SPI Slave MISO pin that requires dynamic hardware control of the output buffer. The auxiliary control bus routes up to 16 UDB or digital peripheral generated output enable signals to one or more pins. 6.4.4 Slew Rate Limited Mode GPIO and SIO pins have fast and slow output slew rate options for strong and open drain drive modes, not resistive drive modes. Because it results in reduced EMI, the slow edge rate option is recommended for signals that are not speed critical, generally less than 1 MHz. The fast slew rate is for signals between 1 MHz and 33 MHz. The slew rate is individually configurable for each pin, and is set by the PRTxSLW registers. Document Number: 001-53304 Rev. *F 6.4.5 Pin Interrupts All GPIO and SIO pins are able to generate interrupts to the system. All eight pins in each port interface to their own Port Interrupt Control Unit (PICU) and associated interrupt vector. Each pin of the port is independently configurable to detect rising edge, falling edge, both edge interrupts, or to not generate an interrupt. Depending on the configured mode for each pin, each time an interrupt event occurs on a pin, its corresponding status bit of the interrupt status register is set to “1” and an interrupt request is sent to the interrupt controller. Each PICU has its own interrupt vector in the interrupt controller and the pin status register providing easy determination of the interrupt source down to the pin level. Port pin interrupts remain active in all sleep modes allowing the PSoC device to wake from an externally generated interrupt. While level sensitive interrupts are not directly supported; Universal Digital Blocks (UDB) provide this functionality to the system when needed. 6.4.6 Input Buffer Mode GPIO and SIO input buffers can be configured at the port level for the default CMOS input thresholds or the optional LVTTL input thresholds. All input buffers incorporate Schmitt triggers for input hysteresis. Additionally, individual pin input buffers can be disabled in any drive mode. 6.4.7 I/O Power Supplies Up to four I/O pin power supplies are provided depending on the device and package. Each I/O supply must be less than or equal to the voltage on the chip’s analog (Vdda) pin. This feature allows users to provide different I/O voltage levels for different pins on the device. Refer to the specific device package pinout to determine Vddio capability for a given port and pin. The SIO port pins support an additional regulated high output capability, as described in Adjustable Output Level. 6.4.8 Analog Connections These connections apply only to GPIO pins. All GPIO pins may be used as analog inputs or outputs. The analog voltage present on the pin must not exceed the Vddio supply voltage to which the GPIO belongs. Each GPIO may connect to one of the analog global busses or to one of the analog mux buses to connect any pin to any internal analog resource such as ADC or comparators. In addition, select pins provide direct connections to specific analog features such as the high current DACs or uncommitted opamps. 6.4.9 CapSense This section applies only to GPIO pins. All GPIO pins may be used to create CapSense buttons and sliders[4]. See the “CapSense” section on page 56 for more information. 6.4.10 LCD Segment Drive This section applies only to GPIO pins. All GPIO pins may be used to generate Segment and Common drive signals for direct glass drive of LCD glass. See the “LCD Direct Drive” section on page 55 for details. Page 33 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data 6.4.11 Adjustable Output Level This section applies only to SIO pins. SIO port pins support the ability to provide a regulated high output level for interface to external signals that are lower in voltage than the SIO’s respective Vddio. SIO pins are individually configurable to output either the standard Vddio level or the regulated output, which is based on an internally generated reference. Typically a voltage DAC (VDAC) is used to generate the reference. The “DAC” section on page 56 has more details on VDAC use and reference routing to the SIO pins. 6.4.12 Adjustable Input Level This section applies only to SIO pins. SIO pins by default support the standard CMOS and LVTTL input levels but also support a differential mode with programmable levels. SIO pins are grouped into pairs. Each pair shares a reference generator block which, is used to set the digital input buffer reference level for interface to external signals that differ in voltage from Vddio. The reference sets the pins voltage threshold for a high logic level. Available input thresholds are: „ 0.5 × Vddio „ 0.4 × Vddio „ 0.5 × Vref „ Vref Typically a voltage DAC (VDAC) generates the Vref reference. “DAC” section on page 56 has more details on VDAC use and reference routing to the SIO pins. 6.4.13 SIO as Comparator This section applies only to SIO pins. The adjustable input level feature of the SIOs as explained in the Adjustable Input Level section can be used to construct a comparator. The threshold for the comparator is provided by the SIO's reference generator. The reference generator has the option to set the analog signal routed through the analog global line as threshold for the comparator. Note that a pair of SIO pins share the same threshold. The digital input path in Figure 6-9 on page 31 illustrates this functionality. In the figure, ‘Reference level’ is the analog signal routed through the analog global. The hysteresis feature can also be enabled for the input buffer of the SIO, which increases noise immunity for the comparator. 6.4.14 Hot Swap This section applies only to SIO pins. SIO pins support ‘hot swap’ capability to plug into an application without loading the signals that are connected to the SIO pins even when no power is applied to the PSoC device. This allows the unpowered PSoC to maintain a high impedance load to the external device while also preventing the PSoC from being powered through a GPIO pin’s protection diode. 6.4.15 Over Voltage Tolerance All I/O pins provide an over voltage tolerance feature at any operating Vdd. „ There are no current limitations for the SIO pins as they present a „ The GPIO pins must be limited to 100 µA using a current limiting resistor. GPIO pins clamp the pin voltage to approximately one diode above the Vddio supply where Vddio < Vin < Vdda. „ In case of a GPIO pin configured for analog input/output, the analog voltage on the pin must not exceed the Vddio supply voltage to which the GPIO belongs. A common application for this feature is connection to a bus such as I2C where different devices are running from different supply voltages. In the I2C case, the PSoC chip is configured into the Open Drain, Drives Low mode for the SIO pin. This allows an external pull up to pull the I2C bus voltage above the PSoC pin supply. For example, the PSoC chip could operate at 1.8V, and an external device could run from 5V. Note that the SIO pin’s Vih and Vil levels are determined by the associated Vddio supply pin. The I/O pin must be configured into a high impedance drive mode, open drain low drive mode, or pull down drive mode, for over voltage tolerance to work properly. Absolute maximum ratings for the device must be observed for all I/O pins. 6.4.16 Reset Configuration While reset is active all I/Os are reset to and held in the High Impedance Analog state. After reset is released, the state can be reprogrammed on a port-by-port basis to pull down or pull up. To ensure correct reset operation, the port reset configuration data is stored in special nonvolatile registers. The stored reset data is automatically transferred to the port reset configuration registers at reset release. 6.4.17 Low Power Functionality In all low power modes the I/O pins retain their state until the part is awakened and changed or reset. To awaken the part, use a pin interrupt, because the port interrupt logic continues to function in all low power modes. 6.4.18 Special Pin Functionality Some pins on the device include additional special functionality in addition to their GPIO or SIO functionality. The specific special function pins are listed in Pinouts on page 5. The special features are: „ Digital 4 to 33 MHz crystal oscillator 32.768 kHz crystal oscillator 2 ‡ Wake from sleep on I C address match. Any pin can be used for I2C if wake from sleep is not required. ‡ JTAG interface pins ‡ SWD interface pins ‡ SWV interface pins ‡ External reset ‡ ‡ „ Analog Opamp inputs and outputs High current IDAC outputs ‡ External reference inputs ‡ ‡ 6.4.19 JTAG Boundary Scan The device supports standard JTAG boundary scan chains on all I/O pins for board level test. high impedance load to the external circuit where Vddio < Vin < 5.5V. Document Number: 001-53304 Rev. *F Page 34 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data 7. Digital Subsystem 7.1 Example Peripherals The digital programmable system creates application specific combinations of both standard and advanced digital peripherals and custom logic functions. These peripherals and logic are then interconnected to each other and to any pin on the device, providing a high level of design flexibility and IP security. The features of the digital programmable system are outlined here to provide an overview of capabilities and architecture. Designers do not need to interact directly with the programmable digital system at the hardware and register level. PSoC Creator provides a high level schematic capture graphical interface to automatically place and route resources similar to PLDs. The main components of the digital programmable system are: „ Universal Digital Blocks (UDB) - These form the core function- ality of the digital programmable system. UDBs are a collection of uncommitted logic (PLD) and structural logic (Datapath) optimized to create all common embedded peripherals and customized functionality that are application or design specific. „ Universal Digital Block Array - UDB blocks are arrayed within a matrix of programmable interconnect. The UDB array structure is homogeneous and allows for flexible mapping of digital functions onto the array. The array supports extensive and flexible routing interconnects between UDBs and the Digital System Interconnect. „ Digital System Interconnect (DSI) - Digital signals from Universal Digital Blocks (UDBs), fixed function peripherals, I/O pins, interrupts, DMA, and other system core signals are attached to the Digital System Interconnect to implement full featured device connectivity. The DSI allows any digital function to any pin or other feature routability when used with the Universal Digital Block Array. Figure 7-1. CY8C34 Digital Programmable Architecture The flexibility of the CY8C34 family’s Universal Digital Blocks (UDBs) and Analog Blocks allow the user to create a wide range of components (peripherals). The most common peripherals were built and characterized by Cypress and are shown in the PSoC Creator component catalog, however, users may also create their own custom components using PSoC Creator. Using PSoC Creator, users may also create their own components for reuse within their organization, for example sensor interfaces, proprietary algorithms, and display interfaces. The number of components available through PSoC Creator is too numerous to list in the data sheet, and the list is always growing. An example of a component available for use in CY8C34 family, but, not explicitly called out in this data sheet is the UART component. 7.1.1 Example Digital Components The following is a sample of the digital components available in PSoC Creator for the CY8C34 family. The exact amount of hardware resources (UDBs, routing, RAM, flash) used by a component varies with the features selected in PSoC Creator for the component. „ Communications I2C UART ‡ SPI ‡ ‡ „ Functions EMIF PWMs ‡ Timers ‡ Counters ‡ ‡ „ Logic NOT OR ‡ XOR ‡ AND ‡ ‡ UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB The following is a sample of the analog components available in PSoC Creator for the CY8C34 family. The exact amount of hardware resources (SC/CT blocks, routing, RAM, flash) used by a component varies with the features selected in PSoC Creator for the component. „ Amplifiers UDB Array UDB Array DSI Routing Interface UDB 7.1.2 Example Analog Components IO Port IO Port Digital Core System and Fixed Function Peripherals TIA PGA ‡ opamp ‡ ‡ ‡ DSI Routing Interface Digital Core System and Fixed Function Peripherals IO Port IO Port „ ADC Delta-Sigma „ DACs Current Voltage ‡ PWM ‡ ‡ „ Comparators „ Mixers Document Number: 001-53304 Rev. *F Page 35 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data 7.1.3 Example System Function Components The following is a sample of the system function components available in PSoC Creator for the CY8C34 family. The exact amount of hardware resources (UDBs, SC/CT blocks, routing, RAM, flash) used by a component varies with the features selected in PSoC Creator for the component. „ CapSense „ LCD Drive „ LCD Control 7.1.4 Designing with PSoC Creator 7.1.4.1 More Than a Typical IDE A successful design tool allows for the rapid development and deployment of both simple and complex designs. It reduces or eliminates any learning curve. It makes the integration of a new design into the production stream straightforward. PSoC Creator is that design tool. PSoC Creator is a full featured Integrated Development Environment (IDE) for hardware and software design. It is optimized specifically for PSoC devices and combines a modern, powerful software development platform with a sophisticated graphical design tool. This unique combination of tools makes Document Number: 001-53304 Rev. *F PSoC Creator the most flexible embedded design platform available. Graphical design entry simplifies the task of configuring a particular part. You can select the required functionality from an extensive catalog of components and place it in your design. All components are parameterized and have an editor dialog that allows you to tailor functionality to your needs. PSoC Creator automatically configures clocks and routes the I/O to the selected pins and then generates APIs to give the application complete control over the hardware. Changing the PSoC device configuration is as simple as adding a new component, setting its parameters, and rebuilding the project. At any stage of development you are free to change the hardware configuration and even the target processor. To retarget your application (hardware and software) to new devices, even from 8- to 32-bit families, just select the new device and rebuild. You also have the ability to change the C compiler and evaluate an alternative. Components are designed for portability and are validated against all devices, from all families, and against all supported tool chains. Switching compilers is as easy as editing the from the project options and rebuilding the application with no errors from the generated APIs or boot code. Page 36 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data Figure 7-2. PSoC Creator Framework Document Number: 001-53304 Rev. *F Page 37 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data 7.1.4.2 Component Catalog 7.1.4.4 Software Development Figure 7-3. Component Catalog Figure 7-4. Code Editor Anchoring the tool is a modern, highly customizable user interface. It includes project management and integrated editors for C and assembler source code, as well the design entry tools. The component catalog is a repository of reusable design elements that select device functionality and customize your PSoC device. It is populated with an impressive selection of content; from simple primitives such as logic gates and device registers, through the digital timers, counters and PWMs, plus analog components such as ADC, DACs, and filters, and communication protocols, such as I2C, USB, and CAN. See Example Peripherals on page 35 for more details about available peripherals. All content is fully characterized and carefully documented in datasheets with code examples, AC/DC specifications, and user code ready APIs. Project build control leverages compiler technology from top commercial vendors such as ARM® Limited, Keil™, and CodeSourcery (GNU). Free versions of Keil C51 and GNU C Compiler (GCC) for ARM, with no restrictions on code size or end product distribution, are included with the tool distribution. Upgrading to more optimizing compilers is a snap with support for the professional Keil C51 product and ARM RealView™ compiler. 7.1.4.5 Nonintrusive Debugging Figure 7-5. PSoC Creator Debugger 7.1.4.3 Design Reuse The symbol editor gives you the ability to develop reusable components that can significantly reduce future design time. Just draw a symbol and associate that symbol with your proven design. PSoC Creator allows for the placement of the new symbol anywhere in the component catalog along with the content provided by Cypress. You can then reuse your content as many times as you want, and in any number of projects, without ever having to revisit the details of the implementation. With JTAG (4-wire) and SWD (2-wire) debug connectivity available on all devices, the PSoC Creator debugger offers full control over the target device with minimum intrusion. Breakpoints and code execution commands are all readily available from toolbar buttons and an impressive lineup of windows—register, locals, watch, call stack, memory and peripherals—make for an unparalleled level of visibility into the system. Document Number: 001-53304 Rev. *F Page 38 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data PSoC Creator contains all the tools necessary to complete a design, and then to maintain and extend that design for years to come. All steps of the design flow are carefully integrated and optimized for ease-of-use and to maximize productivity. 7.2 Universal Digital Block The Universal Digital Block (UDB) represents an evolutionary step to the next generation of PSoC embedded digital peripheral functionality. The architecture in first generation PSoC digital blocks provides coarse programmability in which a few fixed functions with a small number of options are available. The new UDB architecture is the optimal balance between configuration granularity and efficient implementation. A cornerstone of this approach is to provide the ability to customize the devices digital operation to match application requirements. „ Status and Control Module - The primary role of this block is to provide a way for CPU firmware to interact and synchronize with UDB operation. „ Clock and Reset Module - This block provides the UDB clocks and reset selection and control. 7.2.1 PLD Module The primary purpose of the PLD blocks is to implement logic expressions, state machines, sequencers, look up tables, and decoders. In the simplest use model, consider the PLD blocks as a standalone resource onto which general purpose RTL is synthesized and mapped. The more common and efficient use model is to create digital functions from a combination of PLD and datapath blocks, where the PLD implements only the random logic and state portion of the function while the datapath (ALU) implements the more structured elements. Figure 7-7. PLD 12C4 Structure PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 To achieve this, UDBs consist of a combination of uncommitted logic (PLD), structured logic (Datapath), and a flexible routing scheme to provide interconnect between these elements, I/O connections, and other peripherals. UDB functionality ranges from simple self contained functions that are implemented in one UDB, or even a portion of a UDB (unused resources are available for other functions), to more complex functions that require multiple UDBs. Examples of basic functions are timers, counters, CRC generators, PWMs, dead band generators, and communications functions, such as UARTs, SPI, and I2C. Also, the PLD blocks and connectivity provide full featured general purpose programmable logic within the limits of the available resources. also contains input/output FIFOs, which are the primary parallel data interface between the CPU/DMA system and the UDB. IN0 TC TC TC TC TC TC TC TC IN1 TC TC TC TC TC TC TC TC IN2 TC TC TC TC TC TC TC TC IN3 TC TC TC TC TC TC TC TC IN4 TC TC TC TC TC TC TC TC IN5 TC TC TC TC TC TC TC TC IN6 TC TC TC TC TC TC TC TC IN7 TC TC TC TC TC TC TC TC IN8 TC TC TC TC TC TC TC TC IN9 TC TC TC TC TC TC TC TC IN10 TC TC TC TC TC TC TC TC IN11 TC TC TC TC TC TC TC TC Figure 7-6. UDB Block Diagram PLD Chaining Clock and Reset Control PLD 12C4 (8 PTs) PLD 12C4 (8 PTs) Status and Control Datapath Datapath Chaining SELIN (carry in) OUT0 MC0 T T T T T T T T OUT1 MC1 T T T T T T T T OUT2 MC2 T T T T T T T T OUT3 MC3 T T T T T T T T SELOUT (carry out) Routing Channel The main component blocks of the UDB are: „ PLD blocks - There are two small PLDs per UDB. These blocks take inputs from the routing array and form registered or combinational sum-of-products logic. PLDs are used to implement state machines, state bits, and combinational logic equations. PLD configuration is automatically generated from graphical primitives. „ Datapath Module - This 8-bit wide datapath contains structured logic to implement a dynamically configurable ALU, a variety of compare configurations and condition generation. This block Document Number: 001-53304 Rev. *F AND Array OR Array One 12C4 PLD block is shown in Figure 7-7. This PLD has 12 inputs, which feed across eight product terms. Each product term (AND function) can be from 1 to 12 inputs wide, and in a given product term, the true (T) or complement (C) of each input can be selected. The product terms are summed (OR function) to create the PLD outputs. A sum can be from 1 to 8 product terms wide. The 'C' in 12C4 indicates that the width of the OR gate (in this case 8) is constant across all outputs (rather than variable as in a 22V10 device). This PLA like structure gives maximum flexibility and insures that all inputs and outputs are permutable for ease of allocation by the software tools. There are two 12C4 PLDs in each UDB. Page 39 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data optimized to implement embedded functions, such as timers, counters, integrators, PWMs, PRS, CRC, shifters and dead band generators and many others. 7.2.2 Datapath Module The datapath contains an 8-bit single cycle ALU, with associated compare and condition generation logic. This datapath block is Figure 7-8. Datapath Top Level PHUB System Bus R/W Access to All Registers F1 FIFOs F0 A0 A1 D0 D1 D1 Data Registers D0 To/From Previous Datapath A1 Conditions: 2 Compares, 2 Zero Detect, 2 Ones Detect Overflow Detect Datapath Control 6 Control Store RAM 8 Word X 16 Bit Input from Programmable Routing Input Muxes Chaining Output Muxes 6 Output to Programmable Routing To/From Next Datapath Accumulators A0 PI Parallel Input/Output (to/from Programmable Routing) PO ALU Shift Mask 7.2.2.1 Working Registers 7.2.2.2 Dynamic Datapath Configuration RAM The datapath contains six primary working registers, which are accessed by CPU firmware or DMA during normal operation. Dynamic configuration is the ability to change the datapath function and internal configuration on a cycle-by-cycle basis, under sequencer control. This is implemented using the 8-word x 16-bit configuration RAM, which stores eight unique 16-bit wide configurations. The address input to this RAM controls the sequence, and can be routed from any block connected to the UDB routing matrix, most typically PLD logic, I/O pins, or from the outputs of this or other datapath blocks. Table 7-1. Working Datapath Registers Name Function Description A0 and A1 Accumulators These are sources and sinks for the ALU and also sources for the compares. D0 and D1 Data Registers These are sources for the ALU and sources for the compares. F0 and F1 FIFOs These are the primary interface to the system bus. They can be a data source for the data registers and accumulators or they can capture data from the accumulators or ALU. Each FIFO is four bytes deep. Document Number: 001-53304 Rev. *F ALU The ALU performs eight general purpose functions. They are: „ Increment „ Decrement „ Add „ Subtract „ Logical AND Page 40 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data „ Logical OR „ Logical XOR Figure 7-9. Example FIFO Configurations System Bus System Bus „ Pass, used to pass a value through the ALU to the shift register, mask, or another UDB register Independent of the ALU operation, these functions are available: F0 F0 F1 D0 A0 D1 A1 „ Shift left „ Shift right „ Nibble swap D0/D1 A0/A1/ALU A0/A1/ALU A0/A1/ALU F1 F0 F1 „ Bitwise OR mask 7.2.2.3 Conditionals Each datapath has two compares, with bit masking options. Compare operands include the two accumulators and the two data registers in a variety of configurations. Other conditions include zero detect, all ones detect, and overflow. These conditions are the primary datapath outputs, a selection of which can be driven out to the UDB routing matrix. Conditional computation can use the built in chaining to neighboring UDBs to operate on wider data widths without the need to use routing resources. 7.2.2.4 Variable MSB The most significant bit of an arithmetic and shift function can be programmatically specified. This supports variable width CRC and PRS functions, and in conjunction with ALU output masking, can implement arbitrary width timers, counters and shift blocks. 7.2.2.5 Built in CRC/PRS The datapath has built in support for single cycle Cyclic Redundancy Check (CRC) computation and Pseudo Random Sequence (PRS) generation of arbitrary width and arbitrary polynomial. CRC/PRS functions longer than 8 bits may be implemented in conjunction with PLD logic, or built in chaining may be use to extend the function into neighboring UDBs. 7.2.2.6 Input/Output FIFOs Each datapath contains two four-byte deep FIFOs, which can be independently configured as an input buffer (system bus writes to the FIFO, datapath internal reads the FIFO), or an output buffer (datapath internal writes to the FIFO, the system bus reads from the FIFO). The FIFOs generate status that are selectable as datapath outputs and can therefore be driven to the routing, to interact with sequencers, interrupts, or DMA. System Bus System Bus TX/RX Dual Capture Dual Buffer 7.2.2.7 Chaining The datapath can be configured to chain conditions and signals such as carries and shift data with neighboring datapaths to create higher precision arithmetic, shift, CRC/PRS functions. 7.2.2.8 Time Multiplexing In applications that are over sampled, or do not need high clock rates, the single ALU block in the datapath can be efficiently shared with two sets of registers and condition generators. Carry and shift out data from the ALU are registered and can be selected as inputs in subsequent cycles. This provides support for 16-bit functions in one (8-bit) datapath. 7.2.2.9 Datapath I/O There are six inputs and six outputs that connect the datapath to the routing matrix. Inputs from the routing provide the configuration for the datapath operation to perform in each cycle, and the serial data inputs. Inputs can be routed from other UDB blocks, other device peripherals, device I/O pins, and so on. The outputs to the routing can be selected from the generated conditions, and the serial data outputs. Outputs can be routed to other UDB blocks, device peripherals, interrupt and DMA controller, I/O pins, and so on. 7.2.3 Status and Control Module The primary purpose of this circuitry is to coordinate CPU firmware interaction with internal UDB operation. Figure 7-10. Status and Control Registers System Bus 8-bit Status Register (Read Only) 8-bit Control Register (Write/Read) Routing Channel Document Number: 001-53304 Rev. *F Page 41 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data The bits of the control register, which may be written to by the system bus, are used to drive into the routing matrix, and thus provide firmware with the opportunity to control the state of UDB processing. The status register is read-only and it allows internal UDB state to be read out onto the system bus directly from internal routing. This allows firmware to monitor the state of UDB processing. Each bit of these registers has programmable connections to the routing matrix and routing connections are made depending on the requirements of the application. Figure 7-11. Digital System Interface Structure System Connections HV B UDB HV A UDB HV B UDB HV A UDB 7.2.3.1 Usage Examples As an example of control input, a bit in the control register can be allocated as a function enable bit. There are multiple ways to enable a function. In one method the control bit output would be routed to the clock control block in one or more UDBs and serve as a clock enable for the selected UDB blocks. A status example is a case where a PLD or datapath block generated a condition, such as a “compare true” condition that is captured and latched by the status register and then read (and cleared) by CPU firmware. HV A HV B HV A HV B UDB UDB UDB UDB UDB UDB UDB UDB HV B HV A HV B HV A 7.2.3.2 Clock Generation Each subcomponent block of a UDB including the two PLDs, the datapath, and Status and Control, has a clock selection and control block. This promotes a fine granularity with respect to allocating clocking resources to UDB component blocks and allows unused UDB resources to be used by other functions for maximum system efficiency. 7.3 UDB Array Description Figure 7-11 shows an example of a 16 UDB array. In addition to the array core, there are a DSI routing interfaces at the top and bottom of the array. Other interfaces that are not explicitly shown include the system interfaces for bus and clock distribution. The UDB array includes multiple horizontal and vertical routing channels each comprised of 96 wires. The wire connections to UDBs, at horizontal/vertical intersection and at the DSI interface are highly permutable providing efficient automatic routing in PSoC Creator. Additionally the routing allows wire by wire segmentation along the vertical and horizontal routing to further increase routing flexibility and capability. Document Number: 001-53304 Rev. *F UDB UDB HV A UDB HV B UDB HV A HV B System Connections 7.3.1 UDB Array Programmable Resources Figure 7-12 shows an example of how functions are mapped into a bank of 16 UDBs. The primary programmable resources of the UDB are two PLDs, one datapath and one status/control register. These resources are allocated independently, because they have independently selectable clocks, and therefore unused blocks are allocated to other unrelated functions. An example of this is the 8-bit Timer in the upper left corner of the array. This function only requires one datapath in the UDB, and therefore the PLD resources may be allocated to another function. A function such as a Quadrature Decoder may require more PLD logic than one UDB can supply and in this case can utilize the unused PLD blocks in the 8-bit Timer UDB. Programmable resources in the UDB array are generally homogeneous so functions can be mapped to arbitrary boundaries in the array. Page 42 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data Figure 7-12. Function Mapping Example in a Bank of UDBs 8-Bit Timer UDB Sequencer Quadrature Decoder UDB HV A 16-Bit PWM HV B Timer Counters 16-Bit PYRS UDB Figure 7-13. Digital System Interconnect CAN Interrupt Controller I2C DMA Controller IO Port Pins Global Clocks UDB HV A HV B Digital System Routing I/F UDB UDB UDB 8-Bit Timer Logic UDB 8-Bit SPI I2C Slave UDB ARRAY 12-Bit SPI UDB UDB UDB UDB Digital System Routing I/F HV B HV A HV B HV A Logic UDB UDB UART UDB UDB 12-Bit PWM 7.4 DSI Routing Interface Description The DSI routing interface is a continuation of the horizontal and vertical routing channels at the top and bottom of the UDB array core. It provides general purpose programmable routing between device peripherals, including UDBs, I/Os, analog peripherals, interrupts, DMA and fixed function peripherals. Figure 7-13 illustrates the concept of the digital system interconnect, which connects the UDB array routing matrix with other device peripherals. Any digital core or fixed function peripheral that needs programmable routing is connected to this interface. Global Clocks IO Port Pins EMIF SC/CT Blocks DACs Comparators Interrupt and DMA routing is very flexible in the CY8C34 programmable architecture. In addition to the numerous fixed function peripherals that can generate interrupt requests, any data signal in the UDB array routing can also be used to generate a request. A single peripheral may generate multiple independent interrupt requests simplifying system and firmware design. Figure 7-14 shows the structure of the IDMUX (Interrupt/DMA Multiplexer). Figure 7-14. Interrupt and DMA Processing in the IDMUX Signals in this category include: „ Interrupt requests from all digital peripherals in the system. Del-Sig Interrupt and DMA Processing in IDMUX Fixed Function IRQs 0 „ DMA requests from all digital peripherals in the system. 1 „ Digital peripheral data signals that need flexible routing to I/Os. IRQs „ Digital peripheral data signals that need connections to UDBs. UDB Array 2 Edge Detect „ Connections to the interrupt and DMA controllers. 3 DRQs „ Connection to I/O pins. DMA termout (IRQs) „ Connection to analog system digital signals. 0 Fixed Function DRQs 1 Edge Detect Document Number: 001-53304 Rev. *F Interrupt Controller DMA Controller 2 Page 43 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data 7.4.1 I/O Port Routing There are a total of 20 DSI routes to a typical 8-bit I/O port, 16 for data and four for drive strength control. When an I/O pin is connected to the routing, there are two primary connections available, an input and an output. In conjunction with drive strength control, this can implement a bidirectional I/O pin. A data output signal has the option to be single synchronized (pipelined) and a data input signal has the option to be double synchronized. The synchronization clock is the system clock (see Figure 6-1). Normally all inputs from pins are synchronized as this is required if the CPU interacts with the signal or any signal derived from it. Asynchronous inputs have rare uses. An example of this is a feed through of combinational PLD logic from input pins to output pins. There are four more DSI connections to a given I/O port to implement dynamic output enable control of pins. This connectivity gives a range of options, from fully ganged 8-bits controlled by one signal, to up to four individually controlled pins. The output enable signal is useful for creating tri-state bidirectional pins and buses. Figure 7-17. I/O Pin Output Enable Connectivity 4 IO Control Signal Connections from UDB Array Digital System Interface Figure 7-15. I/O Pin Synchronization Routing DO OE PIN 0 DI OE PIN1 OE PIN2 OE PIN3 OE PIN4 OE PIN5 OE PIN6 OE PIN7 Port i Figure 7-16. I/O Pin Output Connectivity 7.5 CAN 8 IO Data Output Connections from the UDB Array Digital System Interface DO PIN 0 DO PIN1 DO PIN2 DO PIN3 DO PIN4 DO PIN5 DO PIN6 DO PIN7 The CAN peripheral is a fully functional Controller Area Network (CAN) supporting communication baud rates up to 1 Mbps. The CAN controller implements the CAN2.0A and CAN2.0B specifications as defined in the Bosch specification and conforms to the ISO-11898-1 standard. The CAN protocol was originally designed for automotive applications with a focus on a high level of fault detection. This ensures high communication reliability at a low cost. Because of its success in automotive applications, CAN is used as a standard communication protocol for motion oriented machine control networks (CANOpen) and factory automation applications (DeviceNet). The CAN controller features allow the efficient implementation of higher level protocols without affecting the performance of the microcontroller CPU. Full configuration support is provided in PSoC Creator. Port i Document Number: 001-53304 Rev. *F Page 44 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data Figure 7-18. CAN Bus System Implementation CAN Node 1 CAN Node 2 CAN Node n PSoC CAN Drivers CAN Controller En Tx Rx CAN Transceiver CAN_H CAN_L CAN_H CAN_L CAN_H CAN_L CAN Bus 7.5.1 CAN Features „ CAN2.0A/B protocol implementation - ISO 11898 compliant Standard and extended frames with up to 8 bytes of data per frame ‡ Message filter capabilities ‡ Remote Transmission Request (RTR) support ‡ Programmable bit rate up to 1 Mbps ‡ „ Listen Only mode „ SW readable error counter and indicator „ Sleep mode: Wake the device from sleep with activity on the Rx pin „ Supports two or three wire interface to external transceiver (Tx, Rx, and Enable). The three-wire interface is compatible with the Philips PHY; the PHY is not included on-chip. The three wires can be routed to any I/O „ Enhanced interrupt controller CAN receive and transmit buffers status ‡ CAN controller error status including BusOff ‡ Document Number: 001-53304 Rev. *F „ Receive path 16 receive buffers each with its own message filter Enhanced hardware message filter implementation that covers the ID, IDE and RTR ‡ DeviceNet addressing support ‡ Multiple receive buffers linkable to build a larger receive message array ‡ Automatic transmission request (RTR) response handler ‡ Lost received message notification ‡ ‡ „ Transmit path Eight transmit buffers Programmable transmit priority • Round robin • Fixed priority ‡ Message transmissions abort capability ‡ ‡ 7.5.2 Software Tools Support CAN Controller configuration integrated into PSoC Creator: „ CAN Configuration walkthrough with bit timing analyzer „ Receive filter setup Page 45 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data Figure 7-19. CAN Controller Block Diagram TxMessage0 TxReq TxAbort Tx Buffer Status TxReq Pending TxMessage1 TxReq TxAbort Bit Timing Priority Arbiter TxMessage6 TxReq TxAbort TxInterrupt Request (if enabled) TxMessage7 TxReq TxAbort RxMessage0 Acceptance Code 0 Acceptance Mask 0 RxMessage1 Acceptance Code 1 Acceptance Mask 1 Rx RxMessage Handler RxInterrupt Request (if enabled) RxMessage14 Acceptance Code 14 Acceptance Mask 14 RxMessage15 Acceptance Code 15 Acceptance Mask 15 ErrInterrupt Request (if enabled) Rx CAN Framer „ Dedicated 8-byte buffer for EP0 PSoC includes a dedicated Full-Speed (12 Mbps) USB 2.0 transceiver supporting all four USB transfer types: control, interrupt, bulk, and isochronous. The maximum data payload size is 64 bytes for control, interrupt, and bulk endpoints and 1023 bytes for isochronous. PSoC Creator provides full configuration support. USB interfaces to hosts through two dedicated USBIO pins, which are detailed in the “I/O System and Routing” section on page 29. „ Three memory modes „ Eight unidirectional data endpoints „ One bidirectional control endpoint 0 (EP0) „ Shared 512-byte buffer for the eight data endpoints CRC Check Error Detection CRC Form ACK Bit Stuffing Bit Error Overload Arbitration 7.6 USB USB includes the following features: CRC Generator Error Status Error Active Error Passive Bus Off Tx Error Counter Rx Error Counter RTR RxMessages 0-15 Rx Buffer Status RxMessage Available Tx Tx CAN Framer WakeUp Request Manual Memory Management with No DMA Access Manual Memory Management with Manual DMA Access ‡ Automatic Memory Management with Automatic DMA Access ‡ ‡ „ Internal 3.3V regulator for transceiver „ Internal 48 MHz main oscillator mode that auto locks to USB bus clock, requiring no external crystal for USB (USB equipped parts only) „ Interrupts on bus and each endpoint event, with device wakeup „ USB Reset, Suspend, and Resume operations „ Bus powered and self powered modes Document Number: 001-53304 Rev. *F Page 46 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data „ Free run mode Figure 7-20. USB „ One Shot mode (stop at end of period) Arbiter 512 X 8 SRAM „ Complementary PWM outputs with deadband System Bus „ PWM output kill SIE (Serial Interface Engine) Figure 7-21. Timer/Counter/PWM USB IO D+ D- Interrupts 48 MHz IMO Clock Reset Enable Capture Kill Timer / Counter / PWM 16-bit IRQ TC / Compare! Compare 7.8 I2C 7.7 Timers, Counters, and PWMs The Timer/Counter/PWM peripheral is a 16-bit dedicated peripheral providing three of the most common embedded peripheral features. As almost all embedded systems use some combination of timers, counters, and PWMs. Four of them have been included on this PSoC device family. Additional and more advanced functionality timers, counters, and PWMs can also be instantiated in Universal Digital Blocks (UDBs) as required. PSoC Creator allows designers to choose the timer, counter, and PWM features that they require. The tool set utilizes the most optimal resources available. The Timer/Counter/PWM peripheral can select from multiple clock sources, with input and output signals connected through the DSI routing. DSI routing allows input and output connections to any device pin and any internal digital signal accessible through the DSI. Each of the four instances has a compare output, terminal count output (optional complementary compare output), and programmable interrupt request line. The Timer/Counter/PWMs are configurable as free running, one shot, or Enable input controlled. The peripheral has timer reset and capture inputs, and a kill input for control of the comparator outputs. The peripheral supports full 16-bit capture. Timer/Counter/PWM features include: „ 16-bit Timer/Counter/PWM (down count only) „ Selectable clock source „ PWM comparator (configurable for LT, LTE, EQ, GTE, GT) „ Period reload on start, reset, and terminal count „ Interrupt on terminal count, compare true, or capture „ Dynamic counter reads „ Timer capture mode „ Count while enable signal is asserted mode The I2C peripheral provides a synchronous two wire interface designed to interface the PSoC device with a two wire I2C serial communication bus. The bus is compliant with Philips ‘The I2C Specification’ version 2.1. Additional I2C interfaces can be instantiated using Universal Digital Blocks (UDBs) in PSoC Creator, as required. To eliminate the need for excessive CPU intervention and overhead, I2C specific support is provided for status detection and generation of framing bits. I2C operates as a slave, a master, or multimaster (Slave and Master). In slave mode, the unit always listens for a start condition to begin sending or receiving data. Master mode supplies the ability to generate the Start and Stop conditions and initiate transactions. Multimaster mode provides clock synchronization and arbitration to allow multiple masters on the same bus. If Master mode is enabled and Slave mode is not enabled, the block does not generate interrupts on externally generated Start conditions. I2C interfaces through the DSI routing and allows direct connections to any GPIO or SIO pins. I2C provides hardware address detect of a 7-bit address without CPU intervention. Additionally the device can wake from low power modes on a 7-bit hardware address match. If wakeup functionality is required, I2C pin connections are limited to the two special sets of SIO pins. I2C features include: „ Slave and Master, Transmitter, and Receiver operation „ Byte processing for low CPU overhead „ Interrupt or polling CPU interface „ Support for bus speeds up to 1 Mbps (3.4 Mbps in UDBs) „ 7 or 10-bit addressing (10-bit addressing requires firmware support) „ SMBus operation (through firmware support - SMBus supported in hardware in UDBs) „ 7-bit hardware address compare „ Wake from low power modes on address match Document Number: 001-53304 Rev. *F Page 47 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data „ Four comparators with optional connection to configurable LUT 8. Analog Subsystem outputs. The analog programmable system creates application specific combinations of both standard and advanced analog signal processing blocks. These blocks are then interconnected to each other and also to any pin on the device, providing a high level of design flexibility and IP security. The features of the analog subsystem are outlined here to provide an overview of capabilities and architecture. „ Flexible, configurable analog routing architecture provided by „ Two configurable switched capacitor/continuous time (SC/CT) blocks for functions that include opamp, unity gain buffer, programmable gain amplifier, transimpedance amplifier, and mixer. „ Two opamps for internal use and connection to GPIO that can be used as high current output buffers. „ CapSense subsystem to enable capacitive touch sensing. analog globals, analog mux bus, and analog local buses. „ Precision reference for generating an accurate analog voltage „ High resolution Delta-Sigma ADC. for internal analog blocks. „ Two 8-bit DACs that provide either voltage or current output. Figure 8-1. Analog Subsystem Block Diagram DAC SC/CT Block SC /CT Block Op Amp R O U T I N G A N A L O G Precision Reference DAC Op Amp GPIO Port DelSig ADC A N A L O G R O U T I N G Com parators CM P CM P CM P G PIO Port CM P CapSense Subsystem Analog Interface DSI Array Clock Distribution The PSoC Creator software program provides a user friendly interface to configure the analog connections between the GPIO and various analog resources and connections from one analog resource to another. PSoC Creator also provides component libraries that allow you to configure the various analog blocks to Document Number: 001-53304 Rev. *F Config & Status Registers PHUB CPU Decim ator perform application specific functions (PGA, transimpedance amplifier, voltage DAC, current DAC, and so on). The tool also generates API interface libraries that allow you to write firmware that allows the communication between the analog peripheral and CPU/Memory. Page 48 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data 8.1 Analog Routing 8.1.2 Functional Description The CY8C34 family of devices has a flexible analog routing architecture that provides the capability to connect GPIOs and different analog blocks, and also route signals between different analog blocks. One of the strong points of this flexible routing architecture is that it allows dynamic routing of input and output connections to the different analog blocks. Analog globals (AGs) and analog mux buses (AMUXBUS) provide analog connectivity between GPIOs and the various analog blocks. There are 16 AGs in the CY8C34 family. The analog routing architecture is divided into four quadrants as shown in Figure 8-2. Each quadrant has four analog globals (AGL[0..3], AGL[4..7], AGR[0..3], AGR[4..7]). Each GPIO is connected to the corresponding AG through an analog switch. The analog mux bus is a shared routing resource that connects to every GPIO through an analog switch. There are two AMUXBUS routes in CY8C34, one in the left half (AMUXBUSL) and one in the right half (AMUXBUSR), as shown in Figure 8-2. 8.1.1 Features „ Flexible, configurable analog routing architecture „ 16 Analog globals (AG) and two analog mux buses (AMUXBUS) to connect GPIOs and the analog blocks „ Each GPIO is connected to one analog global and one analog mux bus „ 8 Analog local buses (abus) to route signals between the different analog blocks „ Multiplexers and switches for input and output selection of the analog blocks Document Number: 001-53304 Rev. *F Page 49 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data Figure 8-2. CY8C34 Analog Interconnect Vssd Vcca * * Vssa Vdda * * AGL[6] AGL[7] AGL[5] swinn * COMPARATOR 90 comp3 out ref in SC/CT AGR[5] Vssa sc1 Vin Vref out sc1_bgref (1.024V) AGR[4] AMUXBUSR refbuf_vref1 (1.024V) refbuf_vref2 (1.2V) refsel[1:0] AGR[6] refbufr sc0 Vin Vref out vssa sc0_bgref (1.024V) v0 DAC0 i0 USB IO v2 DAC2 i2 USB IO * P15[6] 36 GPIO P5[7] GPIO P5[6] GPIO P5[5] GPIO P5[4] SIO P12[7] SIO P12[6] GPIO * P1[7] GPIO * P1[6] dac_vref (0.256V) vpwra vpwra/2 dsm0_vcm_vref1 (0.8V) dsm0_vcm_vref2 (0.7V) + DSM0 - dsm0_qtz_vref2 (1.2V) dsm0_qtz_vref1 (1.024V) Vdda Vdda/4 en_resvda vssa DSM vcm refs qtz_ref vref_vss_ext 28 ExVrefL refmux[2:0] ExVrefR CY8C55 only 01 23 456 7 0123 3210 76543210 Vssd XRES Vbat Ind Vboost * * Vssb * * * Document Number: 001-53304 Rev. *F Notes: * Denotes pins on all packages LCD signals are not shown. AMUXBUSR AGR[0] Vddio1 * Large ( ~200 Ohms) * * Switch Resistance Small ( ~870 Ohms ) * * GPIO P2[5] GPIO P2[6] GPIO P2[7] SIO P12[4] SIO P12[5] GPIO P6[4] GPIO P6[5] GPIO P6[6] GPIO P6[7] * GPIO P5[0] GPIO P5[1] GPIO P5[2] GPIO P5[3] GPIO P1[0] GPIO P1[1] GPIO P1[2] GPIO P1[3] GPIO P1[4] GPIO P1[5] * Connection * AGR[1] AGR[3] AGR[2] AGR[1] AGR[0] AMUXBUSR AGL[3] AGL[2] AGL[1] AGL[0] AMUXBUSL 13 Mux Group Switch Group AGR[2] AGR[3] LPF * AGL[1] AGL[2] AGL[3] VBE Vss ref * TS ADC : AMUXBUSR ANALOG ANALOG BUS GLOBALS * AMUXBUSL AGL[0] ANALOG ANALOG GLOBALS BUS * AMUXBUSL Vssd Vddd * P15[7] VIDAC vcmsel[1:0] en_resvpwra Vccd ABUSR0 ABUSR1 ABUSR2 ABUSR3 ABUSL0 ABUSL1 ABUSL2 ABUSL3 * * Vddd cmp0_vref (1.024V) AGR[7] CAPSENSE out ref in refbufl refsel[1:0] GPIO P6[0] GPIO P6[1] GPIO P6[2] GPIO P6[3] GPIO P15[4] GPIO P15[5] GPIO P2[0] GPIO P2[1] GPIO P2[2] GPIO P2[3] * GPIO P2[4] * + - bg_vda_swabusl0 refbuf_vref1 (1.024V) refbuf_vref2 (1.2V) Vssd ExVrefR comp1 + - cmp1_vref Vdda Vdda/2 Vccd swout swin refbufr_ cmp refbufl_ cmp out1 + - comp2 cmp_muxvn[1:0] vref_cmp1 (0.256V) bg_vda_res_en in1 5 comp0 + cmp1_vref cmp0_vref (1.024V) LPF out0 swin i2 * GPIO P4[2] GPIO P4[3] GPIO P4[4] GPIO P4[5] GPIO P4[6] GPIO P4[7] Vddio2 in0 swout abuf_vref_int (1.024V) cmp1_vref i0 * * * AGL[4] GPIO P3[5] GPIO P3[4] GPIO P3[3] GPIO P3[2] GPIO P3[1] GPIO P3[0] GPXT * P15[1] GPXT * P15[0] 3210 76543210 swfol swfol * * AMUXBUSL 44 01 2 3 4 56 7 0123 * * * * opamp2 * ExVrefL2 opamp0 * GPIO P0[4] GPIO P0[5] GPIO P0[6] GPIO P0[7] AGR[6] AGR[7] AGL[7] ExVrefL ExVrefL1 * AGR[4] AGR[5] AGL[4] AGL[5] AGL[6] swinp * * AMUXBUSR AMUXBUSL * swinp Vddio3 GPIO P3[6] GPIO P3[7] SIO P12[0] SIO P12[1] GPIO P15[2] GPIO P15[3] SIO P12[2] SIO P12[3] GPIO P4[0] GPIO P4[1] GPIO P0[0] GPIO P0[1] GPIO P0[2] GPIO P0[3] Vddio0 swinn Rev #51 2-April-2010 Page 50 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data Analog local buses (abus) are routing resources located within the analog subsystem and are used to route signals between different analog blocks. There are eight abus routes in CY8C34, four in the left half (abusl [0:3]) and four in the right half (abusr [0:3]) as shown in Figure 8-2. Using the abus saves the analog globals and analog mux buses from being used for interconnecting the analog blocks. control register or an assertion of the Start Of Conversion (SOC) signal. When the conversion is complete, a status bit is set and the output signal End Of Conversion (EOC) asserts high and remains high until the value is read by either the DMA controller or the CPU. Multiplexers and switches exist on the various buses to direct signals into and out of the analog blocks. A multiplexer can have only one connection on at a time, whereas a switch can have multiple connections on simultaneously. In Figure 8-2, multiplexers are indicated by grayed ovals and switches are indicated by transparent ovals. In Single Sample mode, the ADC performs one sample conversion on a trigger. In this mode, the ADC stays in standby state waiting for the SOC signal to be asserted. When SOC is signaled the ADC performs one sample conversion and captures the result. To detect the end of conversion, the system may poll a control register for status or configure the external EOC signal to generate an interrupt or invoke a DMA request. When the transfer is done the ADC reenters the standby state where it stays until another SOC event. 8.2 Delta-Sigma ADC The CY8C34 device contains one Delta Sigma ADC. This ADC offers differential input, high resolution and excellent linearity, making it a good ADC choice for both audio signal processing and measurement applications. The converter's nominal operation is 12 bits at 192 ksps. 8.2.1 Functional Description The ADC connects and configures three basic components, input buffer, delta-sigma modulator, and decimator. The basic block diagram is shown in Table 8-3. The input buffer is connected to the internal and external buses input muxes. The signal from the input muxes is delivered to the delta-sigma modulator either directly or through the input buffer. The delta-sigma modulator performs the actual analog to digital conversion. The modulator over-samples the input and generates a serial data stream output. This high speed data stream is not useful for most applications without some type of post processing, and so is passed to the decimator through the Analog Interface block. The decimator converts the high speed serial data stream into parallel ADC results. Resolution and sample rate are controlled by the Decimator. Data is pipelined in the decimator; the output is a function of the last four samples. When the input multiplexer is switched, the output data is not valid until after the fourth sample after the switch. Figure 8-3. Delta-Sigma ADC Block Diagram Input Buffer Negative Input Mux Delta Sigma Modulator Decimator 12 Bit Resul EOC SOC 8.2.2 Operational Modes The ADC can be configured by the user to operate in one of four modes: Single Sample, Fast Filter, Continuous or Fast Average. All four modes are started by either a write to the start bit in a Document Number: 001-53304 Rev. *F 8.2.2.2 Continuous In continuous mode, the channel resets and then runs continuously until stopped. This mode is used when the input signal is not switched between sources and multiple samples are required. 8.2.2.3 Fast Filter The Fast Filter mode continuously captures signals back-to-back and the ADC channel resets between each sample. Upon completion of conversion of a sample, the next sample is begun immediately. The results can be transferred either using polling, interrupts, or a DMA request. This mode is best used when the input is switched between multiple sources, requiring a filter reset between each sample. 8.2.2.4 Fast FIR (Average) This mode is similar to Fast Filter mode, but does not reset the modulator between intermediate conversions. It is used when decimation ratios greater than 128 are required. This mode uses post processor sinc1 filter to perform additional decimation to obtain resolutions greater than 16. More information on output formats is provided in the Technical Reference Manual. 8.2.3 Start of Conversion Input Positive Input Mux (Analog Routing) 8.2.2.1 Single Sample The Start of Conversion (SOC) signal is used to start an ADC conversion. A digital clock or UDB output can be used to drive this input. In applications where the sampling period must be longer than the conversion time this signal can be used. Also in systems where the ADC needs to be synchronized to other hardware, the SOC input is used. This signal is optional and does not need to be connected if ADC is running in a continuous mode. 8.2.4 End of Conversion Output The End of Conversion (EOC) signal goes high at the end of each ADC conversion. This signal may be used to trigger either an interrupt or DMA request. Page 51 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data „ The positive input of the comparators may be optionally passed 8.3 Comparators through a low pass filter. Two filters are provided The CY8C34 family of devices contains four comparators in a device. Comparators have these features: „ Comparator inputs can be connections to GPIO, DAC outputs and SC block outputs „ Input offset factory trimmed to less than 5 mV 8.3.1 Input and Output Interface „ Rail-to-rail common mode input range (Vssa to Vdda) The positive and negative inputs to the comparators come from the analog global buses, the analog mux line, the analog local bus and precision reference through multiplexers. The output from each comparator could be routed to any of the two input LUTs. The output of that LUT is routed to the UDB Digital System Interface. „ Speed and power can be traded off by using one of three modes: fast, slow, or ultra low power „ Comparator outputs can be routed to look up tables to perform simple logic functions and then can also be routed to digital blocks Figure 8-4. Analog Comparator From Analog Routing From Analog Routing ANAIF + comp0 _ + comp1 _ + comp3 _ + _ From Analog Routing From Analog Routing comp2 4 4 LUT0 4 4 4 LUT1 4 LUT2 4 4 LUT3 UDBs 8.3.2 LUT The CY8C34 family of devices contains four LUTs. The LUT is a two input, one output lookup table that is driven by any one or two of the comparators in the chip. The output of any LUT is routed to the digital system interface of the UDB array. From the digital system interface of the UDB array, these signals can be Document Number: 001-53304 Rev. *F connected to UDBs, DMA controller, I/O, or the interrupt controller. The LUT control word written to a register sets the logic function on the output. The available LUT functions and the associated control word is shown in Table 8-1. Page 52 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data Table 8-1. LUT Function vs. Program Word and Inputs Control Word Output (A and B are LUT inputs) 0000b FALSE (‘0’) 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b Figure 8-6. Opamp Configurations a) Voltage Follower A AND B A AND (NOT B) A (NOT A) AND B B A XOR B A OR B A NOR B A XNOR B NOT B Opamp Vout to Pin Vin b) External Uncommitted Opamp Opamp Vout to GPIO A OR (NOT B) NOT A (NOT A) OR B A NAND B TRUE (‘1’) 8.4 Opamps The CY8C34 family of devices contains two general purpose opamps in a device. Vp to GPIO Vn to GPIO c) Internal Uncommitted Opamp Vn To Internal Signals Figure 8-5. Opamp Opamp Vout to Pin Vp GPIO Pin GPIO Analog Global Bus Analog Global Bus VREF Analog Internal Bus Opamp GPIO = Analog Switch GPIO The opamp has three speed modes, slow, medium, and fast. The slow mode consumes the least amount of quiescent power and the fast mode consumes the most power. The inputs are able to swing rail-to-rail. The output swing is capable of rail-to-rail operation at low current output, within 50 mV of the rails. When driving high current loads (about 25 mA) the output voltage may only get within 500 mV of the rails. 8.5 Programmable SC/CT Blocks The opamp is uncommitted and can be configured as a gain stage or voltage follower, or output buffer on external or internal signals. See Figure 8-6. In any configuration, the input and output signals can all be connected to the internal global signals and monitored with an ADC, or comparator. The configurations are implemented with switches between the signals and GPIO pins. The CY8C34 family of devices contains two switched capacitor/continuous time (SC/CT) blocks in a device. Each switched capacitor/continuous time block is built around a single rail-to-rail high bandwidth opamp. Switched capacitor is a circuit design technique that uses capacitors plus switches instead of resistors to create analog functions. These circuits work by moving charge between capacitors by opening and closing different switches. Nonoverlapping in phase clock signals control the switches, so that not all switches are ON simultaneously. The PSoC Creator tool offers a user friendly interface, which allows you to easily program the SC/CT blocks. Switch control and clock phase control configuration is done by PSoC Creator so users only need to determine the application use parameters such as gain, amplifier polarity, vref connection, and so on. Document Number: 001-53304 Rev. *F Page 53 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data The same opamps and block interfaces are also connectable to an array of resistors which allows the construction of a variety of continuous time functions. The opamp and resistor array is programmable to perform various analog functions including Figure 8-7. PGA Resistor Settings Vin 0 Vref 1 R1 R2 20k to 980k 20k or 40k „ Naked Operational Amplifier - Continuous Mode „ Unity-Gain Buffer - Continuous Mode S „ Programmable Gain Amplifier (PGA) - Continuous Mode Vref 0 „ Transimpedance Amplifier (TIA) - Continuous Mode Vin 1 „ Up/Down Mixer - Continuous Mode „ Sample and Hold Mixer (NRZ S/H) - Switched Cap Mode „ First Order Analog to Digital Modulator - Switched Cap Mode 8.5.1 Naked Opamp The Naked Opamp presents both inputs and the output for connection to internal or external signals. The opamp has a unity gain bandwidth greater than 6.0 MHz and output drive current up to 650 µA. This is sufficient for buffering internal signals (such as DAC outputs) and driving external loads greater than 7.5 kohms. 8.5.2 Unity Gain The Unity Gain buffer is a Naked Opamp with the output directly connected to the inverting input for a gain of 1.00. It has a -3 dB bandwidth greater than 6.0 MHz. 8.5.3 PGA The PGA amplifies an external or internal signal. The PGA can be configured to operate in inverting mode or noninverting mode. The PGA function may be configured for both positive and negative gains as high as 50 and 49 respectively. The gain is adjusted by changing the values of R1 and R2 as illustrated in Figure 8-7. The schematic in Figure 8-7 shows the configuration and possible resistor settings for the PGA. The gain is switched from inverting and non inverting by changing the shared select value of the both the input muxes. The bandwidth for each gain case is listed in Table 8-2. The PGA is used in applications where the input signal may not be large enough to achieve the desired resolution in the ADC, or dynamic range of another SC/CT block such as a mixer. The gain is adjustable at runtime, including changing the gain of the PGA prior to each ADC sample. 8.5.4 TIA The Transimpedance Amplifier (TIA) converts an internal or external current to an output voltage. The TIA uses an internal feedback resistor in a continuous time configuration to convert input current to output voltage. For an input current Iin, the output voltage is Iin x Rfb +Vref, where Vref is the value placed on the non inverting input. The feedback resistor Rfb is programmable between 20 KΩ and 1 MΩ through a configuration register. Table 8-3 shows the possible values of Rfb and associated configuration settings. Table 8-3. Feedback Resistor Settings Configuration Word Nominal Rfb (KΩ) 000b 20 001b 30 010b 40 Table 8-2. Bandwidth Gain Bandwidth 1 6.0 MHz 24 340 kHz 48 220 kHz 50 215 kHz 011b 60 100b 120 101b 250 110b 500 111b 1000 Figure 8-8. Continuous Time TIA Schematic R fb I in V ref Document Number: 001-53304 Rev. *F V out Page 54 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data The TIA configuration is used for applications where an external sensor's output is current as a function of some type of stimulus such as temperature, light, magnetic flux etc. In a common application, the voltage DAC output can be connected to the VREF TIA input to allow calibration of the external sensor bias current by adjusting the voltage DAC output voltage. 8.6 LCD Direct Drive The PSoC Liquid Crystal Display (LCD) driver system is a highly configurable peripheral designed to allow PSoC to directly drive a broad range of LCD glass. All voltages are generated on chip, eliminating the need for external components. With a high multiplex ratio of up to 1/16, the CY8C34 family LCD driver system can drive a maximum of 736 segments. The PSoC LCD driver module was also designed with the conservative power budget of portable devices in mind, enabling different LCD drive modes and power down modes to conserve power. PSoC Creator provides an LCD segment drive component. The component wizard provides easy and flexible configuration of LCD resources. You can specify pins for segments and commons along with other options. The software configures the device to meet the required specifications. This is possible because of the programmability inherent to PSoC devices. Key features of the PSoC LCD segment system are: „ LCD panel direct driving „ Type A (standard) and Type B (low power) waveform support „ Wide operating voltage range support (2V to 5V) for LCD panels „ Static, 1/2, 1/3, 1/4, 1/5 bias voltage levels „ Internal bias voltage generation through internal resistor ladder „ Up to 62 total common and segment outputs „ Up to 1/16 multiplex for a maximum of 16 backplane/common outputs „ Up to 62 front plane/segment outputs for direct drive „ Drives up to 736 total segments (16 backplane x 46 front plane) „ Up to 64 levels of software controlled contrast „ Ability to move display data from memory buffer to LCD driver through DMA (without CPU intervention) „ Adjustable LCD refresh rate from 10 Hz to 150 Hz „ Ability to invert LCD display for negative image „ Three LCD driver drive modes, allowing power optimization Document Number: 001-53304 Rev. *F Figure 8-9. LCD System LCD DAC Global Clock UDB LCD Driver Block DMA PIN Display RAM PHUB 8.6.1 LCD Segment Pin Driver Each GPIO pin contains an LCD driver circuit. The LCD driver buffers the appropriate output of the LCD DAC to directly drive the glass of the LCD. A register setting determines whether the pin is a common or segment. The pin’s LCD driver then selects one of the six bias voltages to drive the I/O pin, as appropriate for the display data. 8.6.2 Display Data Flow The LCD segment driver system reads display data and generates the proper output voltages to the LCD glass to produce the desired image. Display data resides in a memory buffer in the system SRAM. Each time you need to change the common and segment driver voltages, the next set of pixel data moves from the memory buffer into the Port Data Registers via DMA. 8.6.3 UDB and LCD Segment Control A UDB is configured to generate the global LCD control signals and clocking. This set of signals is routed to each LCD pin driver through a set of dedicated LCD global routing channels. In addition to generating the global LCD control signals, the UDB also produces a DMA request to initiate the transfer of the next frame of LCD data. 8.6.4 LCD DAC The LCD DAC generates the contrast control and bias voltage for the LCD system. The LCD DAC produces up to five LCD drive voltages plus ground, based on the selected bias ratio. The bias voltages are driven out to GPIO pins on a dedicated LCD bias bus, as required. Page 55 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data 8.7 CapSense 8.9 DAC The CapSense system provides a versatile and efficient means for measuring capacitance in applications such as touch sense buttons, sliders, proximity detection, etc. The CapSense system uses a configuration of system resources, including a few hardware functions primarily targeted for CapSense. Specific resource usage is detailed in the CapSense component in PSoC Creator. The CY8C34 parts contain two Digital to Analog Convertors (DACs). Each DAC is 8-bit and can be configured for either voltage or current output. The DACs support CapSense, power supply regulation, and waveform generation. Each DAC has the following features: A capacitive sensing method using a Delta-Sigma Modulator (CSD) is used. It provides capacitance sensing using a switched capacitor technique with a delta-sigma modulator to convert the sensing current to a digital code. „ Programmable step size (range selection) 8.8 Temp Sensor „ 8 Msps conversion rate for current output Die temperature is used to establish programming parameters for writing flash. Die temperature is measured using a dedicated sensor based on a forward biased transistor. The temperature sensor has its own auxiliary ADC. „ 1 Msps conversion rate for voltage output „ Adjustable voltage or current output in 255 steps „ Eight bits of calibration to correct ± 25% of gain error „ Source and sink option for current output „ Monotonic in nature Figure 8-10. DAC Block Diagram I source  Range  1x , 8x , 64x  Reference  Source  Scaler   Vout  R    3R     Iout      I sink  Range     1x , 8x , 64x  8.9.1 Current DAC 8.10 Up/Down Mixer The current DAC (IDAC) can be configured for the ranges 0 to 32 µA, 0 to 256 µA, and 0 to 2.048 mA. The IDAC can be configured to source or sink current. In continuous time mode, the SC/CT block components are used to build an up or down mixer. Any mixing application contains an input signal frequency and a local oscillator frequency. The polarity of the clock, Fclk, switches the amplifier between inverting or noninverting gain. The output is the product of the input and the switching function from the local oscillator, with frequency components at the local oscillator plus and minus the signal frequency (Fclk + Fin and Fclk - Fin) and reduced-level frequency components at odd integer multiples of the local oscillator frequency. The local oscillator frequency is provided by the selected clock source for the mixer. 8.9.2 Voltage DAC For the voltage DAC (VDAC), the current DAC output is routed through resistors. The two ranges available for the VDAC are 0 to 1.024V and 0 to 4.096V. In voltage mode any load connected to the output of a DAC should be purely capacitive (the output of the VDAC is not buffered). Continuous time up and down mixing works for applications with input signals and local oscillator frequencies up to 1 MHz. Document Number: 001-53304 Rev. *F Page 56 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data is the output of the comparator and not the integrator in the modulator case. The signal is downshifted and buffered and then processed by a decimator to make a delta-sigma converter or a counter to make an incremental converter. The accuracy of the sampled data from the first-order modulator is determined from several factors. Figure 8-11. Mixer Configuration C2 = 1.7 pF C1 = 850 fF The main application for this modulator is for a low frequency ADC with high accuracy. Applications include strain gauges, thermocouples, precision voltage, and current measurement. Rmix 0 20k or 40k sc_clk Rmix 0 20k or 40k Vin Vout 0 Vref 1 sc_clk 8.11 Sample and Hold The main application for a sample and hold, is to hold a value stable while an ADC is performing a conversion. Some applications require multiple signals to be sampled simultaneously, such as for power calculations (V and I). Figure 8-12. Sample and Hold Topology (Φ1 and Φ2 are opposite phases of a clock) Φ1 Vi C1 C2 Φ1 n Φ1 Φ2 V ref V out Φ2 Φ2 Φ1 Φ2 Φ1 Φ1 V ref Φ2 C3 C4 Φ2 Vref 8.11.1 Down Mixer The SC/CT block can be used as a mixer to down convert an input signal. This circuit is a high bandwidth passive sample network that can sample input signals up to 14 MHz. This sampled value is then held using the opamp with a maximum clock rate of 4 MHz. The output frequency is at the difference between the input frequency and the highest integer multiple of the Local Oscillator that is less than the input. 9. Programming, Debug Interfaces, Resources PSoC devices include extensive support for programming, testing, debugging, and tracing both hardware and firmware. Three interfaces are available: JTAG, SWD, and SWV. JTAG and SWD support all programming and debug features of the device. JTAG also supports standard JTAG scan chains for board level test and chaining multiple JTAG devices to a single JTAG connection. Complete Debug on Chip (DoC) functionality enables full device debugging in the final system using the standard production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the standard programming connections are required to fully support debug. The PSoC Creator IDE software provides fully integrated programming and debug support for PSoC devices. The low cost MiniProg3 programmer and debugger is designed to provide full programming and debug support of PSoC devices in conjunction with the PSoC Creator IDE. PSoC JTAG, SWD, and SWV interfaces are fully compatible with industry standard third party tools. All DOC circuits are disabled by default and can only be enabled in firmware. If not enabled, the only way to reenable them is to erase the entire device, clear flash protection, and reprogram the device with new firmware that enables DOC. Disabling DOC features, robust flash protection, and hiding custom analog and digital functionality inside the PSoC device provide a level of security not possible with multichip application solutions. Additionally, all device interfaces can be permanently disabled (Device Security) for applications concerned about phishing attacks due to a maliciously reprogrammed device. Permanently disabling interfaces is not recommended in most applications because the designer then cannot access the device. Because all programming, debug, and test interfaces are disabled when Device Security is enabled, PSoCs with Device Security enabled may not be returned for failure analysis. Table 9-1. Debug Configurations Debug and Trace Configuration All debug and trace disabled GPIO Pins Used 0 8.11.2 First Order Modulator - SC Mode JTAG 4 or 5 A first order modulator is constructed by placing the SC/CT block in an integrator mode and using a comparator to provide a 1-bit feedback to the input. Depending on this bit, a reference voltage is either subtracted or added to the input signal. The block output SWD 2 SWV 1 SWD + SWV 3 Document Number: 001-53304 Rev. *F Page 57 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data 9.1 JTAG Interface 9.4 Trace Features The IEEE 1149.1 compliant JTAG interface exists on four or five pins (the nTRST pin is optional). The JTAG clock frequency can be up to 8 MHz, or 1/3 of the CPU clock frequency for 8 and 16-bit transfers, or 1/5 of the CPU clock frequency for 32-bit transfers, whichever is least. By default, the JTAG pins are enabled on new devices but the JTAG interface can be disabled, allowing these pins to be used as General Purpose I/O (GPIO) instead. The JTAG interface is used for programming the flash memory, debugging, I/O scan chains, and JTAG device chaining. The CY8C34 supports the following trace features when using JTAG or SWD: 9.2 Serial Wire Debug Interface „ Trace windowing, that is, only trace when the PC is within a The SWD interface is the preferred alternative to the JTAG interface. It requires only two pins instead of the four or five needed by JTAG. SWD provides all of the programming and debugging features of JTAG at the same speed. SWD does not provide access to scan chains or device chaining. The SWD clock frequency can be up to 1/3 of the CPU clock frequency. SWD uses two pins, either two of the JTAG pins (TMS and TCK) or the USBIO D+ and D- pins. The USBIO pins are useful for in system programming of USB solutions that would otherwise require a separate programming connector. One pin is used for the data clock and the other is used for data input and output. SWD can be enabled on only one of the pin pairs at a time. This only happens if, within 8 µs (key window) after reset, that pin pair (JTAG or USB) receives a predetermined sequence of 1s and 0s. SWD is used for debugging or for programming the flash memory. The SWD interface can be enabled from the JTAG interface or disabled, allowing its pins to be used as GPIO. Unlike JTAG, the SWD interface can always be reacquired on any device during the key window. It can then be used to reenable the JTAG interface, if desired. When using SWD or JTAG pins as standard GPIO, make sure that the GPIO functionality and PCB circuits do not interfere with SWD or JTAG use. „ Trace the 8051 program counter (PC), accumulator register (ACC), and one SFR / 8051 core RAM register „ Trace depth up to 1000 instructions if all registers are traced, or 2000 instructions if only the PC is traced (on devices that include trace memory) „ Program address trigger to start tracing given range „ Two modes for handling trace buffer full: continuous (overwriting the oldest trace data) or break when trace buffer is full 9.5 Single Wire Viewer Interface The SWV interface is closely associated with SWD but can also be used independently. SWV data is output on the JTAG interface’s TDO pin. If using SWV, the designer must configure the device for SWD, not JTAG. SWV is not supported with the JTAG interface. SWV is ideal for application debug where it is helpful for the firmware to output data similar to 'printf' debugging on PCs. The SWV is ideal for data monitoring, because it requires only a single pin and can output data in standard UART format or Manchester encoded format. For example, it can be used to tune a PID control loop in which the output and graphing of the three error terms greatly simplifies coefficient tuning. The following features are supported in SWV: „ 32 virtual channels, each 32 bits long „ Simple, efficient packing and serializing protocol „ Supports standard UART format (N81) 9.3 Debug Features 9.6 Programming Features Using the JTAG or SWD interface, the CY8C34 supports the following debug features: The JTAG and SWD interfaces provide full programming support. The entire device can be erased, programmed, and verified. Designers can increase flash protection levels to protect firmware IP. Flash protection can only be reset after a full device erase. Individual flash blocks can be erased, programmed, and verified, if block security settings permit. „ Halt and single-step the CPU „ View and change CPU and peripheral registers, and RAM addresses „ Eight program address breakpoints „ One memory access breakpoint—break on reading or writing any memory address and data value „ Break on a sequence of breakpoints (non recursive) „ Debugging at the full speed of the CPU „ Debug operations are possible while the device is reset, or in low power modes „ Compatible with PSoC Creator and MiniProg3 programmer and debugger „ Standard JTAG programming and debugging interfaces make CY8C34 compatible with other popular third-party tools (for example, ARM / Keil) Document Number: 001-53304 Rev. *F 9.7 Device Security PSoC 3 offers an advanced security feature called device security, which permanently disables all test, programming, and debug ports, protecting your application from external access. The device security is activated by programming a 32-bit key (0x50536F43) to a Write Once Latch (WOL). The Write Once Latch is a type of nonvolatile latch (NVL). The cell itself is an NVL with additional logic wrapped around it. Each WOL device contains four bytes (32 bits) of data. The wrapper outputs a ‘1’ if a super-majority (28 of 32) of its bits match a pre-determined pattern (0x50536F43); it outputs a ‘0’ if this majority is not reached. When the output is 1, the Write Once NV latch locks the part out of Debug and Test modes; it also permanently gates off the ability to erase or alter the contents of the latch. Matching all bits is intentionally not required, so that single (or few) bit failures do not deassert the WOL output. The state of Page 58 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data the NVL bits after wafer processing is truly random with no tendency toward 1 or 0. 10. Development Support The WOL only locks the part after the correct 32-bit key (0x50536F43) is loaded into the NVL's volatile memory, programmed into the NVL's nonvolatile cells, and the part is reset. The output of the WOL is only sampled on reset and used to disable the access. This precaution prevents anyone from reading, erasing, or altering the contents of the internal memory. The CY8C34 family has a rich set of documentation, development tools, and online resources to assist you during your development process. Visit psoc.cypress.com/getting-started to find out more. The user can write the key into the WOL to lock out external access only if no flash protection is set (see “Flash Security” on page 18). However, after setting the values in the WOL, a user still has access to the part until it is reset. Therefore, a user can write the key into the WOL, program the flash protection data, and then reset the part to lock it. A suite of documentation, supports the CY8C34 family to ensure that you can find answers to your questions quickly. This section contains a list of some of the key documents. If the device is protected with a WOL setting, Cypress cannot perform failure analysis and, therefore, cannot accept RMAs from customers. The WOL can be read out via Serial Wire Debug (SWD) port to electrically identify protected parts. The user can write the key in WOL to lock out external access only if no flash protection is set. For more information on how to take full advantage of the security features in PSoC see the PSoC 3 TRM. Disclaimer Note the following details of the flash code protection features on Cypress devices. Cypress products meet the specifications contained in their particular Cypress data sheets. Cypress believes that its family of products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress, that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Cypress is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress are committed to continuously improving the code protection features of our products. Document Number: 001-53304 Rev. *F 10.1 Documentation Software User Guide: A step-by-step guide for using PSoC Creator. The software user guide shows you how the PSoC Creator build process works in detail, how to use source control with PSoC Creator, and much more. Component Data Sheets: The flexibility of PSoC allows the creation of new peripherals (components) long after the device has gone into production. Component data sheets provide all of the information needed to select and use a particular component, including a functional description, API documentation, example code, and AC/DC specifications. Application Notes: PSoC application notes discuss a particular application of PSoC in depth; examples include brushless DC motor control and on-chip filtering. Application notes often include example projects in addition to the application note document. Technical Reference Manual: The Technical Reference Manual (TRM) contains all the technical detail you need to use a PSoC device, including a complete description of all PSoC registers. 10.2 Online In addition to print documentation, the Cypress PSoC forums connect you with fellow PSoC users and experts in PSoC from around the world, 24 hours a day, 7 days a week. 10.3 Tools With industry standard cores, programming, and debugging interfaces, the CY8C34 family is part of a development tool ecosystem. Visit us at www.cypress.com/go/psoccreator for the latest information on the revolutionary, easy to use PSoC Creator IDE, supported third party compilers, programmers, debuggers, and development kits. Page 59 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data 11. Electrical Specifications Specifications are valid for -40°C ≤ TA ≤ 85°C and TJ ≤ 100°C, except where noted. Specifications are valid for 1.71V to 5.5V, except where noted. The unique flexibility of the PSoC UDBs and analog blocks enable many functions to be implemented in PSoC Creator components, see the component data sheets for full AC/DC specifications of individual functions. See the “Example Peripherals” section on page 35 for further explanation of PSoC Creator components. 11.1 Absolute Maximum Ratings Table 11-1. Absolute Maximum Ratings DC Specifications Parameter Description Min Typ Max Units -55 25 100 °C Analog supply voltage relative to Vssa -0.5 - 6 V VDDD Digital supply voltage relative to Vssd -0.5 - 6 V Vddio I/O supply voltage relative to Vssd -0.5 - 6 V Vcca Direct analog core voltage input -0.5 - 1.95 V Vccd Direct digital core voltage input -0.5 - 1.95 V Vssa Analog ground voltage Vssd -0.5 - Vssd + 0.5 V Vgpio[5] DC input voltage on GPIO Includes signals sourced by VDDA and routed internal to the pin Vssd -0.5 - Vddio + 0.5 V Vsio DC input voltage on SIO Output disabled Vssd -0.5 - 7 V Output enabled Vssd -0.5 - 6 V TSTG Storage temperature VDDA Vind Voltage at boost converter input Vbat Boost converter supply Conditions Higher storage temperatures reduce NVL data retention time. Recommended storage temperature is +25°C ±25°C. Extended duration storage temperatures above 85°C degrade reliability. 0.5 - 5.5 V Vssd -0.5 - 5.5 V Ivddio Current per Vddio supply pin - - 100 mA ESDHBM Electro-static discharge voltage Human Body Model 2200 - - V ESDCDM Electro-static discharge voltage Charge Device Model 500 - - V Note Usage above the absolute maximum conditions listed in Table 11-1 may cause permanent damage to the device. Exposure to maximum conditions for extended periods of time may affect device reliability. When used below maximum conditions but above normal operating conditions the device may not operate to specification. Note 5. The Vddio supply voltage must be greater than the maximum analog voltage on the associated GPIO pins. Maximum analog voltage on GPIO pin ≤ Vddio ≤ VDDA. Document Number: 001-53304 Rev. *F Page 60 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data 11.2 Device Level Specifications Specifications are valid for -40°C ≤ TA ≤ 85°C and TJ ≤ 100°C, except where noted. Specifications are valid for 1.71V to 5.5V, except where noted. 11.2.1 Device Level Specifications Table 11-2. DC Specifications Parameter Description Conditions Min VDDA Analog supply voltage and input to Analog core regulator enabled analog core regulator 1.8 VDDA Analog supply voltage, analog regulator bypassed Analog core regulator disabled 1.71 VDDD Digital supply voltage relative to Vssd Digital core regulator enabled 1.8 VDDD Digital supply voltage, digital regulator bypassed Digital core regulator disabled 1.71 Vddio[5] I/O supply voltage relative to Vssio Vcca Direct analog core voltage input (Analog regulator bypass) Analog core regulator disabled 1.71 Vccd Direct digital core voltage input (Digital regulator bypass) Digital core regulator disabled 1.71 Vbat Voltage supplied to boost converter Typ Max Units 5.5 V 1.89 V VDDA V 1.89 V VDDA V 1.8 1.89 V 1.8 1.89 V 5.5 V 1.8 1.8 1.71 0.5 Active Mode, VDD = 1.71V - 5.5V Idd[6] Execute from CPU instruction buffer. See “Flash Program Memory” on page 18. CPU at 3 MHz T= -40°C T= 25°C mA 0.8 T= 85°C CPU at 6 MHz T= -40°C T= 25°C CPU at 12 MHz mA 1.2 T= 85°C mA mA 2.0 T= 85°C mA 3.5 mA T= 85°C mA T= -40°C mA T= 25°C T= 85°C Document Number: 001-53304 Rev. *F mA mA T= -40°C T= 25°C CPU at 50 MHz mA T= -40°C T= 25°C CPU at 24 MHz mA mA 6.6 mA mA Page 61 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data Table 11-2. DC Specifications (continued) Parameter Description Conditions Min Typ Max Units [7] Sleep Mode CPU OFF RTC = ON (= ECO32K ON, in low power mode) Sleep timer = ON (= ILO ON at 1 kHz)[8] WDT = OFF I2C Wake = OFF Comparator = OFF POR = ON Boost = OFF SIO pins in single ended input, unregulated output mode VDD = VDDIO = 4.5 - 5.5V T= -40°C µA T= 25°C µA T= 85°C µA VDD = VDDIO = 2.7 - 3.6V T= -40°C T= 25°C VDD = VDDIO = 1.71 1.95V µA 1 µA T= 85°C µA T= -40°C µA T= 25°C µA T= 85°C µA Hibernate Mode[7] VDD = VDDIO = 4.5 - 5.5V T= -40°C Hibernate mode current All regulators and oscillators off. SRAM retention GPIO interrupts are active Boost = OFF SIO pins in single ended input, unregulated output mode nA T= 25°C nA T= 85°C nA VDD = VDDIO = 2.7 - 3.6V T= -40°C T= 25°C VDD = VDDIO = 1.71 1.95V nA 200 nA T= 85°C nA T= -40°C nA T= 25°C nA T= 85°C nA Notes 6. The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective data sheets, available in PSoC Creator, the integrated design environment. To compute total current, find CPU current at frequency of interest and add peripheral currents for your particular system from the device data sheet and component data sheets. 7. If Vccd and Vcca are externally regulated, the voltage difference between Vccd and Vcca must be less than 50 mV. 8. Sleep timer generates periodic interrupts to wake up the CPU. This specification applies only to those times that the CPU is off. Document Number: 001-53304 Rev. *F Page 62 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data Table 11-3. AC Specifications[9] Parameter Description Conditions Min Typ Max Units FCPU CPU frequency 1.71V ≤ VDDD ≤ 5.5V DC - 50 MHz Fbusclk Bus frequency 1.71V ≤ VDDD ≤ 5.5V DC - 50 MHz Svdd Vdd ramp rate - - 1 V/ns Tio_init Time from VDDD/VDDA/Vccd/Vcca ≥ IPOR to I/O ports set to their reset states - - 10 µs Tstartup Time from VDDD/VDDA/Vccd/Vcca ≥ Vcca/Vccd = regulated from VDDA/VDDD, no PLL used, IMO PRES to CPU executing code at reset vector boot mode (12 MHz typ.) - - 66 µs Tsleep Wakeup from sleep mode Application of non-LVD interrupt to beginning of execution of next CPU instruction - - 12 µs Wakeup from sleep mode - Occurrence of LVD interrupt to beginning of execution of next CPU instruction - - 15 µs Wakeup from hibernate mode Application of external interrupt to beginning of execution of next CPU instruction - - 100 µs Thibernate Figure 11-1. Fcpu vs. Vdd Vdd Voltage 5.5V Valid Operating Region 3.3V 1.71V Valid Operating Region with SMP 0.5V 0V DC 1 MHz 10 MHz 50 MHz CPU Frequency Note 9. Based on device characterization (Not production tested). Document Number: 001-53304 Rev. *F Page 63 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data 11.3 Power Regulators Specifications are valid for -40°C ≤ TA ≤ 85°C and TJ ≤ 100°C, except where noted. Specifications are valid for 1.71V to 5.5V, except where noted. 11.3.1 Digital Core Regulator Table 11-4. Digital Core Regulator DC Specifications Parameter Description VDDD Input voltage Vccd Output voltage Regulator output capacitor Conditions ±10%, X5R ceramic or better. The two Vccd pins must be shorted together, with as short a trace as possible, see Power System on page 25 Min Typ Max Units 1.8 - 5.5 V - 1.80 - V - 1 - µF 11.3.2 Analog Core Regulator Table 11-5. Analog Core Regulator DC Specifications Parameter Description VDDA Input voltage Vcca Output voltage Regulator output capacitor Conditions ±10%, X5R ceramic or better Min Typ Max Units 1.8 - 5.5 V - 1.80 - V - 1 - µF Min Typ Max Units 11.3.3 Inductive Boost Regulator Table 11-6. Inductive Boost Regulator DC Specifications Parameter Vbat Iboost Description Input voltage Load current [10, 11] Conditions 0.5 - 5.5 V Vin=1.6-5.5V, Vout=1.6-5.5V, external diode Includes startup - - 50 mA Vin=1.6-3.6V, Vout=1.6-3.6V, internal diode - - 75 mA Vin=0.8-1.6V, Vout=1.6-3.6V, internal diode - - 30 mA Vin=0.8-1.6V, Vout=3.6-5.5V, external diode - - 20 mA Vin=0.5-0.8V, Vout=1.6-3.6V, internal diode - - 15 mA Lboost Boost inductor 10 µH spec'd 4.7 10 47 µH Cboost Filter capacitor[9] 22 µF || 0.1 µF spec'd 10 22 47 µF If External Schottky diode average forward current External Schottky diode is required for Vboost > 3.6V 1 - - A Vr External Schottky diode peak reverse voltage External Schottky diode is required for Vboost > 3.6V 20 - - V Ilpk Inductor peak current Quiescent current - - 700 mA Boost active mode - 200 - µA Boost standby mode, 32 khz external crystal oscillator, Iboost < 1 µA - 12 - µA Notes 10. For output voltages above 3.6V, an external diode is required. 11. Maximum output current applies for output voltages < 4x input voltage. Document Number: 001-53304 Rev. *F Page 64 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data Table 11-6. Inductive Boost Regulator DC Specifications (continued) Parameter Description Conditions Min Typ Max Units 1.8V 1.71 1.80 1.89 V 1.9V 1.81 1.90 2.00 V 2.0V 1.90 2.00 2.10 V 2.4V 2.28 2.40 2.52 V 2.7V 2.57 2.70 2.84 V 3.0V 2.85 3.00 3.15 V 3.3V 3.14 3.30 3.47 V [9] Boost output voltage range Vboost 3.6V 3.42 3.60 3.78 V 4.75 5.00 5.25 V Load regulation - - TBD % Line regulation - - TBD % 90 - - % Conditions Min Typ Max Units Vout = 1.8V, Fsw = 400 kHz, Iout = 10 mA - - 100 mV - 0.1, 0.4, or 2 - MHz 20 - 80 % 5.0V External diode required Efficiency Vbat = 2.4 V, Vout = 2.7 V, Iout = 10 mA, Fsw = 400 kHz Table 11-7. Inductive Boost Regulator AC Specifications Parameter Description Vripple Ripple voltage (peak-to-peak) Fsw Switching frequency Duty cycle Document Number: 001-53304 Rev. *F Page 65 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data 11.4 Inputs and Outputs Specifications are valid for -40°C ≤ TA ≤ 85°C and TJ ≤ 100°C, except where noted. Specifications are valid for 1.71V to 5.5V, except where noted. 11.4.1 GPIO Table 11-8. GPIO DC Specifications Parameter Description Vih Input voltage high threshold Vil Input voltage low threshold Vih Input voltage high threshold Vih Input voltage high threshold Vil Input voltage low threshold Vil Input voltage low threshold Voh Output voltage high Vol Output voltage low Rpullup Rpulldown Iil Cin Pull up resistor Pull down resistor Input leakage current (absolute value)[9] Input capacitance[9] Vh Input voltage hysteresis (Schmitt-Trigger)[9] Current through protection diode to Vddio and Vssio Resistance pin to analog global bus Resistance pin to analog mux bus Idiode Rglobal Rmux Conditions Min CMOS Input, PRT[x]CTL = 0 0.7 × Vddio CMOS Input, PRT[x]CTL = 0 LVTTL Input, PRT[x]CTL = 1,Vddio 0.7 x Vddio < 2.7V LVTTL Input, PRT[x]CTL = 1, Vddio 2.0 ≥ 2.7V LVTTL Input, PRT[x]CTL = 1,Vddio < 2.7V LVTTL Input, PRT[x]CTL = 1, Vddio ≥ 2.7V Ioh = 4 mA at 3.3 Vddio Vddio - 0.6 Ioh = 1 mA at 1.8 Vddio Vddio - 0.5 Iol = 8 mA at 3.3 Vddio Iol = 4 mA at 1.8 Vddio 4 4 25°C, Vddio = 3.0V GPIOs without OpAmp outputs GPIOs with OpAmp outputs - Typ - Max Units V 0.3 × Vddio V V - - V - 0.3 x Vddio V - 0.8 V 5.6 5.6 40 0.6 0.6 8 8 2 7 18 - V V V V kΩ kΩ nA pF pF mV - - 100 µA - 320 220 - Ω Ω Conditions 3.3V Vddio Cload = 25 pF 3.3V Vddio Cload = 25 pF 3.3V Vddio Cload = 25 pF 3.3V Vddio Cload = 25 pF Min Typ Max Units 2 2 10 10 - 12 12 60 60 ns ns ns ns 90/10% Vddio into 25 pF - - 33 MHz 90/10% Vddio into 25 pF - - 20 MHz 3.3V < Vddio < 5.5V, slow strong drive 90/10% Vddio into 25 pF mode 1.71V < Vddio < 3.3V, slow strong drive 90/10% Vddio into 25 pF mode GPIO input operating frequency 1.71V < Vddio < 5.5V 90/10% Vddio - - 7 MHz - - 3.5 MHz - - 50 MHz 25°C, Vddio = 3.0V 25°C, Vddio = 3.0V Table 11-9. GPIO AC Specifications Parameter TriseF TfallF TriseS TfallS Fgpioout Fgpioin Description Rise time in Fast Strong Mode[9] Fall time in Fast Strong Mode[9] Rise time in Slow Strong Mode[9] Fall time in Slow Strong Mode[9] GPIO output operating frequency 3.3V < Vddio < 5.5V, fast strong drive mode 1.71V < Vddio < 3.3V, fast strong drive mode Document Number: 001-53304 Rev. *F Page 66 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data 11.4.2 SIO Table 11-10. SIO DC Specifications Parameter Vinref Description Conditions Min Typ Max Units 0.5 - 0.52 ×Vddio V Vddio > 3.7 1 - Vddio-1 V Vddio < 3.7 1 - Vddio - 0.5 V GPIO mode CMOS input 0.7 × Vddio - - V Differential input mode Hysteresis disabled Vinref+0.1 - - V Input voltage reference (Differential input mode) Output voltage reference (Regulated output mode) Voutref Input voltage high threshold Vih Input voltage low threshold Vil GPIO mode CMOS input - - 0.3 × Vddio V Differential input mode Hysteresis disabled - - Vinref-0.1 V Output voltage high Voh Unregulated mode Ioh = 4 mA, Vddio = 3.3V Vddio - 0.4 - - V Regulated mode Ioh = 1 mA Voutref-0.6 - Voutref+0.2 V Regulated mode Ioh = 0.1 mA Voutref-0.25 - Voutref+0.2 V Output voltage low Vol Vddio = 3.30V, Iol = 25 mA - - 0.8 V Vddio = 1.80V, Iol = 4 mA - - 0.4 V Rpullup Pull up resistor 4 5.6 8 kΩ Rpulldown Pull down resistor 4 5.6 8 kΩ Iil Input leakage current (absolute value)[9] Vih < Vddsio 25°C, Vddsio = 3.0V, Vih = 3.0V - - 14 nA Vih > Vddsio 25°C, Vddsio = 0V, Vih = 3.0V - - 10 µA - - 7 pF Single ended mode (GPIO mode) - 40 - mV Differential mode - 50 - mV - - 100 µA Cin Input Capacitance[9] Vh Input voltage hysteresis (Schmitt-Trigger)[9] Idiode Current through protection diode to Vssio Table 11-11. SIO AC Specifications Min Typ Max Units TriseF Parameter Rise time in Fast Strong Mode (90/10%)[9] Description Cload = 25 pF, Vddio = 3.3V 1 - 12 ns TfallF Fall time in Fast Strong Mode (90/10%)[9] Cload = 25 pF, Vddio = 3.3V 1 - 12 ns TriseS Rise time in Slow Strong Mode (90/10%)[9] Cload = 25 pF, Vddio = 3.0V 10 - 75 ns TfallS Fall time in Slow Strong Mode (90/10%)[9] Cload = 25 pF, Vddio = 3.0V 10 - 60 ns Document Number: 001-53304 Rev. *F Conditions Page 67 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data Table 11-11. SIO AC Specifications (continued) Parameter Description Conditions Min Typ Max Units 90/10% Vddio into 25 pF - - 33 MHz 1.71V < Vddio < 3.3V, Unregulated 90/10% Vddio into 25 pF output (GPIO) mode, fast strong drive mode - - 16 MHz 3.3V < Vddio < 5.5V, Unregulated output (GPIO) mode, slow strong drive mode 90/10% Vddio into 25 pF - - 5 MHz 1.71V < Vddio < 3.3V, Unregulated 90/10% Vddio into 25 pF output (GPIO) mode, slow strong drive mode - - 4 MHz 3.3V < Vddio < 5.5V, Regulated Output continuously switching into output mode, fast strong drive mode 25 pF - - 20 MHz 1.71V < Vddio < 3.3V, Regulated Output continuously switching into output mode, fast strong drive mode 25 pF - - 10 MHz 1.71V < Vddio < 5.5V, Regulated output mode, slow strong drive mode Output continuously switching into 25 pF - - 2.5 MHz 90/10% Vddio - - 50 MHz SIO output operating frequency 3.3V < Vddio < 5.5V, Unregulated output (GPIO) mode, fast strong drive mode Fsioout Fsioin SIO input operating frequency 1.71V < Vddio < 5.5V 11.4.3 USBIO For operation in USB mode, VDDD range condition is 3.15V ≤ VDDD ≤ 3.45V (USB regulator bypassed) or 4.35V ≤ VDDD ≤ 5.25V (USB regulator in use). For operation in GPIO mode, the standard range for VDDD applies, see Device Level Specifications on page 61. Table 11-12. USBIO DC Specifications Parameter Description Conditions Min Typ Max Units Rusbi USB D+ pull up resistance With idle bus 0.900 - 1.575 kΩ Rusba USB D+ pull up resistance While receiving traffic 1.425 - 3.090 kΩ Vohusb Static output high 15 kΩ ±5% to Vss, internal pull up enabled 2.8 - 3.6 V Volusb Static output low 15 kΩ ±5% to Vss, internal pull up enabled - - 0.3 V Vohgpio Output voltage high, GPIO mode Ioh = 4 mA, VDDD ≥ 3V 2.4 - - V Volgpio Output voltage low, GPIO mode Iol = 4 mA, VDDD ≥ 3V - - 0.3 V Vdi Differential input sensitivity |(D+)-(D-)| - - 0.2 V Vcm Differential input common mode range 0.8 - 2.5 V Vse Single ended receiver threshold 0.8 - 2 V Rps2 PS/2 pull up resistance In PS/2 mode, with PS/2 pull up enabled 3 - 7 kΩ External USB series resistor In series with each USB pin 21.78 (-1%) 22 22.22 (+1%) Ω Zo USB driver output impedance Including Rext 28 - 44 Ω Cin USB transceiver input capacitance - - 20 pF Iil Input leakage current (absolute value) - - 2 nA Rext Document Number: 001-53304 Rev. *F 25°C, VDDD = 3.0V Page 68 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data Table 11-13. USBIO AC Specifications Parameter Description Conditions Min Typ Max Units Tdrate Full-speed data rate average bit rate 12 - 0.25% 12 12 + 0.25% MHz Tjr1 Receiver data jitter tolerance to next transition -8 - 8 ns Tjr2 Receiver data jitter tolerance to pair transition -5 - 5 ns Tdj1 Driver differential jitter to next transition -3.5 - 3.5 ns Tdj2 Driver differential jitter to pair transition -4 - 4 ns Tfdeop Source jitter for differential transition to SE0 transition -2 - 5 ns Tfeopt Source SE0 interval of EOP 160 - 175 ns Tfeopr Receiver SE0 interval of EOP 82 - - ns Tfst Width of SE0 interval during differential transition - - 14 ns Fgpio_out GPIO mode output operating frequency - - 20 MHz VDDD = 1.71V - - 6 MHz Tr_gpio Rise time, GPIO mode, 10%/90% VDDD VDDD > 3V, 25 pF load 1 - 12 ns VDDD = 1.71V, 25 pF load 4 - 40 ns Tf_gpio Fall time, GPIO mode, 90%/10% VDDD VDDD > 3V, 25 pF load 1 - 12 ns 4 - 40 ns Min Typ Max Units 3V ≤ VDDD ≤ 5.5V VDDD = 1.71V, 25 pF load Table 11-14. USB Driver AC Specifications Parameter Description Conditions Tr Transition rise time 4 - 20 ns Tf Transition fall time 4 - 20 ns 90% - 111% 1.3 - 2 V Min Typ Max Units TR Rise/fall time matching Vcrs Output signal crossover voltage 11.4.4 XRES Table 11-15. XRES DC Specifications Parameter Description Conditions Vih Input voltage high threshold CMOS Input, PRT[x]CTL = 0 0.7 × Vddio - - V Vil Input voltage low threshold CMOS Input, PRT[x]CTL = 0 - - 0.3 × Vddio V Rpullup Pull up resistor 4 5.6 8 kΩ Cin Input capacitance[9] - 3 - pF Vh Input voltage hysteresis (Schmitt-Trigger)[9] - 100 - mV Idiode Current through protection diode to Vddio and Vssio - - 100 µA Min Typ Max Units 1 - - µs Table 11-16. XRES AC Specifications Parameter Treset Description Reset pulse width Document Number: 001-53304 Rev. *F Conditions Page 69 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data 11.5 Analog Peripherals Specifications are valid for -40°C ≤ TA ≤ 85°C and TJ ≤ 100°C, except where noted. Specifications are valid for 1.71V to 5.5V, except where noted. 11.5.1 Opamp Table 11-17. Opamp DC Specifications Parameter Vioff Vioff TCVos Ge1 Vi Vo Iout Description Input offset voltage Input offset voltage Input offset voltage drift with temperature Gain error, unity gain buffer mode Quiescent current Input voltage range Output voltage range Output current Output current Iout CMRR Conditions T = 25 °C Rload = 1 kΩ Output load = 1 mA Output voltage is between Vssa +500 mV and VDDA -500 mV, and VDDA > 2.7V Output voltage is between Vssa +500 mV and VDDA -500 mV, and VDDA > 1.7V and VDDA < 2.7V Common mode rejection ratio[9] Min Vssa Vssa + 50 25 Typ 0.5 12 900 - Max 2 0.1 VDDA VDDA - 50 - Units mV mV µv/°C % µA mV mV mA 16 - - mA 70 - - dB Min 3 Typ - Max - Units MHz 3 - 38 - V/µs nv/ sqrtHz Table 11-18. Opamp AC Specifications Parameter GBW Gain BW[9] Tslew Description Slew rate[9] Input noise density[9] Document Number: 001-53304 Rev. *F Conditions 100 mV pk-pk, load capacitance 200 pF Load capacitance 200 pF Page 70 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data 11.5.2 Delta-Sigma ADC Table 11-19. 12-Bit Delta-Sigma ADC DC Specifications Parameter Description Conditions [9] Min Max Units bits Resolution 8 - 12 Number of channels - single ended - - No. of GPIO - - No. of GPIO/2 Yes - - Number of channels - differential Differential pair is formed using a pair of GPIOs Monotonicity[9] Gain error Input buffer bypassed - - ±0.2 % - - ±0.1 mV - - 3.75 mA Vssa - VDDA V Input offset voltage Current consumption 192 ksps, 12-bit mode, ADC clock = 6.144 MHz[9] Input voltage range - single ended[9] Input voltage range - differential[9] Vssa - VDDA V Input voltage range - differential (buffered)[9] Vssa - VDDA - 1 V 10 - - MΩ - kΩ 0.0032 % Input resistance[9] THD Typ Total harmonic distortion[9] Input buffer used [12] Input buffer bypassed, 12 bits, ADC clock = 6.144 MHz, gain = 1 - 148 Input buffer used - - Table 11-20. 12-Bit Delta-Sigma ADC AC Specifications Parameter PSRR CMRR SNR INL DNL Description Startup time[9] Power supply rejection ratio[9] Common mode rejection ratio[9] Sample rate Signal-to-noise ratio (SNR) Input bandwidth[9] Integral non linearity[9] Differential non linearity[9] Conditions Input buffer used Input buffer used ADC clock = 6.144 MHz, continuous sample mode Input buffer bypassed Min 90 90 - Typ - Max 4 192 Units samples dB dB ksps 70 - 44 - 1 1 dB kHz LSB LSB Min Typ Max Units 1.014 (-1%) 1.024 1.034 (+1%) V 11.5.3 Voltage Reference Table 11-21. Voltage Reference Specifications Parameter Vref Description Precision reference voltage Conditions Initial trim Note 12. Holding the gain and number of bits constant, the input resistance is proportional to the inverse of the clock frequency. Document Number: 001-53304 Rev. *F Page 71 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data 11.5.4 Analog Globals Table 11-22. Analog Globals Specifications Parameter Description Conditions Min Typ Max Units Rppag Resistance pin-to-pin through analog global[13] VDDA = 3.0V - 939 1461 Ω Rppmuxbus Resistance pin-to-pin through analog mux bus[13] VDDA = 3.0V - 721 1135 Ω BWag 3 dB bandwidth of analog globals VDDA = 3.0V - - 2 MHz CMRRag Common mode rejection for differential signals VDDA = 3.0V 85 91 - dB Min Typ Max Units 11.5.5 Comparator Table 11-23. Comparator DC Specifications Parameter Vioff Description Conditions Input offset voltage in fast mode Factory trim - - ±2 mV Input offset voltage in slow mode Factory trim - - ±2 mV Input offset voltage in fast mode [14] Custom trim - - ±2 mV Input offset voltage in slow mode[14] Custom trim - - ±1 mV Vioff Input offset voltage in ultra low power mode - ±12 - mV Vhyst Hysteresis Hysteresis enable mode - 10 32 mV Vicm Input common mode voltage Fast mode 0 - VDDA-0.1 V CMRR Common mode rejection ratio Icmp Vioff Slow mode 0 - VDDA V 50 - - dB High current mode/fast mode[9] - - 400 µA Low current mode/slow mode[9] - - 100 µA - 6 - µA Min Typ Max Units 50 mV overdrive, measured pin-to-pin - 95 TBD ns Response time, low current mode[9] 50 mV overdrive, measured pin-to-pin - 155 TBD ns 50 mV overdrive, measured pin-to-pin - 55 - µs Ultra low power mode [9] Table 11-24. Comparator AC Specifications Parameter Description Response time, high current mode[9] Tresp Response time, ultra low power mode[9] Conditions Note 13. The resistance of the analog global and analog mux bus is high if VDDA ≤ 2.7V, and the chip is in either sleep or hibernate mode. Use of analog global and analog mux bus under these conditions is not recommended. 14. The recommended procedure for using a custom trim value for the on-chip comparators can be found in the TRM. Document Number: 001-53304 Rev. *F Page 72 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data 11.5.6 IDAC Table 11-25. IDAC (Current Digital-to-Analog Converter) DC Specifications Parameter Description Conditions Resolution Min Typ Max - 8 - Units Output current Code = 255, VDDA ≥ 2.7V, RL 600Ω - 2.040 - mA Code = 255, VDDA ≤ 2.7V, RL 300Ω - 2.040 - mA Medium Code = 255, RL 600Ω - 255 - µA Low[9] Code = 255, RL 600Ω - 31.875 - µA High[9] Iout [9] INL Integral non linearity RL 600Ω, CL=15 pF - - ±1 LSB DNL Differential non linearity RL 600Ω, CL=15 pF - - ±0.5 LSB - 0 ±1 LSB Uncompensated - - 3.5 % Ezs Zero scale error Eg Gain error Temperature compensated - - TBD % IDAC_ICC DAC current low speed mode[9] Code = 0 - - 100 µA IDAC_ICC DAC current high speed mode[9] Code = 0 - - 500 µA Min Typ Max Units - - 8 Msps Table 11-26. IDAC (Current Digital-to-Analog Converter) AC Specifications Parameter Fdac Tsettle Description Conditions Update rate Settling time to 0.5LSB Full scale transition, 600Ω load, CL = 15 pF Fast mode Independent of IDAC range setting (Iout) - - 100 ns Slow mode Independent of IDAC range setting (Iout) - - 1000 ns Min Typ Max Units - 8 - 11.5.7 VDAC Table 11-27. VDAC (Voltage Digital-to-Analog Converter) DC Specifications Parameter Description Conditions Resolution Output resistance[9] Rout High Vout = 4V - 16 - kΩ Low Vout = 1V - 4 - kΩ Code = 255, VDDA > 5V - 4 - V Output voltage range Vout [9] High Code = 255 - 1 - V INL Integral non linearity Low CL=15 pF - - ±1 LSB DNL Differential non linearity CL=15 pF - - ±1 LSB Ezs Zero scale error - - ±1 LSB Eg Gain error [9] VDAC_ICC DAC current low speed mode VDAC_ICC DAC current high speed mode[9] Document Number: 001-53304 Rev. *F Uncompensated - - 3 % Temperature compensated - - TBD % Code = 0 - - 100 µA Code = 0 - - 500 µA Page 73 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data Table 11-28. VDAC (Voltage Digital-to-Analog Converter) AC Specifications Parameter Fdac Description Conditions Update rate 1V mode - Update rate[9] 4V mode - [9] Settling time to 0.5LSB Tsettle Min [9] Typ Max Units - 1 Msps - 250 Ksps Full scale transition, CL = 15 pF High[9] Vout = 4V - - 4000 ns [9] Vout = 1V - - 1000 ns Low 11.5.8 Discrete Time Mixer The discrete time mixer is used for modulating (shifting signals in frequency down) where the output frequency of the mixer is equal to the difference of the input frequency and the local oscillator frequency. The discrete time mixer is created using a SC/CT Analog Block, see the Mixer component data sheet in PSoC Creator for full AC/DC specifications, and APIs and example code. Table 11-29. Discrete Time Mixer DC Specifications Parameter Description Conditions Analog input noise injection (RMS) 1 MHz clock rate 4 MHz clock rate Input voltage[15] Min Typ Max Units - 10 - µV - 30 - µV Vssa - VDDA V Input offset voltage - - 10 mV Quiescent current - 0.9 2 mA Table 11-30. Discrete Time Mixer AC Specifications Parameter LO Min Typ Max Units Local oscillator frequency[9] Description Conditions 0 - 4 MHz Input signal frequency for down mixing[9] 0 - 14 MHz 11.5.9 Continuous Time Mixer The continuous time mixer is used for modulating (shift) frequencies up or down, to a limit of 1.0 MHz. The continuous time mixer is created using a SC/CT Analog Block, see the Mixer component data sheet in PSoC Creator for full AC/DC specifications, and APIs and example code. Table 11-31. Continuous Time Mixer DC Specifications Parameter Description Conditions Analog input noise injection (RMS) No input signal Input voltage[15] Min Typ Max Units Vssa - 10 µV - VDDA V Input offset voltage - - 10 mV Quiescent current - 0.9 2 mA Min Typ Max Units - - 1 MHz - - 1 MHz Table 11-32. Continuous Time Mixer AC Specifications Parameter LO Description Local oscillator frequency Input signal frequency[9] Conditions [9] Note 15. Bandwidth is guaranteed for input common mode between 0.3V and VDDA-1.2V and for output that is between 0.05V and VDDA-0.05V. Document Number: 001-53304 Rev. *F Page 74 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data 11.5.10 Transimpedance Amplifier The TIA is created using a SC/CT Analog Block, see the TIA component data sheet in PSoC Creator for full AC/DC specifications, and APIs and example code. Table 11-33. Transimpedance Amplifier (TIA) DC Specifications Parameter Vioff Description Conversion resistance Rconv Conditions Input offset voltage Min Typ Max Units - - 10 mV [16] R = 20K 40 pF load -20 - +30 % R = 30K 40 pF load -20 - +30 % R = 40K 40 pF load -20 - +30 % R = 80K 40 pF load -20 - +30 % R = 120K 40 pF load -20 - +30 % R = 250K 40 pF load -20 - +30 % R= 500K 40 pF load -20 - +30 % R = 1M 40 pF load -20 - +30 % - 900 - µA Min Typ Max Units R = 20K 1800 - - kHz R = 120K 330 - - kHz R = 1M 47 - - kHz R = 20K 1500 - - kHz R = 120K 300 - - kHz R = 1M 46 - - kHz Quiescent current Table 11-34. Transimpedance Amplifier (TIA) AC Specifications Parameter Description Input bandwidth (-3 dB) - 20 pF load Conditions [15] Input bandwidth (3 dB) - 40 pF load Note 16. Conversion resistance values are not calibrated. Calibrated values and details about calibration are provided in PSoC Creator component data sheets. External precision resistors can also be used. Document Number: 001-53304 Rev. *F Page 75 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data 11.5.11 Programmable Gain Amplifier The PGA is created using a SC/CT Analog Block, see the PGA component data sheet in PSoC Creator for full AC/DC specifications, and APIs and example code. Table 11-35. PGA DC Specifications Parameter Vos Description Conditions Min Typ Max Units - - 10 mV - ±30 - µV/°C - - 250 µA 100 kHz 69 - - dB 1 MHz 38 - - dB For non inverting inputs 35 - - MΩ - - ±0.15 % ±1 % Input offset voltage[9] DeltaV/DeltaTa Input offset voltage drift [9] Output current source capability[9] Drive setting 3, VDDA = 1.71V PSRR Zin [9] Power supply rejection ratio Input impedance [9] Gain Error[9] Non inverting mode, reference = Vssa Ge1 Gain = 1 Rin of 40K Ge2 Gain = 2 Rin of 40K Ge4 Gain = 4 Rin of 40K - - ±1.03 % Ge8 Gain = 8 Rin of 40K - - ±1.23 % Ge16 Gain = 16 Rin of 40K - - ±2.5 % Ge32 Gain = 32 Rin of 40K - - ±5 % Ge50 Gain = 50 Rin of 40K - - ±5 % Vonl DC output non linearity G = 1[9] - - 0.01 % of FSR Voh, Vol Output voltage swing Vssa + 0.15 - VDDA 0.15 V Quiescent current[9] - - 1.65 mA Conditions Min Typ Max Units Table 11-36. PGA AC Specifications Parameter Description -3 db Bandwidth[9] BW1 Gain = 1 Noninverting mode, 300 mV ≤ Vin ≤ VDDA - 1.2V, Cl ≤ 25 pF 7 - - MHz BW24 Gain = 24 Noninverting mode, 300 mV ≤ Vin ≤ VDDA - 1.2V, Cl ≤ 25 pF 360 - - kHz BW48 Gain = 48 Noninverting mode, 300 mV ≤ Vin ≤ VDDA - 1.2V, Cl ≤ 25 pF 215 - - kHz 3 - - V/µs Slew Rate[9] SR1 Gain = 1 VDDA = 1.71V 5% to 90% FS output SR24 Gain = 24 RC limited 0.5 - - V/µs SR48 Gain = 48 RC limited 0.5 - - V/µs Input Noise Voltage Density [9] eni1 Gain = 1 10 kHz - 38 - nV/sqrtHz eni24 Gain = 24 10 kHz - 38 - nV/sqrtHz eni48 Gain = 48 10 kHz - 38 - nV/sqrtHz Document Number: 001-53304 Rev. *F Page 76 of 101 [+] Feedback PRELIMINARY PSoC® 3: CY8C34 Family Data 11.5.12 Unity Gain Buffer The Unity Gain Buffer is created using a SC/CT Analog Block. See the Unity Gain Buffer component data sheet in PSoC Creator for full AC/DC specifications, and APIs and example code. Table 11-37. Unity Gain Buffer DC Specifications Parameter Vos Description Input offset voltage Conditions [9] Offset voltage drift Input voltage range Voh, Vol Min Typ Max Units - - 10 mV - - 30 µv/°C Vssa - VDDA V Vssa + 0.15 - VDDA 0.15 V Output current source capability[9] Drive setting 3, VDDA = 1.71V - - 250 µA Quiescent current - 900 - µA Output voltage range Table 11-38. Unity Gain Buffer AC Specifications Parameter Conditions Min Typ Max Units Bandwidth[9, 15] Description Noninverting mode, 300 mV ≤ Vin ≤ VDDA - 1.2V, Cl ≤ 25 pF 7 - - MHz Slew rate[9] VDDA = 1.71V 5% to 90% FS output, CL = 50 pF 3 - - V/µs - 38 - nV/sqrtHz Min Typ Max Units - ±5 - °C Input noise spectral density[9] 11.5.13 Temperature Sensor Table 11-39. Temperature Sensor Specifications Parameter Description Temp sensor accuracy Conditions Range: -40°C to +85°C 11.5.14 LCD Direct Drive Table 11-40. LCD Direct Drive DC Specifications Parameter Description Conditions Min Typ Max Units 16x4 segment display at 50 Hz [18]. - 19 - μA 2 - 5.5 V VDDA ≥ 3V and VDDA ≥ Vbias - 9.1 x VDDA - mV Drivers may be combined. - 500 5000 pF - - 10 mV 528 - 655 µA Strong drive 220 260 300 µA Weak drive - 11 - µA Icc LCD operating current Vbias LCD bias range (Vbias refers to the VDDA ≥ 3V and VDDA ≥ Vbias main output voltage(V0) of LCD DAC) LCD bias step size LCD capacitance per segment/common driver Long term segment offset Iout (Output drive current per segment driver) Strong drive Output current in Strong drive mode for Vddio = 5.5V Icc per segment driver Weak drive 2 - 22 - µA No drive -