PSoC® 4: PSoC 4200
Family Datasheet
®
Programmable System-on-Chip (PSoC )
General Description
PSoC® 4 is a scalable and reconfigurable platform architecture for a family of mixed-signal programmable embedded system
controllers with an ARM® Cortex™-M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible
automatic routing. The PSoC 4200 product family, based on this platform, is a combination of a microcontroller with digital programmable logic, high-performance analog-to-digital conversion, opamps with Comparator mode, and standard communication and timing
peripherals. The PSoC 4200 products will be fully upward compatible with members of the PSoC 4 platform for new applications and
design needs. The programmable analog and digital sub-systems allow flexibility and in-field tuning of the design.
Features
32-bit MCU Sub-system
Serial Communication
■
48-MHz ARM Cortex-M0 CPU with single cycle multiply
■
Up to 32 kB of flash with Read Accelerator
■
Up to 4 kB of SRAM
■
Two independent run-time reconfigurable serial communication blocks (SCBs) with reconfigurable I2C, SPI, or UART
functionality
Timing and Pulse-Width Modulation
Programmable Analog
■
Four 16-bit timer/counter pulse-width modulator (TCPWM)
blocks
■
Center-aligned, Edge, and Pseudo-random modes
■
Comparator-based triggering of Kill signals for motor drive and
other high-reliability digital logic applications
■
Two opamps with reconfigurable high-drive external and
high-bandwidth internal drive, Comparator modes, and ADC
input buffering capability
■
12-bit, 1-Msps SAR ADC with differential and single-ended
modes; Channel Sequencer with signal averaging
■
Two current DACs (IDACs) for general-purpose or capacitive
sensing applications on any pin
Up to 36 Programmable GPIOs
■
Two low-power comparators that operate in Deep Sleep mode
■
Any GPIO pin can be CapSense, LCD, analog, or digital
■
Drive modes, strengths, and slew rates are programmable
Programmable Digital
■
Four programmable logic blocks called universal digital blocks,
(UDBs), each with 8 Macrocells and data path
■
Cypress-provided peripheral component library, user-defined
state machines, and Verilog input
Five different packages
■
■
Low Power 1.71-V to 5.5-V Operation
48-pin TQFP, 44-pin TQFP, 40-pin QFN, 35-ball WLCSP, and
28-pin SSOP package
35-ball WLCSP package is shipped with I2C Bootloader in
Flash
■
20-nA Stop Mode with GPIO pin wakeup
Extended Industrial Temperature Operation
■
Hibernate and Deep Sleep modes allow wakeup-time versus
power trade-offs
■
PSoC Creator Design Environment
Capacitive Sensing
■
Cypress CapSense Sigma-Delta (CSD) provides best-in-class
SNR (>5:1) and water tolerance
■
Cypress-supplied software component makes capacitive
sensing design easy
■
Automatic hardware tuning (SmartSense™)
■
Integrated Development Environment (IDE) provides
schematic design entry and build (with analog and digital
automatic routing)
■
Applications Programming Interface (API) component for all
fixed-function and programmable peripherals
Industry-Standard Tool Compatibility
Segment LCD Drive
■
■
LCD drive supported on all pins (common or segment)
■
Operates in Deep Sleep mode with 4 bits per pin memory
Cypress Semiconductor Corporation
Document Number: 001-87197 Rev. *J
–40 °C to + 105 °C operation
•
198 Champion Court
After schematic entry, development can be done with
ARM-based industry-standard development tools
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 10, 2017
PSoC® 4: PSoC 4200
Family Datasheet
More Information
Cypress provides a wealth of data at www.cypress.com to help you to select the right PSoC device for your design, and to help you
to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article
KBA86521, How to Design with PSoC 3, PSoC 4, and PSoC 5LP. Following is an abbreviated list for PSoC 4:
■
■
■
Overview: PSoC Portfolio, PSoC Roadmap
Product Selectors: PSoC 1, PSoC 3, PSoC 4, PSoC 5LP
In addition, PSoC Creator includes a device selection tool.
Application notes: Cypress offers a large number of PSoC
application notes covering a broad range of topics, from basic
to advanced level. Recommended application notes for getting
started with PSoC 4 are:
❐ AN79953: Getting Started With PSoC 4
❐ AN88619: PSoC 4 Hardware Design Considerations
❐ AN86439: Using PSoC 4 GPIO Pins
❐ AN57821: Mixed Signal Circuit Board Layout
❐ AN81623: Digital Design Best Practices
❐ AN73854: Introduction To Bootloaders
❐ AN89610: ARM Cortex Code Optimization
❐ AN90071: CY8CMBRxxx CapSense Design Guide
■
Technical Reference Manual (TRM) is in two documents:
❐ Architecture TRM details each PSoC 4 functional block.
❐ Registers TRM describes each of the PSoC 4 registers.
Development Kits:
❐ CY8CKIT-042, PSoC 4 Pioneer Kit, is an easy-to-use and
inexpensive development platform. This kit includes
connectors for Arduino™ compatible shields and Digilent®
Pmod™ daughter cards.
❐ CY8CKIT-049 is a very low-cost prototyping platform. It is a
low-cost alternative to sampling PSoC 4 devices.
❐ CY8CKIT-001 is a common development platform for any
one of the PSoC 1, PSoC 3, PSoC 4, or PSoC 5LP families
of devices.
The MiniProg3 device provides an interface for flash
programming and debug.
■
PSoC Creator
PSoC Creator is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design
of PSoC 3, PSoC 4, and PSoC 5LP based systems. Create designs using classic, familiar schematic capture supported by over 100
pre-verified, production-ready PSoC Components; see the list of component datasheets. With PSoC Creator, you can:
1. Drag and drop component icons to build your hardware
3. Configure components using the configuration tools
system design in the main design workspace
4. Explore the library of 100+ components
2. Codesign your application firmware with the PSoC hardware,
5. Review component datasheets
using the PSoC Creator IDE C compiler
Figure 1. Multiple-Sensor Example Project in PSoC Creator
1
2
3
4
5
Document Number: 001-87197 Rev. *J
Page 2 of 45
PSoC® 4: PSoC 4200
Family Datasheet
Contents
Functional Definition........................................................ 5
CPU and Memory Subsystem ..................................... 5
System Resources ...................................................... 5
Analog Blocks.............................................................. 6
Programmable Digital.................................................. 7
Fixed Function Digital.................................................. 8
GPIO ........................................................................... 8
Special Function Peripherals....................................... 9
Pinouts ............................................................................ 10
Power............................................................................... 16
Unregulated External Supply..................................... 16
Regulated External Supply........................................ 17
Development Support .................................................... 18
Documentation .......................................................... 18
Online ........................................................................ 18
Tools.......................................................................... 18
Electrical Specifications ................................................ 19
Absolute Maximum Ratings....................................... 19
Device Level Specifications....................................... 19
Document Number: 001-87197 Rev. *J
Analog Peripherals ....................................................
Digital Peripherals .....................................................
Memory .....................................................................
System Resources ....................................................
Ordering Information......................................................
Part Numbering Conventions ....................................
Packaging........................................................................
Acronyms ........................................................................
Document Conventions .................................................
Units of Measure .......................................................
Revision History .............................................................
Sales, Solutions, and Legal Information ......................
Worldwide Sales and Design Support.......................
Products ....................................................................
PSoC® Solutions ......................................................
Cypress Developer Community.................................
Technical Support .....................................................
23
27
30
31
35
36
37
41
43
43
44
45
45
45
45
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Page 3 of 45
PSoC® 4: PSoC 4200
Family Datasheet
Figure 2. Block Diagram
C P U S ubs y s tem
P S oC 4200
SWD
32-bit
AH B-Lite
C ortex
M0
48 MH z
F LA S H
U p to 32 kB
SRAM
U p to 4 kB
R OM
4 kB
F AST M U L
N VIC, IR QM X
R ead Accelerator
SR AM C ontroller
R OM C ontroller
System R eso u rces
x1
SM X
C TBm
2x Op Am p x1
U DB
...
UD B
x4
2x LP Comparator
SAR AD C
(12-b it)
Programmable
D igital
LCD
Programmable
Analog
2x SCB-I2C/SPI/UART
T est
D F T Logic
D F T Analog
Peripheral Interconnect (MMIO )
PC LK
Capsense
Reset
R eset C ontrol
XR ES
P eripherals
4x TCPWM
Clock
C lock C ontrol
WD T
IM O
ILO
System Interconnect (Single Layer AH B )
IOSS GPIO (5x ports)
Pow er
Sleep C ontrol
WIC
POR
LVD
R EF
BOD
PWR SYS
N VLatches
Po rt Interfa ce & D igita l Syste m In te rco n ne ct (D SI)
H igh Sp e ed I/ O M a trix
Pow er M odes
Active /Sleep
D eep Sleep
H ibernate
36x GPIOs
IO S ubs y s tem
The PSoC 4200 devices include extensive support for
programming, testing, debugging, and tracing both hardware
and firmware.
The ARM Serial_Wire Debug (SWD) interface supports all
programming and debug features of the device.
Complete debug-on-chip functionality enables full-device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
The PSoC Creator IDE provides fully integrated programming
and debug support for the PSoC 4200 devices. The SWD
interface is fully compatible with industry-standard third-party
tools. With the ability to disable debug features, with very robust
flash protection, and allowing customer-proprietary functionality
to be implemented in on-chip programmable blocks, the
Document Number: 001-87197 Rev. *J
PSoC 4200 family provides a level of security not possible with
multi-chip application solutions or with microcontrollers.
The debug circuits are enabled by default and can only be
disabled in firmware. If not enabled, the only way to re-enable
them is to erase the entire device, clear flash protection, and
reprogram the device with new firmware that enables debugging.
Additionally, all device interfaces can be permanently disabled
(device security) for applications concerned about phishing
attacks due to a maliciously reprogrammed device or attempts to
defeat security by starting and interrupting flash programming
sequences. Because all programming, debug, and test interfaces are disabled when maximum device security is enabled,
PSoC 4200 with device security enabled may not be returned for
failure analysis. This is a trade-off the PSoC 4200 allows the
customer to make.
Page 4 of 45
PSoC® 4: PSoC 4200
Family Datasheet
Functional Definition
System Resources
CPU and Memory Subsystem
Power System
CPU
The Cortex-M0 CPU in PSoC 4200 is part of the 32-bit MCU
subsystem, which is optimized for low-power operation with
extensive clock gating. It mostly uses 16-bit instructions and
executes a subset of the Thumb-2 instruction set. This enables
fully compatible binary upward migration of the code to higher
performance processors such as the Cortex-M3 and M4, thus
enabling upward compatibility. The Cypress implementation
includes a hardware multiplier that provides a 32-bit result in one
cycle. It includes a nested vectored interrupt controller (NVIC)
block with 32 interrupt inputs and also includes a Wakeup
Interrupt Controller (WIC). The WIC can wake the processor up
from the Deep Sleep mode, allowing power to be switched off to
the main processor when the chip is in the Deep Sleep mode.
The Cortex-M0 CPU provides a Non-Maskable Interrupt (NMI)
input, which is made available to the user when it is not in use
for system functions requested by the user.
The CPU also includes a debug interface, the serial wire debug
(SWD) interface, which is a 2-wire form of JTAG; the debug
configuration used for PSoC 4200 has four break-point (address)
comparators and two watchpoint (data) comparators.
Flash
The PSoC 4200 device has a flash module with a flash accelerator, tightly coupled to the CPU to improve average access
times from the flash block. The flash block is designed to deliver
1 wait-state (WS) access time at 48 MHz and with 0-WS access
time at 24 MHz. The flash accelerator delivers 85% of
single-cycle SRAM access performance on average. Part of the
flash module can be used to emulate EEPROM operation if
required.
The PSoC 4200 Flash supports the following flash protection
modes at the memory subsystem level:
■
Open: No Protection. Factory default mode in which the
product is shipped.
■
Protected: User may change from Open to Protected. This
mode disables Debug interface accesses. The mode can be
set back to Open but only after completely erasing the Flash.
■
Kill: User may change from Open to Kill. This mode disables
all Debug accesses. The part cannot be erased externally, thus
obviating the possibility of partial erasure by power interruption
and potential malfunction and security leaks. This is an irrecvocable mode.
In addition, row-level Read/Write protection is also supported to
prevent inadvertent Writes as well as selectively block Reads.
Flash Read/Write/Erase operations are always available for
internal code using system calls.
SRAM
SRAM memory is retained during Hibernate.
SROM
A supervisory ROM that contains boot and configuration routines
is provided.
Document Number: 001-87197 Rev. *J
The power system is described in detail in the section Power on
page 16. It provides assurance that voltage levels are as
required for each respective mode and either delay mode entry
(on power-on reset (POR), for example) until voltage levels are
as required for proper function or generate resets (brown-out
detect (BOD)) or interrupts (low-voltage detect (LVD)). The
PSoC 4200 operates with a single external supply over the range
of 1.71 to 5.5 V and has five different power modes, transitions
between which are managed by the power system. The
PSoC 4200 provides Sleep, Deep Sleep, Hibernate, and Stop
low-power modes.
Clock System
The PSoC 4200 clock system is responsible for providing clocks
to all subsystems that require clocks and for switching between
different clock sources without glitching. In addition, the clock
system ensures that no metastable conditions occur.
The clock system for PSoC 4200 consists of the internal main
oscillator (IMO) and the internal low-power oscillator (ILO) and a
provision for an external clock.
Figure 3. PSoC 4200 MCU Clocking Architecture
IMO
HFCLK
EXTCLK
ILO
HFCLK
LFCLK
Prescaler
SYSCLK
UDB
Dividers
UDBn
Analog
Divider
SAR clock
Peripheral
Dividers
PERXYZ_CLK
The HFCLK signal can be divided down (see PSoC 4200 MCU
Clocking Architecture) to generate synchronous clocks for the
UDBs, and the analog and digital peripherals. There are a total
of 12 clock dividers for PSoC 4200, each with 16-bit divide
capability; this allows eight to be used for the fixed-function
blocks and four for the UDBs. The analog clock leads the digital
clocks to allow analog events to occur before digital clock-related
noise is generated. The 16-bit capability allows a lot of flexibility
in generating fine-grained frequency values and is fully
supported in PSoC Creator. When UDB-generated pulse interrupts are used, SYSCLK must equal HFCLK.
Page 5 of 45
PSoC® 4: PSoC 4200
Family Datasheet
Analog Blocks
IMO Clock Source
The IMO is the primary source of internal clocking in PSoC 4200.
It is trimmed during testing to achieve the specified accuracy.
Trim values are stored in nonvolatile latches (NVL). Additional
trim settings from flash can be used to compensate for changes.
The IMO default frequency is 24 MHz and it can be adjusted
between 3 MHz to 48 MHz in steps of 1 MHz. The IMO tolerance
with Cypress-provided calibration settings is ±2%.
ILO Clock Source
The ILO is a very low-power oscillator, which is primarily used to
generate clocks for peripheral operation in Deep Sleep mode.
ILO-driven counters can be calibrated to the IMO to improve
accuracy. Cypress provides a software component, which does
the calibration.
Watchdog Timer
A watchdog timer is implemented in the clock block running from
the ILO; this allows watchdog operation during Deep Sleep and
generates a watchdog reset if not serviced before the timeout
occurs. The watchdog reset is recorded in the Reset Cause
register.
Reset
PSoC 4200 can be reset from a variety of sources including a
software reset. Reset events are asynchronous and guarantee
reversion to a known state. The reset cause is recorded in a
register, which is sticky through reset and allows software to
determine the cause of the Reset. An XRES pin is reserved for
external reset to avoid complications with configuration and
multiple pin functions during power-on or reconfiguration. The
XRES pin has an internal pull-up resistor that is always enabled.
Voltage Reference
The PSoC 4200 reference system generates all internally
required references. A 1% voltage reference spec is provided for
the 12-bit ADC. To allow better signal to noise ratios (SNR) and
better absolute accuracy, it is possible to bypass the internal
reference using a GPIO pin or to use an external reference for
the SAR.
12-bit SAR ADC
The 12-bit 1-Msps SAR ADC can operate at a maximum clock
rate of 18 MHz and requires a minimum of 18 clocks at that
frequency to do a 12-bit conversion.
The block functionality is augmented for the user by adding a
reference buffer to it (trimmable to ±1%) and by providing the
choice (for the PSoC-4200 case) of three internal voltage references: VDD, VDD/2, and VREF (nominally 1.024 V) as well as an
external reference through a GPIO pin. The sample-and-hold
(S/H) aperture is programmable allowing the gain bandwidth
requirements of the amplifier driving the SAR inputs, which
determine its settling time, to be relaxed if required. System
performance will be 65 dB for true 12-bit precision providing
appropriate references are used and system noise levels permit.
To improve performance in noisy conditions, it is possible to
provide an external bypass (through a fixed pin location) for the
internal reference amplifier.
The SAR is connected to a fixed set of pins through an 8-input
sequencer. The sequencer cycles through selected channels
autonomously (sequencer scan) and does so with zero switching
overhead (that is, aggregate sampling bandwidth is equal to
1 Msps whether it is for a single channel or distributed over
several channels). The sequencer switching is effected through
a state machine or through firmware driven switching. A feature
provided by the sequencer is buffering of each channel to reduce
CPU interrupt service requirements. To accommodate signals
with varying source impedance and frequency, it is possible to
have different sample times programmable for each channel.
Also, signal range specification through a pair of range registers
(low and high range values) is implemented with a corresponding
out-of-range interrupt if the digitized value exceeds the
programmed range; this allows fast detection of out-of-range
values without the necessity of having to wait for a sequencer
scan to be completed and the CPU to read the values and check
for out-of-range values in software.
The SAR is able to digitize the output of the on-board temperature sensor for calibration and other temperature-dependent
functions. The SAR is not available in Deep Sleep and Hibernate
modes as it requires a high-speed clock (up to 18 MHz). The
SAR operating range is 1.71 V to 5.5 V.
Figure 4. SAR ADC System Diagram
AHB System Bus and Programmable Logic
Interconnect
SAR Sequencer
vminus vplus
P7
Port 2 (8 inputs)
SARMUX
P0
Sequencing
and Control
Data and
Status Flags
POS
SARADC
NEG
External
Reference
and
Bypass
(optional)
Reference
Selection
VDD/2
VDDD
VREF
Inputs from other Ports
Document Number: 001-87197 Rev. *J
Page 6 of 45
PSoC® 4: PSoC 4200
Family Datasheet
Figure 5. UDB Array
Two Opamps (CTBm Block)
S y s te m
In te rc o n n e c t
CPU
S u b -s y s te m
C lo c k s
8 to 3 2
4 to 8
U D B IF
B U S IF
Other Digital
Signals in Chip
Temperature Sensor
PSoC 4200 has one on-chip temperature sensor This consists
of a diode, which is biased by a current source that can be
disabled to save power. The temperature sensor is connected to
the ADC, which digitizes the reading and produces a temperature value using Cypress supplied software that includes
calibration and linearization.
IR Q IF
C L K IF
PP
oPrt
IFIF
oortrt
IF
DSI
R o u tin g
C h a n n e ls
High-Speed I/O Matrix
PSoC 4200 has two opamps with Comparator modes which
allow most common analog functions to be performed on-chip
eliminating external components; PGAs, voltage buffers, filters,
trans-impedance amplifiers, and other functions can be realized
with external passives saving power, cost, and space. The
on-chip opamps are designed with enough bandwidth to drive
the S/H circuit of the ADC without requiring external buffering.
DSI
UDB
UDB
UDB
UDB
Low-power Comparators
PSoC 4200 has a pair of low-power comparators, which can also
operate in the Deep Sleep and Hibernate modes. This allows the
analog system blocks to be disabled while retaining the ability to
monitor external voltage levels during low-power modes. The
comparator outputs are normally synchronized to avoid metastability unless operating in an asynchronous power mode
(Hibernate) where the system wake-up circuit is activated by a
comparator switch event.
DSI
DSI
P ro g ra m m a b le D ig ita l S u b sy s te m
UDBs can be clocked from a clock divider block, from a port
interface (required for peripherals such as SPI), and from the DSI
network directly or after synchronization.
Programmable Digital
Universal Digital Blocks (UDBs) and Port Interfaces
A port interface is defined, which acts as a register that can be
clocked with the same source as the PLDs inside the UDB array.
This allows faster operation because the inputs and outputs can
be registered at the port interface close to the I/O pins and at the
edge of the array. The port interface registers can be clocked by
one of the I/Os from the same port. This allows interfaces such
as SPI to operate at higher clock speeds by eliminating the delay
for the port input to be routed over DSI and used to register other
inputs (see Figure 6).
PSoC 4200 has four UDBs; the UDB array also provides a
switched Digital System Interconnect (DSI) fabric that allows
signals from peripherals and ports to be routed to and through
the UDBs for communication and control. The UDB array is
shown in the following figure.
The UDBs can generate interrupts (one UDB at a time) to the
interrupt controller. The UDBs retain the ability to connect to any
pin on the chip through the DSI.
Figure 6. Port Interface
High Speed I/O Matrix
To Clock
Tree
8
Input Registers
7
Digital
GlobalClocks
3 DSI Signals ,
1 I/O Signal
6
Clock Selector
Block from
UDB
2
Reset Selector
Block from
UDB
2
0
6
...
Enables
0
3
2
[1]
8
Document Number: 001-87197 Rev. *J
7
[0]
1
0
[1]
4
8
[1]
[0]
To DSI
4
Output Registers
...
9
4
8
8
From DSI
[1]
From DSI
Page 7 of 45
PSoC® 4: PSoC 4200
Family Datasheet
Fixed Function Digital
■
Timer/Counter/PWM Block (TCPWM)
The TCPWM block consists of four 16-bit counters with
user-programmable period length. There is a Capture register to
record the count value at the time of an event (which may be an
I/O event), a period register used to either stop or auto-reload the
counter when its count is equal to the period register, and
compare registers to generate compare value signals which are
used as PWM duty cycle outputs. The block also provides true
and complementary outputs with programmable offset between
them to allow use as deadband programmable complementary
PWM outputs. It also has a Kill input to force outputs to a predetermined state; for example, this is used in motor drive systems
when an overcurrent state is indicated and the PWMs driving the
FETs need to be shut off immediately with no time for software
intervention.
Serial Communication Blocks (SCB)
PSoC 4200 has two SCBs, which can each implement an I2C,
UART, or SPI interface.
I2C Mode: The hardware I2C block implements a full
multi-master and slave interface (it is capable of multimaster
arbitration). This block is capable of operating at speeds of up to
1 Mbps (Fast Mode Plus) and has flexible buffering options to
reduce interrupt overhead and latency for the CPU. The FIFO
mode is available in all channels and is very useful in the
absence of DMA.
The I2C peripheral is compatible with the I2C Standard-mode,
Fast-mode, and Fast-Mode Plus devices as defined in the NXP
I2C-bus specification and user manual (UM10204). The I2C bus
I/O is implemented with GPIO in open-drain modes. The I2C bus
uses open-drain drivers for clock and data with pull-up resistors
on the bus for clock and data connected to all nodes. The
required Rise and Fall times for different I2C speeds are
guaranteed by using appropriate pull-up resistor values
depending on VDD, Bus Capacitance, and resistor tolerance.
For detailed information on how to calculate the optimum pull-up
resistor value for your design, refer to the UM10204 I2C bus
specification and user manual (the latest revision is available at
www.nxp.com).
PSoC 4200 is not completely compliant with the I2C spec in the
following respects:
■
GPIO cells are not overvoltage-tolerant and, therefore, cannot
be hot-swapped or powered up independently of the rest of the
I2C system.
■
Fast-Mode Plus has an IOL specification of 20 mA at a VOL of
0.4 V. The GPIO cells can sink a maximum of 8-mA IOL with a
VOL maximum of 0.6 V.
■
Fast mode and Fast-Mode Plus specify minimum Fall times,
which are not met with the GPIO cell; Slow strong mode can
help meet this spec depending on the Bus Load.
■
When the SCB is an I2C master, it interposes an IDLE state
between NACK and Repeated Start; the I2C spec defines Bus
free as following a Stop condition so other Active Masters do
not intervene but a Master that has just become activated may
start an Arbitration cycle.
Document Number: 001-87197 Rev. *J
When the SCB is in I2C slave mode, and Address Match on
External Clock is enabled (EC_AM = 1) along with operation in
the internally clocked mode (EC_OP = 0), then its I2C address
must be even.
UART Mode: This is a full-feature UART operating at up to
1 Mbps. It supports automotive single-wire interface (LIN),
infrared interface (IrDA), and SmartCard (ISO7816) protocols, all
of which are minor variants of the basic UART protocol. In
addition, it supports the 9-bit multiprocessor mode that allows
addressing of peripherals connected over common RX and TX
lines. Common UART functions such as parity error, break
detect, and frame error are supported. An 8-deep FIFO allows
much greater CPU service latencies to be tolerated. Note that
hardware handshaking is not supported. This is not commonly
used and can be implemented with a UDB-based UART in the
system, if required.
SPI Mode: The SPI mode supports full Motorola SPI, TI SSP
(essentially adds a start pulse used to synchronize SPI Codecs),
and National Microwire (half-duplex form of SPI). The SPI block
can use the FIFO.
GPIO
PSoC 4200 has 36 GPIOs. The GPIO block implements the
following:
■
Eight drive strength modes:
❐ Analog input mode (input and output buffers disabled)
❐ Input only
❐ Weak pull-up with strong pull-down
❐ Strong pull-up with weak pull-down
❐ Open drain with strong pull-down
❐ Open drain with strong pull-up
❐ Strong pull-up with strong pull-down
❐ Weak pull-up with weak pull-down
■
Input threshold select (CMOS or LVTTL).
■
Individual control of input and output buffer enabling/disabling
in addition to the drive strength modes.
■
Hold mode for latching previous state (used for retaining I/O
state in Deep Sleep mode and Hibernate modes).
■
Selectable slew rates for dV/dt related noise control to improve
EMI.
The pins are organized in logical entities called ports, which are
8-bit in width. During power-on and reset, the blocks are forced
to the disable state so as not to crowbar any inputs and/or cause
excess turn-on current. A multiplexing network known as a
high-speed I/O matrix is used to multiplex between various
signals that may connect to an I/O pin. Pin locations for
fixed-function peripherals are also fixed to reduce internal multiplexing complexity (these signals do not go through the DSI
network). DSI signals are not affected by this and any pin may
be routed to any UDB through the DSI network.
Data output and pin state registers store, respectively, the values
to be driven on the pins and the states of the pins themselves.
Every I/O pin can generate an interrupt if so enabled and each
I/O port has an interrupt request (IRQ) and interrupt service
routine (ISR) vector associated with it (5 for PSoC 4200 since it
has 4.5 ports).
Page 8 of 45
PSoC® 4: PSoC 4200
Family Datasheet
Special Function Peripherals
LCD Segment Drive
PSoC 4200 has an LCD controller which can drive up to four
commons and up to 32 segments. It uses full digital methods to
drive the LCD segments requiring no generation of internal LCD
voltages. The two methods used are referred to as digital correlation and PWM.
Digital correlation pertains to modulating the frequency and
levels of the common and segment signals to generate the
highest RMS voltage across a segment to light it up or to keep
the RMS signal zero. This method is good for STN displays but
may result in reduced contrast with TN (cheaper) displays.
PWM pertains to driving the panel with PWM signals to effectively use the capacitance of the panel to provide the integration
of the modulated pulse-width to generate the desired LCD
voltage. This method results in higher power consumption but
can result in better results when driving TN displays. LCD
operation is supported during Deep Sleep refreshing a small
display buffer (4 bits; 1 32-bit register per port).
CapSense
CapSense is supported on all pins in PSoC 4200 through a
CapSense Sigma-Delta (CSD) block that can be connected to
any pin through an analog mux bus that any GPIO pin can be
connected to via an Analog switch. CapSense function can thus
be provided on any pin or group of pins in a system under
software control. A component is provided for the CapSense
block to make it easy for the user.
Shield voltage can be driven on another Mux Bus to provide
water tolerance capability. Water tolerance is provided by driving
the shield electrode in phase with the sense electrode to keep
the shield capacitance from attenuating the sensed input.
Document Number: 001-87197 Rev. *J
The CapSense block has two IDACs which can be used for
general purposes if CapSense is not being used.(both IDACs are
available in that case) or if CapSense is used without water
tolerance (one IDAC is available).
WLCSP Package Bootloader
The WLCSP package is supplied with an I2C Bootloader
installed in flash. The bootloader is compatible with PSoC
Creator bootloadable project files and has the following default
settings:
■
I2C SCL and SDA connected to port pins P4.0 and P4.1 respectively (external pull-up resistors required)
■
I2C Slave mode, address 8, data rate = 100 kbps
■
Single application
■
Wait two seconds for bootload command
■
Other bootloader options are as set by the PSoC Creator
Bootloader Component default
■
Occupies the bottom 4.5 KB of flash
For more information on this bootloader, see the following
Cypress application note:
AN73854 - Introduction to Bootloaders
Note that a PSoC Creator bootloadable project must be
associated with .hex and .elf files for a bootloader project that is
configured for the target device. Bootloader .hex and .elf files can
be found at http://www.cypress.com/?rID=78632. The
factory-installed bootloader can be overwritten using JTAG or
SWD programming.
Page 9 of 45
PSoC® 4: PSoC 4200
Family Datasheet
Pinouts
The following is the pin-list for the PSoC 4200 (44-TQFP, 40-QFN, 28-SSOP, and 48-TQFP). Port 2 comprises of the high-speed Analog inputs for the SAR Mux. P1.7 is the
optional external input and bypass for the SAR reference. Ports 3 and 4 contain the Digital Communication channels. All pins support CSD CapSense and Analog Mux Bus
connections.
44-TQFP
40-QFN
28-SSOP
48-TQFP
Alternate Functions for Pins
Pin Description
Pin
Name
Pin
Name
Pin
Name
Pin
1
VSS
–
–
–
–
–
2
P2.0
1
P2.0
–
–
2
3
P2.1
2
P2.1
–
–
3
4
P2.2
3
P2.2
5
P2.2
5
P2.3
4
P2.3
6
P2.3
6
P2.4
5
P2.4
7
7
P2.5
6
P2.5
8
P2.6
7
9
P2.7
8
10
VSS
–
–
Name
Analog
Alt 1
Alt 2
Alt 3
Alt 4
–
–
–
–
–
–
Ground
P2.0
sarmux.0
–
–
–
–
Port 2 Pin 0: gpio, lcd, csd, sarmux
P2.1
sarmux.1
–
–
–
–
Port 2 Pin 1: gpio, lcd, csd, sarmux
4
P2.2
sarmux.2
–
–
–
–
Port 2 Pin 2: gpio, lcd, csd, sarmux
5
P2.3
sarmux.3
–
–
–
–
Port 2 Pin 3: gpio, lcd, csd, sarmux
P2.4
6
P2.4
sarmux.4
tcpwm0_p[1]
–
–
–
Port 2 Pin 4: gpio, lcd, csd, sarmux, pwm
8
P2.5
7
P2.5
sarmux.5
tcpwm0_n[1]
–
–
–
Port 2 Pin 5: gpio, lcd, csd, sarmux, pwm
P2.6
9
P2.6
8
P2.6
sarmux.6
tcpwm1_p[1]
–
–
–
Port 2 Pin 6: gpio, lcd, csd, sarmux, pwm
P2.7
10
P2.7
9
P2.7
sarmux.7
tcpwm1_n[1]
–
–
–
Port 2 Pin 7: gpio, lcd, csd, sarmux, pwm
9
VSS
–
–
–
–
–
–
–
–
–
Ground
–
–
–
–
10
NC
–
–
–
–
–
No Connect
No Connect
–
–
–
–
–
–
11
NC
–
–
–
–
–
11
P3.0
10
P3.0
11
P3.0
12
P3.0
–
tcpwm0_p[0]
scb1_uart_rx[0]
scb1_i2c_scl[0]
scb1_spi_mosi[0]
Port 3 Pin 0: gpio, lcd, csd, pwm, scb1
12
P3.1
11
P3.1
12
P3.1
13
P3.1
–
tcpwm0_n[0]
scb1_uart_tx[0]
scb1_i2c_sda[0]
scb1_spi_miso[0]
Port 3 Pin 1: gpio, lcd, csd, pwm, scb1
13
P3.2
12
P3.2
13
P3.2
14
P3.2
–
tcpwm1_p[0]
–
swd_io[0]
scb1_spi_clk[0]
Port 3 Pin 2: gpio, lcd, csd, pwm, scb1,
swd
–
–
–
–
–
–
15
VSSD
–
–
–
–
–
14
P3.3
13
P3.3
14
P3.3
16
P3.3
–
tcpwm1_n[0]
–
swd_clk[0]
15
P3.4
14
P3.4
–
–
17
P3.4
–
tcpwm2_p[0]
–
–
scb1_spi_ssel_1
Port 3 Pin 4: gpio, lcd, csd, pwm, scb1
16
P3.5
15
P3.5
–
–
18
P3.5
–
tcpwm2_n[0]
–
–
scb1_spi_ssel_2
Port 3 Pin 5: gpio, lcd, csd, pwm, scb1
17
P3.6
16
P3.6
–
–
19
P3.6
–
tcpwm3_p[0]
–
–
scb1_spi_ssel_3
18
P3.7
17
P3.7
–
–
20
P3.7
–
tcpwm3_n[0]
–
–
–
Port 3 Pin 7: gpio, lcd, csd, pwm
19
VDDD
–
–
–
–
21
VDDD
–
–
–
–
–
Digital Supply, 1.8 - 5.5V
20
P4.0
18
P4.0
15
P4.0
22
P4.0
–
–
scb0_uart_rx
scb0_i2c_scl
scb0_spi_mosi
Port 4 Pin 0: gpio, lcd, csd, scb0
21
P4.1
19
P4.1
16
P4.1
23
P4.1
–
–
scb0_uart_tx
scb0_i2c_sda
scb0_spi_miso
Port 4 Pin 1: gpio, lcd, csd, scb0
22
P4.2
20
P4.2
17
P4.2
24
P4.2
csd_c_mod
–
–
–
scb0_spi_clk
Port 4 Pin 2: gpio, lcd, csd, scb0
23
P4.3
21
P4.3
18
P4.3
25
P4.3
csd_c_sh_tank
–
–
–
scb0_spi_ssel_0
–
–
–
–
–
–
26
NC
–
–
–
–
–
No Connect
–
–
–
–
–
–
27
NC
–
–
–
–
–
No Connect
Document Number: 001-87197 Rev. *J
Ground
scb1_spi_ssel_0[0] Port 3 Pin 3: gpio, lcd, csd, pwm, scb1,
swd
Port 3 Pin 6: gpio, lcd, csd, pwm, scb1
Port 4 Pin 3: gpio, lcd, csd, scb0
Page 10 of 45
PSoC® 4: PSoC 4200
Family Datasheet
44-TQFP
40-QFN
28-SSOP
48-TQFP
Alternate Functions for Pins
Pin Description
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Analog
Alt 1
Alt 2
Alt 3
Alt 4
24
P0.0
22
P0.0
19
P0.0
28
P0.0
comp1_inp
–
–
–
scb0_spi_ssel_1
Port 0 Pin 0: gpio, lcd, csd, scb0, comp
25
P0.1
23
P0.1
20
P0.1
29
P0.1
comp1_inn
–
–
–
scb0_spi_ssel_2
Port 0 Pin 1: gpio, lcd, csd, scb0, comp
26
P0.2
24
P0.2
21
P0.2
30
P0.2
comp2_inp
–
–
–
scb0_spi_ssel_3
27
P0.3
25
P0.3
22
P0.3
31
P0.3
comp2_inn
–
–
–
–
Port 0 Pin 3: gpio, lcd, csd, comp
28
P0.4
26
P0.4
–
–
32
P0.4
–
–
scb1_uart_rx[1]
scb1_i2c_scl[1]
scb1_spi_mosi[1]
Port 0 Pin 4: gpio, lcd, csd, scb1
Port 0 Pin 2: gpio, lcd, csd, scb0, comp
29
P0.5
27
P0.5
–
–
33
P0.5
–
–
scb1_uart_tx[1]
scb1_i2c_sda[1]
scb1_spi_miso[1]
30
P0.6
28
P0.6
23
P0.6
34
P0.6
–
ext_clk
–
–
scb1_spi_clk[1]
Port 0 Pin 5: gpio, lcd, csd, scb1
31
P0.7
29
P0.7
24
P0.7
35
P0.7
–
–
–
wakeup
32
XRES
30
XRES
25
XRES
36
XRES
–
–
–
–
–
Chip reset, active low
33
VCCD
31
VCCD
26
VCCD
37
VCCD
–
–
–
–
–
Regulated supply, connect to 1µF cap or
1.8V
Port 0 Pin 6: gpio, lcd, csd, scb1, ext_clk
scb1_spi_ssel_0[1] Port 0 Pin 7: gpio, lcd, csd, scb1, wakeup
–
–
–
–
–
–
38
VSSD
–
–
–
–
–
Digital Ground
34
VDDD
32
VDDD
27
VDD
39
VDDD
–
–
–
–
–
Digital Supply, 1.8 - 5.5V
35
VDDA
33
VDDA
27
VDD
40
VDDA
–
–
–
–
–
Analog Supply, 1.8 - 5.5V, equal to VDDD
36
VSSA
34
VSSA
28
VSS
41
VSSA
–
–
–
–
–
Analog Ground
37
P1.0
35
P1.0
1
P1.0
42
P1.0
ctb.oa0.inp
tcpwm2_p[1]
–
–
–
Port 1 Pin 0: gpio, lcd, csd, ctb, pwm
38
P1.1
36
P1.1
2
P1.1
43
P1.1
ctb.oa0.inm
tcpwm2_n[1]
–
–
–
Port 1 Pin 1: gpio, lcd, csd, ctb, pwm
39
P1.2
37
P1.2
3
P1.2
44
P1.2
ctb.oa0.out
tcpwm3_p[1]
–
–
–
Port 1 Pin 2: gpio, lcd, csd, ctb, pwm
40
P1.3
38
P1.3
–
–
45
P1.3
ctb.oa1.out
tcpwm3_n[1]
–
–
–
Port 1 Pin 3: gpio, lcd, csd, ctb, pwm
41
P1.4
39
P1.4
–
–
46
P1.4
ctb.oa1.inm
–
–
–
–
Port 1 Pin 4: gpio, lcd, csd, ctb
42
P1.5
–
–
–
–
47
P1.5
ctb.oa1.inp
–
–
–
–
Port 1 Pin 5: gpio, lcd, csd, ctb
43
P1.6
–
–
–
–
48
P1.6
ctb.oa0.inp_alt
–
–
–
–
Port 1 Pin 6: gpio, lcd, csd
44
P1.7/VREF
40
P1.7/VREF
4
P1.7/VREF
1
P1.7/VREF ctb.oa1.inp_alt
ext_vref
–
–
–
–
Port 1 Pin 7: gpio, lcd, csd, ext_ref
Notes:
1. tcpwm_p and tcpwm_n refer to tcpwm non-inverted and inverted outputs respectively.
2. P3.2 and P3.3 are SWD pins after boot (reset).
Document Number: 001-87197 Rev. *J
Page 11 of 45
PSoC® 4: PSoC 4200
Family Datasheet
The following is the pin-list for the PSoC 4200 (35-WLCSP).
35-Ball CSP
Pin
Name
Alternate Functions for Pins
Analog
Alt 1
Alt 2
Alt 3
Pin Description
Alt 4
D3
P2.2
sarmux.2
–
–
–
–
Port 2 Pin 2: gpio, lcd, csd, sarmux
E4
P2.3
sarmux.3
–
–
–
–
Port 2 Pin 3: gpio, lcd, csd, sarmux
E5
P2.4
sarmux.4
tcpwm0_p[1]
–
–
–
Port 2 Pin 4: gpio, lcd, csd, sarmux, pwm
E6
P2.5
sarmux.5
tcpwm0_n[1]
–
–
–
Port 2 Pin 5: gpio, lcd, csd, sarmux, pwm
E3
P2.6
sarmux.6
tcpwm1_p[1]
–
–
–
Port 2 Pin 6: gpio, lcd, csd, sarmux, pwm
E2
P2.7
sarmux.7
tcpwm1_n[1]
–
–
–
Port 2 Pin 7: gpio, lcd, csd, sarmux, pwm
E1
P3.0
–
tcpwm0_p[0]
scb1_uart_rx[0] scb1_i2c_scl[0]
scb1_uart_tx[0] scb1_i2c_sda[0] scb1_spi_miso[0] Port 3 Pin 1: gpio, lcd, csd, pwm, scb1
scb1_spi_mosi[0] Port 3 Pin 0: gpio, lcd, csd, pwm, scb1
D2
P3.1
–
tcpwm0_n[0]
D1
P3.2
–
tcpwm1_p[0]
–
swd_io[0]
scb1_spi_clk[0]
B7
VSS
–
–
–
–
–
C1
P3.3
–
tcpwm1_n[0]
–
swd_clk[0]
C2
P3.4
–
tcpwm2_p[0]
-
–
scb1_spi_ssel_1
B1
P4.0
–
–
scb0_uart_rx
scb0_i2c_scl
scb0_spi_mosi
Port 4 Pin 0: gpio, lcd, csd, scb0
B2
P4.1
–
–
scb0_uart_tx
scb0_i2c_sda
scb0_spi_miso
Port 4 Pin 1: gpio, lcd, csd, scb0
A2
P4.2
csd_c_mod
–
–
–
scb0_spi_clk
Port 4 Pin 2: gpio, lcd, csd, scb0
Port 3 Pin 2: gpio, lcd, csd, pwm, scb1, swd
Ground
scb1_spi_ssel_0[0] Port 3 Pin 3: gpio, lcd, csd, pwm, scb1, swd
Port 3 Pin 4: gpio, lcd, csd, pwm, scb1
A1
P4.3
csd_c_sh_tank
–
–
–
scb0_spi_ssel_0
Port 4 Pin 3: gpio, lcd, csd, scb0
C3
P0.0
comp1_inp
–
–
–
scb0_spi_ssel_1
Port 0 Pin 0: gpio, lcd, csd, scb0, comp
A5
P0.1
comp1_inn
–
–
–
scb0_spi_ssel_2
Port 0 Pin 1: gpio, lcd, csd, scb0, comp
A4
P0.2
comp2_inp
–
–
–
scb0_spi_ssel_3
Port 0 Pin 2: gpio, lcd, csd, scb0, comp
A3
P0.3
comp2_inn
–
–
–
B3
P0.4
–
–
scb1_uart_rx[1] scb1_i2c_scl[1]
A6
P0.5
–
–
scb1_uart_tx[1] scb1_i2c_sda[1] scb1_spi_miso[1] Port 0 Pin 5: gpio, lcd, csd, scb1
B4
P0.6
–
ext_clk
–
–
B5
P0.7
–
–
–
wakeup
–
Port 0 Pin 3: gpio, lcd, csd, comp
scb1_spi_mosi[1] Port 0 Pin 4: gpio, lcd, csd, scb1
scb1_spi_clk[1]
Port 0 Pin 6: gpio, lcd, csd, scb1, ext_clk
scb1_spi_ssel_0[1] Port 0 Pin 7: gpio, lcd, csd, scb1, wakeup
B6
XRES
–
–
–
–
–
Chip reset, active low
A7
VCCD
–
–
–
–
–
Regulated supply, connect to 1µF cap or 1.8V
C7
VDD
–
–
–
–
–
Supply, 1.8 - 5.5V
C4
P1.0
ctb.oa0.inp
tcpwm2_p[1]
–
–
–
Port 1 Pin 0: gpio, lcd, csd, ctb, pwm
C5
P1.1
ctb.oa0.inm
tcpwm2_n[1]
–
–
–
Port 1 Pin 1: gpio, lcd, csd, ctb, pwm
C6
P1.2
ctb.oa0.out
tcpwm3_p[1]
–
–
–
Port 1 Pin 2: gpio, lcd, csd, ctb, pwm
Document Number: 001-87197 Rev. *J
Page 12 of 45
PSoC® 4: PSoC 4200
Family Datasheet
35-Ball CSP
Alternate Functions for Pins
Pin Description
Pin
Name
Analog
Alt 1
Alt 2
Alt 3
Alt 4
D7
P1.3
ctb.oa1.out
tcpwm3_n[1]
–
–
–
Port 1 Pin 3: gpio, lcd, csd, ctb, pwm
D4
P1.4
ctb.oa1.inm
–
–
–
–
Port 1 Pin 4: gpio, lcd, csd, ctb
D5
P1.5
ctb.oa1.inp
–
–
–
–
Port 1 Pin 5: gpio, lcd, csd, ctb
P1.6
ctb.oa0.inp_alt
–
–
–
–
Port 1 Pin 6: gpio, lcd, csd
P1.7/VR ctb.oa1.inp_alt
EF
ext_vref
–
–
–
–
Port 1 Pin 7: gpio, lcd, csd, ext_ref
D6
E7
Descriptions of the Pin functions are as follows:
VDDD: Power supply for both analog and digital sections (where there is no VDDA pin).
VDDA: Analog VDD pin where package pins allow; shorted to VDDD otherwise.
VSSA: Analog ground pin where package pins allow; shorted to VSS otherwise
VSS: Ground pin.
VCCD: Regulated Digital supply (1.8 V ±5%).
Port Pins can all be used as LCD Commons, LCD Segment drivers, or CSD sense and shield pins can be connected to AMUXBUS A or B or can all be used as GPIO pins
that can be driven by firmware or DSI signals.
The following packages are supported: 48-pin TQFP, 44-pin TQFP, 40-pin QFN, and 28-pin SSOP.
Document Number: 001-87197 Rev. *J
Page 13 of 45
PSoC® 4: PSoC 4200
Family Datasheet
Figure 7. 48-Pin TQFP Pinout
36 VSSA
35 VD DA
34 VD DD
(GPIO)P1[3]
(GPIO)P1[2]
(GPIO)P1[1]
(GPIO)P1[0]
40
39
38
37
(GPIO)P1[7]
44
Document Number: 001-87197 Rev. *J
1
2
3
4
5
6
33
32
31
30
29
TQFP
(Top View)
28
27
26
25
24
23
VCCD
XRES
(GPIO) P0[7]
(GPIO)
(GPIO)
(GPIO)
(GPIO)
(GPIO)
(GPIO)
( GPIO)
( GPIO)
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
P0[1]
P0[0]
P4[3]
(GPIO) P4[0]
(GPIO) P4[1]
(GPIO) P4[2]
16
17
18
19
20
21
22
(GPIO) P3[5]
(GPIO) P3[6]
(GPIO) P3[7]
VDD D
12
13
14
15
(GPIO) P3[1]
7
8
9
10
11
(GPIO) P3[2]
(GPIO) P3[3]
(GPIO) P3[4]
VSS
(GPIO) P2[ 0]
(GPIO) P2[1]
(GPIO) P2[2]
(GPIO) P2[3]
(GPIO) P2[4]
(GPIO) P2[5]
(GPIO) P2[6]
(GPIO) P2[7]
VSS
( GPIO) P3[0]
43 (GPIO)P1[6]
42 (GPIO)P1[5]
41 (GPIO)P1[4]
Figure 8. 44-pin TQFP Part Pinout
Page 14 of 45
PSoC® 4: PSoC 4200
Family Datasheet
40
39
38
37
36
35
34
33
32
31
(GPIO)P1[7]
(GPIO)P1[4]
(GPIO)P1[3]
(GPIO)P1[2]
(GPIO)P1[1]
(GPIO)P1[0]
VSSA
VDDA
VDDD
VCCD
Figure 9. 40-Pin QFN Pinout
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
QFN
(Top View)
XRES
(GPIO)P0[7]
(GPIO)P0[6]
(GPIO)P0[5]
(GPIO)P0[4]
(GPIO)P0[3]
(GPIO)P0[2]
(GPIO)P0[1]
(GPIO)P0[0]
(GPIO)P4[3]
(GPIO)P3[1]
(GPIO)P3[2]
(GPIO)P3[3]
(GPIO)P3[4]
(GPIO)P3[5]
(GPIO)P3[6]
(GPIO)P3[7]
(GPIO)P4[0]
(GPIO)P4[1]
(GPIO)P4[2]
11
12
13
14
15
16
17
18
19
20
(GPIO)P2[0]
(GPIO)P2[1]
(GPIO)P2[2]
(GPIO)P2[3]
(GPIO)P2[4]
(GPIO)P2[5]
(GPIO)P2[6]
(GPIO)P2[7]
VSS
(GPIO)P3[0]
Figure 10. 35-Ball WLCSP
7
6
5
4
3
2
1
A
VCCD
P0.5
P0.1
P0.2
P0.3
P4.2
P4.3
B
VSS
XRES
P0.7
P0.6
P0.4
P4.1
C
VDD
P1.2
P1.1
P1.0
P0.0
D
P1.3
P1.6
P1.5
P1.4
P2.5
P2.4
P2.3
E P1.7/VREF
1
2
3
4
5
6
7
A
P4.3
P4.2
P0.3
P0.2
P0.1
P0.5
VCCD
P4.0
B
P4.0
P4.1
P0.4
P0.6
P0.7
XRES
VSS
P3.4
P3.3
C
P3.3
P3.4
P0.0
P1.0
P1.1
P1.2
VDD
P2.2
P3.1
P3.2
D
P3.2
P3.1
P2.2
P1.4
P1.5
P1.6
P1.3
P2.6
P2.7
P3.0
E
P3.0
P2.7
P2.6
P2.3
P2.4
P2.5
P1.7/VREF
Balls Up View
Top View
Figure 11. 28-Pin SSOP Pinout
(GPIO)P1[0]
(GPIO)P1[1]
(GPIO)P1[2]
(GPIO)P1[7]
(GPIO)P2[2]
(GPIO)P2[3]
(GPIO)P2[4]
(GPIO)P2[5]
(GPIO)P2[6]
(GPIO)P2[7]
(GPIO)P3[0]
(GPIO)P3[1]
(GPIO)P3[2]
(GPIO)P3[3]
Document Number: 001-87197 Rev. *J
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SSOP
(Top View)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VSS
VDDD
VCCD
XRES
(GPIO)P0[7]
(GPIO)P0[6]
(GPIO)P0[3]
(GPIO)P0[2]
(GPIO)P0[1]
(GPIO)P0[0]
(GPIO)P4[3]
(GPIO)P4[2]
(GPIO)P4[1]
(GPIO)P4[0]
Page 15 of 45
PSoC® 4: PSoC 4200
Family Datasheet
Power
Figure 13. 48-TQFP Package Example
VDDA
VCCD
41
VDDD
42
VSSD
43
(GPIO) P1.0
(GPIO) P1.1
44
VSSA
(GPIO) P1.2
(GPIO) P1.5
(GPIO) P1.4
45
46
40
39
38
37
GROUND
35
(GPIO) P0.7
(GPIO) P2.1
3
34
(GPIO) P0.6
(GPIO) P2.2
4
(GPIO) P2.3
5
(GPIO) P2.4
6
(GPIO) P2.5
7
(GPIO) P2.6
8
(GPIO) P2.7
Top View
33
(GPIO) P0.5
32
(GPIO) P0.4
31
(GPIO) P0.3
30
(GPIO) P0.2
29
(GPIO) P0.1
(GPIO) P0.0
9
28
NC
10
27
NC
11
19
20
21
VDDD
22
23
24
(GPIO) P4.2
18
(GPIO) P4.1
17
(GPIO) P4.0
16
(GPIO) P3.7
VDDD
15
(GPIO) P3.6
14
GROUND
NC
(GPIO) P4.3
25
13
(GPIO) P3.4
12
C5 1 µF
NC
26
(GPIO) P3.5
(GPIO) P3.0
VSSA
48 TQFP
0.1 µF C4
VDDD
1.8 Volt
Reg
VCCD
C2 0.1 µF
XRES
36
2
VSSD
Analog
Domain
C3 1 µF
1 µF C1
(GPIO) P2.0
VDDA
Digital
Domain
47
(GPIO) P1.3
(GPIO) P1.6
48
(GPIO)P1.7/VREF1 ?
(GPIO) P3.3
VDDA
0.1 µF C4
GROUND
(GPIO) P3.1
Figure 12. PSoC 4 Power Supply
GROUND
(GPIO) P3.2
The following power system diagrams show the minimum set of
power supply pins as implemented for the PSoC 4200. The
system has one regulator in Active mode for the digital circuitry.
There is no analog regulator; the analog circuits run directly from
the VDDA input. There are separate regulators for the Deep Sleep
and Hibernate (lowered power supply and retention) modes.
There is a separate low-noise regulator for the bandgap. The
supply voltage range is 1.71 to 5.5 V with all functions and
circuits operating over that range.
C3 1 µF
GROUND
Figure 14. 44-TQFP Package Example
VSSD
C 3 1 µF
0.1 µF C4
VSS
VDDA and VDDD must be shorted together; the grounds, VSSA
and VSS must also be shorted together. Bypass capacitors must
be used from VDDD to ground, typical practice for systems in this
frequency range is to use a capacitor in the 1-µF range in parallel
with a smaller capacitor (0.1 µF for example). Note that these are
simply rules of thumb and that, for critical applications, the PCB
layout, lead inductance, and the bypass capacitor parasitic
should be simulated to design and obtain optimal bypassing.
(GPIO)P1[6]
(GPIO)P1[5]
(GPIO)P1[4]
(GPIO)P1[3]
(GPIO)P1[2]
(GPIO)P1[1]
(GPIO)P1[0]
21
22
(GPIO) P4[0]
(GPIO) P4[1]
(GPIO) P4[2]
33
32
31
30
29
28
27
26
25
24
23
C2 0 .1 µF
VSS
VC CD
XRES
(GP IO)
(GP IO)
(GP IO)
(GP IO)
(GP IO)
(GP IO)
(GP IO)
(GP IO)
(GP IO)
P0[7]
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
P0[1]
P0[0]
P4[3]
C 5 1 µF
VSS
C6 0.1 µF
VSS
Power Supply
VDDD–VSS
VDDA–VSSA
VCCD–VSS
VREF–VSSA
(optional)
Document Number: 001-87197 Rev. *J
39
38
37
VSSA 36
VDDA 35
VDDD 34
12
14
15
16
17
18
19 VDDD
20
VSS
13
In this mode, PSoC 4200 is powered by an external power supply
that can be anywhere in the range of 1.8 V to 5.5 V. This range
is also designed for battery-powered operation, for instance, the
chip can be powered from a battery system that starts at 3.5 V
and works down to 1.8 V. In this mode, the internal regulator of
PSoC 4200 supplies the internal logic and the VCCD output of
PSoC 4200 must be bypassed to ground via an external
capacitor (in the range of 1 µF to 1.6 µF; X5R ceramic or better).
(GPIO) P3[3]
(GPIO) P3[4]
(GPIO) P3[5]
(GPIO) P3[6]
(GPIO) P3[7]
Unregulated External Supply
(G PIO)P 3[0]
TQ FP
(Top View )
(GPIO) P3[2]
The PSoC 4200 family allows two distinct modes of power supply
operation: Unregulated External Supply and Regulated External
Supply modes.
1 V SS
2
3
4
5
6
7
8
9
10 VSS
11
1 µF C1
(GPIO) P3[1]
(G PIO )P 2[0]
(G PIO )P 2[1]
(GP IO )P 2[2]
(G PIO )P 2[3]
(G PIO )P2[4]
(G PIO )P 2[5]
(G PIO )P 2[6]
(G PIO )P 2[7]
42
41
40
44
43
(GPIO)P1[7]
V SS
Bypass Capacitors
0.1-µF ceramic at each pin (C2, C6) plus
bulk capacitor 1 µF to 10 µF (C1). Total
capacitance may be greater than 10 µF.
0.1-µF ceramic at pin (C4). Additional
1 µF to 10 µF (C3) bulk capacitor. Total
capacitance may be greater than 10 µF.
1-µF ceramic capacitor at the VCCD pin
(C5)
The internal bandgap may be bypassed
with a 1-µF to 10-µF capacitor. Total
capacitance may be greater than 10 µF.
Page 16 of 45
PSoC® 4: PSoC 4200
Family Datasheet
Note It is good practice to check the datasheets for your bypass
capacitors, specifically the working voltage and the DC bias
specifications. With some capacitors, the actual capacitance can
decrease considerably when the DC bias (VDDA, VDDD, or VCCD)
is a significant percentage of the rated working voltage. VDDA
must be equal to or higher than the VDDD supply when powering
up.
Figure 15. 40-pin QFN Example
0.1 µF C4
VSS
(GPIO)P1[7]
(GPIO)P1[4]
40
39
38
37
36
35
34
33
32
31
VSSA
VDDA
VDDD
VCCD
QFN
0.1 µF C2
C1 1µF
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SSOP
( Top View)
VSS 28
VDDD27
VCCD26
25
24
23
22
21
20
19
18
17
16
15
19
20
VSS
(GPIO) P4[1]
(GPIO) P4[2]
16
17
18
(GPIO) P4[0]
(GPIO) P3[3]
(GPIO) P3[4]
C5 1 µF
30 XRES
29 (GPIO) P0[7]
28 (GPIO) P0[6]
27 (GPIO) P0[5]
26 (GPIO) P0[4]
25 (GPIO) P0[3]
24 (GPIO) P0[2]
23 (GPIO) P0[1]
22 (GPIO) P0[0]
21 (GPIO) P4[3]
Regulated External Supply
Figure 16. 28-SSOP Example
(GPIO )P1[0]
(GPIO)P1[1]
(GPIO )P1[2]
( GPIO) P1[7]
( GPIO) P2[2]
(GPIO ) P2[3]
(GPIO ) P2[4]
(GPIO ) P2[5]
(GPIO) P2[6]
(GPIO) P2[7]
( GPIO) P3[0]
(GPIO )P3[1]
(GPIO )P3[2]
(GPIO )P3[3]
(GPIO) P3[2]
(GPIO) P3[1]
VSS
15
(Top View)
11
12
13
14
(GPIO) P3[0]
1
2
3
4
5
6
7
8
9 VSS
10
(GPIO) P3[5]
(GPIO) P3[6]
(GPIO) P3[7]
(GPIO) P2[6]
(GPIO) P2[7]
(GPIO)P1[3]
(GPIO)P1[2]
(GPIO)P1[1]
(GPIO)P1[0]
VSS
(GPIO) P2[0]
(GPIO) P2[1]
(GPIO) P2[2]
(GPIO) P2[3]
(GPIO) P2[4]
(GPIO) P2[5]
VSS
C2 0.1 µF
1µF C1
C3 1µF
VSS
XRES
( GPIO) P0[7]
( GPIO) P0[6]
( GPIO) P0[3]
( GPIO) P0[2]
( GPIO) P0[1]
( GPIO) P0[0]
( GPIO) P4[3]
( GPIO)P4[2]
( GPIO)P4[1]
( GPIO)P4[0]
Document Number: 001-87197 Rev. *J
In this mode, PSoC 4200 is powered by an external power supply
that must be within the range of 1.71 V to 1.89 V (1.8 ±5%); note
that this range needs to include power supply ripple too. In this
mode, VCCD, VDDA, and VDDD pins are all shorted together and
bypassed. The internal regulator is disabled in firmware.
C3 1µF
VSS
Page 17 of 45
PSoC® 4: PSoC 4200
Family Datasheet
Development Support
The PSoC 4200 family has a rich set of documentation, development tools, and online resources to assist you during your
development process. Visit www.cypress.com/go/psoc4 to find
out more.
Documentation
A suite of documentation supports the PSoC 4200 family to
ensure that you can find answers to your questions quickly. This
section contains a list of some of the key documents.
Software User Guide: A step-by-step guide for using PSoC
Creator. The software user guide shows you how the PSoC
Creator build process works in detail, how to use source control
with PSoC Creator, and much more.
Component Datasheets: The flexibility of PSoC allows the
creation of new peripherals (components) long after the device
has gone into production. Component data sheets provide all of
the information needed to select and use a particular component,
including a functional description, API documentation, example
code, and AC/DC specifications.
motor control and on-chip filtering. Application notes often
include example projects in addition to the application note
document.
Technical Reference Manual: The Technical Reference Manual
(TRM) contains all the technical detail you need to use a PSoC
device, including a complete description of all PSoC registers.
The TRM is available in the Documentation section at
www.cypress.com/psoc4.
Online
In addition to print documentation, the Cypress PSoC forums
connect you with fellow PSoC users and experts in PSoC from
around the world, 24 hours a day, 7 days a week.
Tools
With industry standard cores, programming, and debugging
interfaces, the PSoC 4200 family is part of a development tool
ecosystem. Visit us at www.cypress.com/go/psoccreator for the
latest information on the revolutionary, easy to use PSoC Creator
IDE, supported third party compilers, programmers, debuggers,
and development kits.
Application Notes: PSoC application notes discuss a particular
application of PSoC in depth; examples include brushless DC
Document Number: 001-87197 Rev. *J
Page 18 of 45
PSoC® 4: PSoC 4200
Family Datasheet
Electrical Specifications
Absolute Maximum Ratings
Table 1. Absolute Maximum Ratings[1]
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
SID1
VDDD_ABS
Digital supply relative to VSSD
–0.5
–
6
V
Absolute max
SID2
VCCD_ABS
Direct digital core voltage input relative
to Vssd
–0.5
–
1.95
V
Absolute max
SID3
VGPIO_ABS
GPIO voltage
–0.5
–
VDD+0.5
V
Absolute max
SID4
IGPIO_ABS
Maximum current per GPIO
–25
–
25
mA
Absolute max
SID5
IGPIO_injection GPIO injection current, Max for VIH >
VDDD, and Min for VIL < VSS
–0.5
–
0.5
mA
Absolute max,
current injected
per pin
BID44
ESD_HBM
Electrostatic discharge human body
model
2200
–
–
V
BID45
ESD_CDM
Electrostatic discharge charged device
model
500
–
–
V
BID46
LU
Pin current for latch-up
–200
–
200
mA
Device Level Specifications
All specifications are valid for –40 °C TA 105 °C and TJ 125 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
Table 2. DC Specifications
Spec ID#
Parameter
Details/
Conditions
With regulator enabled
Description
Min
Typ
Max
Units
Power Supply Input Voltage
(VDDA = VDDD = VDD)
Power Supply Input Voltage unregulated
1.8
–
5.5
V
1.71
1.8
1.89
V
SID54
VCCD
Output voltage (for core logic)
–
1.8
SID55
CEFC
External Regulator voltage bypass
1
1.3
SID56
CEXC
Power supply decoupling capacitor
–
1
Active Mode, VDD = 1.71 V to 5.5 V. Typical Values measured at VDD = 3.3 V
SID9
IDD4
Execute from Flash; CPU at 6 MHz
–
–
SID10
IDD5
Execute from Flash; CPU at 6 MHz
–
2.2
SID12
IDD7
Execute from Flash; CPU at 12 MHz,
–
–
SID13
IDD8
Execute from Flash; CPU at 12 MHz
–
3.7
SID16
IDD11
Execute from Flash; CPU at 24 MHz
–
6.7
SID17
IDD12
Execute from Flash; CPU at 24 MHz
–
–
SID19
IDD14
Execute from Flash; CPU at 48 MHz
–
12.8
SID20
IDD15
Execute from Flash; CPU at 48 MHz
–
–
Sleep Mode, VDD = 1.7 V to 5.5 V
–
1.3
SID25
IDD20
I2C wakeup, WDT, and Comparators on.
6 MHz.
SID25A
IDD20A
I2C wakeup, WDT, and Comparators on.
–
1.7
12 MHz
–
1.6
–
V
µF
µF
2.8
–
4.2
–
–
7.2
–
13.8
mA
mA
mA
mA
mA
mA
mA
mA
T = 25 °C
T = 25 °C
1.8
mA
VDD = 1.71 to 5.5 V.
2.2
mA
VDD = 1.71 to 5.5 V.
SID53
VDD
SID255
VDDD
Internally unregulated
supply
X5R ceramic or better
X5R ceramic or better
T = 25 °C
T = 25 °C
Note
1. Usage above the absolute maximum conditions listed in Table 1 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended
periods of time may affect device reliability. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature
Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification.
Document Number: 001-87197 Rev. *J
Page 19 of 45
PSoC® 4: PSoC 4200
Family Datasheet
Table 2. DC Specifications (continued)
Spec ID#
Parameter
Description
Typ
Max
Units
–
–
1.3
–
–
45
µA
µA
T = 25 °C
T = 85 °C
–
1.5
15
µA
Typ. at 25 °C. Max at 85
°C.
–
–
1.7
–
–
60
µA
µA
T = 25 °C
T = 85 °C
–
–
–
–
–
–
135
180
140
µA
µA
µA
VDD = 1.71 to 1.89
VDD = 1.8 to 3.6
VDD = 3.6 to 5.5
–
–
150
–
1000
nA
nA
T = 25 °C
T = 85 °C
–
150
–
nA
T = 25 °C
–
–
150
–
–
1000
nA
nA
T = 25 °C
T = 85 °C
–
–
–
–
–
–
19.4
17
16
µA
µA
µA
VDD = 1.71 to 1.89
VDD = 1.8 to 3.6
VDD = 3.6 to 5.5
–
20
80
nA
Typ. at 25 °C. Max at 85
°C.
Stop Mode current; VDD = 3.6 V
–
–
5645
nA
Supply current while XRES asserted
–
2
5
mA
Min
Typ
Max
Units
Details/
Conditions
DC
–
48
MHz
1.71 VDD 5.5
Deep Sleep Mode, VDD = 1.8 V to 3.6 V (Regulator on)
SID31
IDD26
I2C wakeup and WDT on.
SID32
IDD27
I2C wakeup and WDT on.
Deep Sleep Mode, VDD = 3.6 V to 5.5 V
SID34
IDD29
I2C wakeup and WDT on
Deep Sleep Mode, VDD = 1.71 V to 1.89 V (Regulator bypassed)
SID37
IDD32
I2C wakeup and WDT on.
SID38
IDD33
I2C wakeup and WDT on
Deep Sleep Mode, +105 °C
SID33Q
IDD28Q
I2C wakeup and WDT on. Regulator Off.
SID34Q
IDD29Q
I2C wakeup and WDT on.
SID35Q
IDD30Q
I2C wakeup and WDT on.
Hibernate Mode, VDD = 1.8 V to 3.6 V (Regulator on)
SID40
IDD35
GPIO and Reset active
SID41
IDD36
GPIO and Reset active
Hibernate Mode, VDD = 3.6 V to 5.5 V
SID43
IDD38
GPIO and Reset active
Hibernate Mode, VDD = 1.71 V to 1.89 V (Regulator bypassed)
SID46
IDD41
GPIO and Reset active
SID47
IDD42
GPIO and Reset active
Hibernate Mode, +105 °C
SID42Q
IDD37Q
Regulator Off
SID43Q
IDD38Q
SID44Q
IDD39Q
Stop Mode
SID304
IDD43A
Stop Mode current; VDD = 3.3 V
Stop Mode, +105 °C
SID304Q
IDD43AQ
XRES current
SID307
IDD_XR
Details/
Conditions
Min
Table 3. AC Specifications
Spec ID#
Parameter
Description
SID48
FCPU
CPU frequency
SID49
TSLEEP
Wakeup from sleep mode
–
0
–
µs
Guaranteed by
characterization
SID50
TDEEPSLEEP
Wakeup from Deep Sleep mode
–
–
25
µs
24 MHz IMO.
Guaranteed by
characterization
SID51
THIBERNATE
Wakeup from Hibernate and Stop
modes
–
–
2
ms
Guaranteed by
characterization
SID52
TRESETWIDTH External reset pulse width
1
–
–
µs
Guaranteed by
characterization
Document Number: 001-87197 Rev. *J
Page 20 of 45
PSoC® 4: PSoC 4200
Family Datasheet
GPIO
Table 4. GPIO DC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
SID57
VIH[2]
Input voltage high threshold
0.7 ×
VDDD
–
–
V
CMOS Input
SID58
VIL
Input voltage low threshold
–
–
0.3 ×
VDDD
V
CMOS Input
SID241
VIH[2]
LVTTL input, VDDD < 2.7 V
0.7×
VDDD
–
–
V
SID242
VIL
LVTTL input, VDDD < 2.7 V
–
–
0.3 ×
VDDD
V
SID243
VIH[2]
LVTTL input, VDDD 2.7 V
2.0
–
–
V
SID244
VIL
LVTTL input, VDDD 2.7 V
–
–
0.8
V
SID59
VOH
Output voltage high level
VDDD
–0.6
–
–
V
IOH = 4 mA at
3-V VDDD
SID60
VOH
Output voltage high level
VDDD
–0.5
–
–
V
IOH = 1 mA at
1.8-V VDDD
SID61
VOL
Output voltage low level
–
–
0.4
V
IOL = 4 mA at
1.8-V VDDD
SID62
VOL
Output voltage low level
–
–
0.6
V
IOL = 8 mA at 3-V
VDDD
SID62A
VOL
Output voltage low level
–
–
0.4
V
IOL = 3 mA at 3-V
VDDD
SID63
RPULLUP
Pull-up resistor
3.5
5.6
8.5
kΩ
SID64
RPULLDOWN
Pull-down resistor
3.5
5.6
8.5
kΩ
SID65
IIL
Input leakage current (absolute value)
–
–
2
nA
SID65A
IIL_CTBM
Input leakage current (absolute value)
for CTBM pins
–
–
4
nA
25 °C, VDDD =
3.0 V
SID66
CIN
Input capacitance
–
–
7
pF
SID67
VHYSTTL
Input hysteresis LVTTL
25
40
–
mV
VDDD 2.7 V.
Guaranteed by
characterization
SID68
VHYSCMOS
Input hysteresis CMOS
0.05 ×
VDDD
–
–
mV
Guaranteed by
characterization
SID69
IDIODE
Current through protection diode to
VDD/Vss
–
–
100
µA
Guaranteed by
characterization
SID69A
ITOT_GPIO
Maximum Total Source or Sink Chip
Current
–
–
200
mA
Guaranteed by
characterization
Note
2. VIH must not exceed VDDD + 0.2 V.
Document Number: 001-87197 Rev. *J
Page 21 of 45
PSoC® 4: PSoC 4200
Family Datasheet
Table 5. GPIO AC Specifications
(Guaranteed by Characterization)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
SID70
TRISEF
Rise time in fast strong mode
2
–
12
ns
3.3-V VDDD,
Cload = 25 pF
SID71
TFALLF
Fall time in fast strong mode
2
–
12
ns
3.3-V VDDD,
Cload = 25 pF
SID72
TRISES
Rise time in slow strong mode
10
–
60
ns
3.3-V VDDD,
Cload = 25 pF
SID73
TFALLS
Fall time in slow strong mode
10
–
60
ns
3.3-V VDDD,
Cload = 25 pF
SID74
FGPIOUT1
GPIO Fout;3.3 V VDDD 5.5 V. Fast
strong mode.
–
–
33
MHz
90/10%, 25-pF
load, 60/40 duty
cycle
SID75
FGPIOUT2
GPIO Fout;1.7 VVDDD3.3 V. Fast
strong mode.
–
–
16.7
MHz
90/10%, 25-pF
load, 60/40 duty
cycle
SID76
FGPIOUT3
GPIO Fout;3.3 V VDDD 5.5 V. Slow
strong mode.
–
–
7
MHz
90/10%, 25-pF
load, 60/40 duty
cycle
SID245
FGPIOUT4
GPIO Fout;1.7 V VDDD 3.3 V. Slow
strong mode.
–
–
3.5
MHz
90/10%, 25-pF
load, 60/40 duty
cycle
SID246
FGPIOIN
GPIO input operating frequency;
1.71 V VDDD 5.5 V
–
–
48
MHz
90/10% VIO
Min
Typ
Max
Units
XRES
Table 6. XRES DC Specifications
Spec ID#
Parameter
Description
Details/
Conditions
SID77
VIH
Input voltage high threshold
0.7 ×
VDDD
–
–
V
CMOS input
SID78
VIL
Input voltage low threshold
–
–
0.3 ×
VDDD
V
CMOS input
SID79
RPULLUP
Pull-up resistor
3.5
5.6
8.5
kΩ
SID80
CIN
Input capacitance
–
3
–
pF
SID81
VHYSXRES
Input voltage hysteresis
–
100
–
mV
Guaranteed by
characterization
SID82
IDIODE
Current through protection diode to
VDDD/VSS
–
–
100
µA
Guaranteed by
characterization
Min
1
Typ
–
Max
–
Units
µs
Table 7. XRES AC Specifications
Spec ID#
SID83
Parameter
TRESETWIDTH
Description
Reset pulse width
Document Number: 001-87197 Rev. *J
Details/
Conditions
Guaranteed by
characterization
Page 22 of 45
PSoC® 4: PSoC 4200
Family Datasheet
Analog Peripherals
Opamp
Table 8. Opamp Specifications
(Guaranteed by Characterization)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
IDD
Opamp block current. No load.
–
–
–
–
SID269
IDD_HI
Power = high
–
1100
1850
µA
SID270
IDD_MED
Power = medium
–
550
950
µA
SID271
IDD_LOW
Power = low
–
150
350
µA
GBW
Load = 20 pF, 0.1 mA. VDDA = 2.7 V
–
–
–
–
SID272
GBW_HI
Power = high
6
–
–
MHz
SID273
GBW_MED
Power = medium
4
–
–
MHz
SID274
GBW_LO
Power = low
–
1
–
MHz
IOUT_MAX
VDDA 2.7 V, 500 mV from rail
–
–
–
–
SID275
IOUT_MAX_HI
Power = high
10
–
–
mA
SID276
IOUT_MAX_MID
Power = medium
10
–
–
mA
SID277
IOUT_MAX_LO
Power = low
–
5
–
mA
IOUT
VDDA = 1.71 V, 500 mV from rail
–
–
–
–
SID278
IOUT_MAX_HI
Power = high
4
–
–
mA
SID279
IOUT_MAX_MID
Power = medium
4
–
–
mA
SID280
IOUT_MAX_LO
Power = low
–
2
–
mA
Details/
Conditions
SID281
VIN
Charge pump on, VDDA 2.7 V
–0.05
–
VDDA – 0.2
V
SID282
VCM
Charge pump on, VDDA 2.7 V
–0.05
–
VDDA – 0.2
V
VOUT
VDDA 2.7 V
–
–
–
SID283
VOUT_1
Power = high, Iload=10 mA
0.5
–
VDDA – 0.5
V
SID284
VOUT_2
Power = high, Iload=1 mA
0.2
–
VDDA – 0.2
V
SID285
VOUT_3
Power = medium, Iload=1 mA
0.2
–
VDDA – 0.2
V
SID286
VOUT_4
Power = low, Iload=0.1mA
0.2
–
VDDA – 0.2
V
SID288
VOS_TR
Offset voltage, trimmed
1
±0.5
1
mV
High mode
SID288A
VOS_TR
Offset voltage, trimmed
–
±1
–
mV
Medium mode
SID288B
VOS_TR
Offset voltage, trimmed
–
±2
–
mV
Low mode
SID290
VOS_DR_TR
Offset voltage drift, trimmed
–10
±3
10
µV/°C
High mode.
TA 85 °C
SID290Q
VOS_DR_TR
Offset voltage drift, trimmed
15
±3
15
µV/°C
High mode.
TA 105 °C
SID290A
VOS_DR_TR
Offset voltage drift, trimmed
–
±10
–
µV/°C
Medium mode
SID290B
VOS_DR_TR
Offset voltage drift, trimmed
–
±10
–
µV/°C
Low mode
SID291
CMRR
DC
70
80
–
dB
VDDD = 3.6 V
SID292
PSRR
At 1 kHz, 100-mV ripple
70
85
–
dB
VDDD = 3.6 V
–
–
–
–
SID293
VN1
Input referred, 1 Hz - 1GHz, power =
high
–
94
–
µVrms
SID294
VN2
Input referred, 1 kHz, power = high
–
72
–
nV/rtHz
SID295
VN3
Input referred, 10kHz, power = high
–
28
–
nV/rtHz
Noise
Document Number: 001-87197 Rev. *J
Page 23 of 45
PSoC® 4: PSoC 4200
Family Datasheet
Table 8. Opamp Specifications
(Guaranteed by Characterization) (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
SID296
VN4
Input referred, 100kHz, power = high
–
15
–
nV/rtHz
SID297
Cload
Stable up to maximum load. Performance specs at 50 pF.
–
–
125
pF
SID298
Slew_rate
Cload = 50 pF, Power = High, VDDA
2.7 V
6
–
–
V/µs
SID299
T_op_wake
From disable to enable, no external RC
dominating
–
300
–
µs
SID299A
OL_GAIN
Open Loop Gain
–
90
–
dB
Comp_mode
Comparator mode; 50 mV drive,
Trise = Tfall (approx.)
–
–
–
SID300
TPD1
Response time; power = high
–
150
–
SID301
TPD2
Response time; power = medium
–
400
–
ns
SID302
TPD3
Response time; power = low
–
2000
–
ns
SID303
Vhyst_op
Hysteresis
–
10
–
mV
Min
Typ
Max
Units
Details/
Conditions
Guaranteed by
design
ns
Comparatorr
Table 9. Comparator DC Specifications
Spec ID#
Parameter
Description
Details/
Conditions
SID85
VOFFSET2
Input offset voltage, Common Mode
voltage range from 0 to VDD-1
–
–
±4
mV
SID85A
VOFFSET3
Input offset voltage. Ultra low-power
mode (VDDD ≥ 2.2 V for Temp < 0 °C,
VDDD ≥ 1.8 V for Temp > 0 °C)
–
±12
–
mV
SID86
VHYST
Hysteresis when enabled, Common
Mode voltage range from 0 to VDD -1.
–
10
35
mV
Guaranteed by
characterization
SID87
VICM1
Input common mode voltage in normal
mode
0
–
VDDD – 0.1
V
Modes 1 and 2.
SID247
VICM2
Input common mode voltage in low
power mode (VDDD ≥ 2.2 V for Temp <
0 °C, VDDD ≥ 1.8 V for Temp > 0 °C)
0
–
VDDD
V
SID247A
VICM3
Input common mode voltage in ultra low
power mode
0
–
VDDD –
1.15
V
SID88
CMRR
Common mode rejection ratio
50
–
–
dB
VDDD 2.7 V.
Guaranteed by
characterization
SID88A
CMRR
Common mode rejection ratio
42
–
–
dB
VDDD 2.7 V.
Guaranteed by
characterization
SID89
ICMP1
Block current, normal mode
–
–
400
µA
Guaranteed by
characterization
SID248
ICMP2
Block current, low power mode
–
–
100
µA
Guaranteed by
characterization
SID259
ICMP3
Block current, ultra low power mode
(VDDD ≥ 2.2 V for Temp < 0 °C, VDDD ≥
1.8 V for Temp > 0 °C)
–
6
28
µA
Guaranteed by
characterization
Document Number: 001-87197 Rev. *J
Page 24 of 45
PSoC® 4: PSoC 4200
Family Datasheet
Table 9. Comparator DC Specifications (continued)
Spec ID#
SID90
Parameter
ZCMP
Description
DC input impedance of comparator
Min
Typ
Max
Units
35
–
–
MΩ
Min
Typ
Max
Units
–
–
110
ns
Details/
Conditions
Guaranteed by
characterization
Table 10. Comparator AC Specifications
(Guaranteed by Characterization)
Spec ID#
Parameter
Description
Details/Conditions
SID91
TRESP1
Response time, normal mode
SID258
TRESP2
Response time, low power mode
–
–
200
ns
50-mV overdrive
SID92
TRESP3
Response time, ultra low power mode
(VDDD ≥ 2.2 V for Temp < 0 °C, VDDD ≥
1.8 V for Temp > 0 °C)
–
–
15
µs
200-mV overdrive
Min
Typ
Max
Units
Details/Conditions
–5
±1
+5
°C
–40 to +85 °C
Min
Typ
Max
Units
bits
50-mV overdrive
Temperature Sensor
Table 11. Temperature Sensor Specifications
Spec ID#
SID93
Parameter
TSENSACC
Description
Temperature sensor accuracy
SAR ADC
Table 12. SAR ADC DC Specifications
Spec ID#
Parameter
Description
Details/Conditions
SID94
A_RES
Resolution
–
–
12
SID95
A_CHNIS_S
Number of channels - single ended
–
–
8
8 full speed
SID96
A-CHNKS_D
Number of channels - differential
–
–
4
Diff inputs use
neighboring I/O
SID97
A-MONO
Monotonicity
–
–
–
Yes. Based on
characterization
SID98
A_GAINERR
Gain error
–
–
±0.1
%
SID99
A_OFFSET
Input offset voltage
–
–
2
mV
SID100
A_ISAR
Current consumption
–
–
1
mA
SID101
A_VINS
Input voltage range - single ended
VSS
–
VDDA
V
Based on device
characterization
SID102
A_VIND
Input voltage range - differential
VSS
–
VDDA
V
Based on device
characterization
SID103
A_INRES
Input resistance
–
–
2.2
KΩ
Based on device
characterization
SID104
A_INCAP
Input capacitance
–
–
10
pF
Based on device
characterization
SID106
A_PSRR
Power supply rejection ratio
70
–
–
dB
SID107
A_CMRR
Common mode rejection ratio
66
–
–
dB
Document Number: 001-87197 Rev. *J
With external
reference.
Guaranteed by
characterization
Measured with 1-V
VREF. Guaranteed by
characterization
Measured at 1 V
Page 25 of 45
PSoC® 4: PSoC 4200
Family Datasheet
Table 12. SAR ADC DC Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID111
A_INL
Integral non linearity
–1.7
–
+2
LSB
VDD = 1.71 to 5.5,
1 Msps, Vref = 1 to
5.5.
SID111A
A_INL
Integral non linearity
–1.5
–
+1.7
LSB
VDDD = 1.71 to 3.6,
1 Msps, Vref = 1.71 to
VDDD.
SID111B
A_INL
Integral non linearity
–1.5
–
+1.7
LSB
VDDD = 1.71 to 5.5,
500 Ksps, Vref = 1 to
5.5.
SID112
A_DNL
Differential non linearity
–1
–
+2.2
LSB
VDDD = 1.71 to 5.5, 1
Msps, Vref = 1 to 5.5.
SID112A
A_DNL
Differential non linearity
–1
–
+2
LSB
VDDD = 1.71 to 3.6, 1
Msps, Vref = 1.71 to
VDDD.
SID112B
A_DNL
Differential non linearity
–1
–
+2.2
LSB
VDDD = 1.71 to 5.5,
500 Ksps, Vref = 1 to
5.5.
Min
–
Typ
–
Max
1
Units
Msps
Details/Conditions
–
–
500
Ksps
–
–
100
Ksps
65
–
–
dB
FIN = 10 kHz
–
–
–65
dB
FIN = 10 kHz.
Table 13. SAR ADC AC Specifications
(Guaranteed by Characterization)
Spec ID#
SID108
Parameter
A_SAMP_1
SID108A
A_SAMP_2
SID108B
A_SAMP_3
SID109
A_SNDR
SID113
A_THD
Description
Sample rate with external reference
bypass cap
Sample rate with no bypass cap.
Reference = VDD
Sample rate with no bypass cap.
Internal reference
Signal-to-noise and distortion ratio
(SINAD)
Total harmonic distortion
Document Number: 001-87197 Rev. *J
Page 26 of 45
PSoC® 4: PSoC 4200
Family Datasheet
CSD
Table 14. CSD Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
SID.CSD#16 IDAC1IDD
IDAC1 (8 bits) block current
–
–
1125
μA
SID.CSD#17 IDAC2IDD
IDAC2 (7 bits) block current
–
–
1125
μA
SID308
VCSD
Voltage range of operation
1.71
–
5.5
V
SID308A
Vcompidac
Voltage compliance range of IDAC for S0
0.8
–
VDD-0.8
V
SID309
IDAC1
DNL for 8-bit resolution
–1
–
1
LSB
SID310
IDAC1
INL for 8-bit resolution
–3
–
3
LSB
SID311
IDAC2
DNL for 7-bit resolution
–1
–
1
LSB
SID312
IDAC2
INL for 7-bit resolution
–3
–
3
LSB
SID313
SNR
Ratio of counts of finger to noise, 0.1-pF
sensitivity
5
–
–
Ratio Capacitance
range of 9 to 35 pF,
0.1-pF sensitivity
SID314
IDAC1_CRT1
Output current of Idac1 (8 bits) in High
range
–
612
–
uA
SID314A
IDAC1_CRT2
Output current of Idac1 (8 bits) in Low
range
–
306
–
uA
SID315
IDAC2_CRT1
Output current of Idac2 (7 bits) in High
range
–
304.8
–
uA
SID315A
IDAC2_CRT2
Output current of Idac2 (7 bits) in Low
range
–
152.4
–
uA
SID320
IDACOFFSET
All zeroes input
–
–
±1
LSB
SID321
IDACGAIN
Full-scale error less offset
–
–
±10
%
SID322
IDACMISMATCH Mismatch between IDACs
–
–
7
LSB
SID323
IDACSET8
Settling time to 0.5 LSB for 8-bit IDAC
–
–
10
μs
Full-scale
transition. No
external load.
SID324
IDACSET7
Settling time to 0.5 LSB for 7-bit IDAC
–
–
10
μs
Full-scale
transition. No
external load.
SID325
CMOD
External modulator capacitor
–
2.2
–
nF
5-V rating, X7R or
NP0 cap.
Document Number: 001-87197 Rev. *J
Page 27 of 45
PSoC® 4: PSoC 4200
Family Datasheet
Digital Peripherals
The following specifications apply to the Timer/Counter/PWM peripherals in the Timer mode.
Timer/Counter/PWM
Table 15. TCPWM Specifications
(Guaranteed by Characterization)
Spec ID
Parameter
Description
Min
Typ
Max
Units
SID.TCPWM.1
ITCPWM1
Block current consumption at 3 MHz
–
–
45
µA
SID.TCPWM.2
ITCPWM2
Block current consumption at 12 MHz
–
–
155
µA
SID.TCPWM.2A ITCPWM3
Block current consumption at 48 MHz
–
–
650
µA
–
–
Fc
MHz
SID.TCPWM.3
TCPWMFREQ Operating frequency
SID.TCPWM.4
TPWMENEXT
Input Trigger Pulse Width for all
Trigger Events
2/Fc
–
–
ns
SID.TCPWM.5
TPWMEXT
Output Trigger Pulse widths
2/Fc
–
–
ns
SID.TCPWM.5A TCRES
Resolution of Counter
1/Fc
–
–
ns
SID.TCPWM.5B PWMRES
PWM Resolution
1/Fc
–
–
ns
SID.TCPWM.5C QRES
Quadrature inputs resolution
1/Fc
–
–
ns
Details/Conditions
All modes
(Timer/Counter/PWM)
All modes
(Timer/Counter/PWM)
All modes
(Timer/Counter/PWM)
Fc max = Fcpu.
Maximum = 24 MHz
Trigger Events can be
Stop, Start, Reload,
Count, Capture, or Kill
depending on which
mode of operation is
selected.
Minimum possible
width of Overflow,
Underflow, and CC
(Counter equals
Compare value)
trigger outputs
Minimum time
between successive
counts
Minimum pulse width
of PWM Output
Minimum pulse width
between Quadrature
phase inputs.
I2C
Table 16. Fixed I2C DC Specifications
(Guaranteed by Characterization)
Min
Typ
Max
Units
SID149
Spec ID
II2C1
Block current consumption at 100 kHz
–
–
50
µA
SID150
II2C2
Block current consumption at 400 kHz
–
–
135
µA
SID151
II2C3
Block current consumption at 1 Mbps
–
–
310
µA
–
–
1.4
µA
Min
–
Typ
–
Max
1
Units
Mbps
SID152
Parameter
II2C4
Description
2
I C enabled in Deep Sleep mode
Details/Conditions
Table 17. Fixed I2C AC Specifications
(Guaranteed by Characterization)
Spec ID
SID153
Parameter
FI2C1
Description
Bit rate
Document Number: 001-87197 Rev. *J
Details/Conditions
Page 28 of 45
PSoC® 4: PSoC 4200
Family Datasheet
LCD Direct Drive
Table 18. LCD Direct Drive DC Specifications
(Guaranteed by Characterization)
Spec ID
SID154
Parameter
ILCDLOW
SID155
CLCDCAP
SID156
LCDOFFSET
SID157
ILCDOP1
SID158
ILCDOP2
Description
Operating current in low power mode
Min
–
Typ
5
Max
–
Units Details/Conditions
µA 16 × 4 small segment
disp. at 50 Hz
pF Guaranteed by Design
LCD capacitance per segment/common
driver
Long-term segment offset
–
500
5000
–
20
–
mV
PWM Mode current. 5-V bias.
24-MHz IMO. 25 °C
PWM Mode current. 3.3-V bias.
24-MHz IMO. 25 °C
–
0.6
–
mA
–
0.5
–
mA
Min
10
Typ
50
Max
150
Units
Hz
32 × 4 segments.
50 Hz
32 × 4 segments.
50 Hz
Table 19. LCD Direct Drive AC Specifications
(Guaranteed by Characterization)
Spec ID
SID159
Parameter
FLCD
Description
LCD frame rate
Details/Conditions
Table 20. Fixed UART DC Specifications
(Guaranteed by Characterization)
Min
Typ
Max
Units
SID160
Spec ID
IUART1
Parameter
Block current consumption at
100 Kbits/sec
Description
–
–
55
µA
SID161
IUART2
Block current consumption at
1000 Kbits/sec
–
–
312
µA
Details/Conditions
Table 21. Fixed UART AC Specifications
(Guaranteed by Characterization)
Spec ID
SID162
Parameter
FUART
Description
Bit rate
Min
Typ
Max
Units
–
–
1
Mbps
Min
Typ
Max
Units
SPI Specifications
Table 22. Fixed SPI DC Specifications
(Guaranteed by Characterization)
Spec ID
Parameter
Description
SID163
ISPI1
Block current consumption at 1 Mbits/sec
–
–
360
µA
SID164
ISPI2
Block current consumption at 4 Mbits/sec
–
–
560
µA
SID165
ISPI3
Block current consumption at 8 Mbits/sec
–
–
600
µA
Min
Typ
Max
Units
–
–
8
MHz
Table 23. Fixed SPI AC Specifications
(Guaranteed by Characterization)
Spec ID
SID166
Parameter
FSPI
Document Number: 001-87197 Rev. *J
Description
SPI operating frequency (master; 6X
oversampling)
Page 29 of 45
PSoC® 4: PSoC 4200
Family Datasheet
Table 24. Fixed SPI Master Mode AC Specifications
(Guaranteed by Characterization)
Min
Typ
Max
Units
SID167
Spec ID
TDMO
Parameter
MOSI valid after Sclock driving edge
Description
–
–
15
ns
SID168
TDSI
MISO valid before Sclock capturing edge.
Full clock, late MISO Sampling used
20
–
–
ns
SID169
THMO
Previous MOSI data hold time with respect
to capturing edge at Slave
0
–
–
ns
Table 25. Fixed SPI Slave Mode AC Specifications
(Guaranteed by Characterization)
Min
Typ
Max
Units
SID170
Spec ID
TDMI
Parameter
MOSI valid before Sclock capturing edge
Description
40
–
–
ns
SID171
TDSO
MISO valid after Sclock driving edge
–
–
42 + 3 ×
Tscbclk
ns
SID171A
TDSO_ext
MISO valid after Sclock driving edge in Ext.
Clock mode
–
–
48
ns
SID172
THSO
Previous MISO data hold time
SID172A
TSSELSCK
SSEL Valid to first SCK Valid edge
0
–
–
ns
100
–
–
ns
Memory
Table 26. Flash DC Specifications
Spec ID
SID173
Parameter
Description
VPE
Erase and program voltage
Min
Typ
Max
Units
1.71
–
5.5
V
Details/Conditions
Table 27. Flash AC Specifications
Spec ID
Parameter
SID174
TROWWRITE[3]
SID175
TROWERASE[3]
SID176
TROWPROGRAM
SID178
TBULKERASE[3]
[3]
[3]
Description
Min
Typ
Max
Units
Details/Conditions
Row (block) write time (erase and
program)
–
–
20
ms
Row (block) = 128 bytes
Row erase time
–
–
13
ms
Row program time after erase
–
–
7
ms
Bulk erase time (32 KB)
–
–
35
ms
Total device program time
–
–
7
100 K
–
–
cycles
Guaranteed by characterization
SID180
TDEVPROG
SID181
FEND
Flash endurance
SID182
FRET
Flash retention. TA 55 °C, 100 K
P/E cycles
20
–
–
years
Guaranteed by characterization
Flash retention. TA 85 °C, 10 K
P/E cycles
10
–
–
years
Guaranteed by characterization
Flash retention. TA 105 °C, 10 K
P/E cycles, three years at TA
85 °C
10
–
20
years
Guaranteed by characterization
SID182A
SID182B
FRETQ
seconds Guaranteed by characterization
Note
3. It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or Flash operations will be interrupted and cannot be relied
on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.
Make certain that these are not inadvertently activated.
Document Number: 001-87197 Rev. *J
Page 30 of 45
PSoC® 4: PSoC 4200
Family Datasheet
System Resources
Power-on-Reset (POR) with Brown Out
Table 28. Imprecise Power On Reset (IPOR)
Spec ID
SID185
Parameter
VRISEIPOR
Description
Rising trip voltage
Min
0.80
Typ
–
Max
1.45
Units
V
SID186
VFALLIPOR
Falling trip voltage
0.75
–
1.4
V
SID187
VIPORHYST
Hysteresis
15
–
200
mV
Details/Conditions
Guaranteed by characterization
Guaranteed by characterization
Guaranteed by characterization
Table 29. Precise Power On Reset (POR)
Spec ID
SID190
Parameter
VFALLPPOR
Description
BOD trip voltage in active and
sleep modes
Min
1.64
Typ
–
Max
–
Units
V
Details/Conditions
Full functionality
between 1.71 V and
BOD trip voltage is
guaranteed by characterization
Guaranteed by characterization
SID192
VFALLDPSLP
BOD trip voltage in Deep Sleep
1.4
–
–
V
BID55
Svdd
Maximum power supply ramp
rate
–
–
67
kV/sec
Voltage Monitors
Table 30. Voltage Monitors DC Specifications
Spec ID
SID195
Parameter
VLVI1
Description
LVI_A/D_SEL[3:0] = 0000b
Min
1.71
Typ
1.75
Max
1.79
Units
V
SID196
VLVI2
LVI_A/D_SEL[3:0] = 0001b
1.76
1.80
1.85
V
SID197
VLVI3
LVI_A/D_SEL[3:0] = 0010b
1.85
1.90
1.95
V
SID198
VLVI4
LVI_A/D_SEL[3:0] = 0011b
1.95
2.00
2.05
V
SID199
VLVI5
LVI_A/D_SEL[3:0] = 0100b
2.05
2.10
2.15
V
SID200
VLVI6
LVI_A/D_SEL[3:0] = 0101b
2.15
2.20
2.26
V
SID201
VLVI7
LVI_A/D_SEL[3:0] = 0110b
2.24
2.30
2.36
V
SID202
VLVI8
LVI_A/D_SEL[3:0] = 0111b
2.34
2.40
2.46
V
SID203
VLVI9
LVI_A/D_SEL[3:0] = 1000b
2.44
2.50
2.56
V
SID204
VLVI10
LVI_A/D_SEL[3:0] = 1001b
2.54
2.60
2.67
V
SID205
VLVI11
LVI_A/D_SEL[3:0] = 1010b
2.63
2.70
2.77
V
SID206
VLVI12
LVI_A/D_SEL[3:0] = 1011b
2.73
2.80
2.87
V
SID207
VLVI13
LVI_A/D_SEL[3:0] = 1100b
2.83
2.90
2.97
V
SID208
VLVI14
LVI_A/D_SEL[3:0] = 1101b
2.93
3.00
3.08
V
SID209
VLVI15
LVI_A/D_SEL[3:0] = 1110b
3.12
3.20
3.28
V
SID210
VLVI16
LVI_A/D_SEL[3:0] = 1111b
4.39
4.50
4.61
V
SID211
LVI_IDD
Block current
–
–
100
µA
Min
–
Typ
–
Max
1
Units
µs
Details/Conditions
Guaranteed by
characterization
Table 31. Voltage Monitors AC Specifications
Spec ID
SID212
Parameter
TMONTRIP
Description
Voltage monitor trip time
Document Number: 001-87197 Rev. *J
Details/Conditions
Guaranteed by
characterization
Page 31 of 45
PSoC® 4: PSoC 4200
Family Datasheet
SWD Interface
Table 32. SWD Interface Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID213
F_SWDCLK1
3.3 V VDD 5.5 V
–
–
14
MHz
SWDCLK ≤ 1/3 CPU
clock frequency
SID214
F_SWDCLK2
1.71 V VDD 3.3 V
–
–
7
MHz
SWDCLK ≤ 1/3 CPU
clock frequency
SID215
T_SWDI_SETUP T = 1/f SWDCLK
0.25*T
–
–
ns
Guaranteed by
characterization
SID216
T_SWDI_HOLD
0.25*T
–
–
ns
Guaranteed by
characterization
SID217
T_SWDO_VALID T = 1/f SWDCLK
–
–
0.5*T
ns
Guaranteed by
characterization
SID217A
T_SWDO_HOLD T = 1/f SWDCLK
1
–
–
ns
Guaranteed by
characterization
Min
Typ
Max
Units
T = 1/f SWDCLK
Internal Main Oscillator
Table 33. IMO DC Specifications
(Guaranteed by Design)
Spec ID
Parameter
Description
SID218
IIMO1
IMO operating current at 48 MHz
–
–
1000
µA
SID219
IIMO2
IMO operating current at 24 MHz
–
–
325
µA
SID220
IIMO3
IMO operating current at 12 MHz
–
–
225
µA
SID221
IIMO4
IMO operating current at 6 MHz
–
–
180
µA
SID222
IIMO5
IMO operating current at 3 MHz
–
–
150
µA
Details/Conditions
Table 34. IMO AC Specifications
Min
Typ
Max
Units
Details/Conditions
SID223
Spec ID
FIMOTOL1
Parameter
Frequency variation from 3 to
48 MHz
Description
–
–
±2
%
±3% if TA > 85 °C and
IMO frequency <
24 MHz
SID226
TSTARTIMO
IMO startup time
–
–
12
µs
SID227
TJITRMSIMO1
RMS Jitter at 3 MHz
–
156
–
ps
SID228
TJITRMSIMO2
RMS Jitter at 24 MHz
–
145
–
ps
SID229
TJITRMSIMO3
RMS Jitter at 48 MHz
–
139
–
ps
Internal Low-Speed Oscillator
Table 35. ILO DC Specifications
(Guaranteed by Design)
Min
Typ
Max
Units
SID231
Spec ID
IILO1
Parameter
ILO operating current at 32 kHz
Description
–
0.3
1.05
µA
Guaranteed by
Characterization
SID233
IILOLEAK
ILO leakage current
–
2
15
nA
Guaranteed by
Design
Document Number: 001-87197 Rev. *J
Details/Conditions
Page 32 of 45
PSoC® 4: PSoC 4200
Family Datasheet
Table 36. ILO AC Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID234
TSTARTILO1
ILO startup time
–
–
2
ms
Guaranteed by characterization
SID236
TILODUTY
ILO duty cycle
40
50
60
%
Guaranteed by characterization
SID237
FILOTRIM1
32 kHz trimmed frequency
15
32
50
kHz
Max ILO frequency is
70 kHz if TA > 85 °C
Table 37. External Clock Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID305
ExtClkFreq
External Clock input Frequency
0
–
48
MHz
Guaranteed by
characterization
SID306
ExtClkDuty
Duty cycle; Measured at VDD/2
45
–
55
%
Guaranteed by
characterization
Table 38. UDB AC Specifications
(Guaranteed by Characterization)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
Datapath performance
SID249
FMAX-TIMER
Max frequency of 16-bit timer in a
UDB pair
–
–
48
MHz
SID250
FMAX-ADDER
Max frequency of 16-bit adder in a
UDB pair
–
–
48
MHz
SID251
FMAX_CRC
Max frequency of 16-bit CRC/PRS in
a UDB pair
–
–
48
MHz
Max frequency of 2-pass PLD
function in a UDB pair
–
–
48
MHz
PLD Performance in UDB
SID252
FMAX_PLD
Clock to Output Performance
SID253
TCLK_OUT_UDB1
Prop. delay for clock in to data out at
25 °C, Typ.
–
15
–
ns
SID254
TCLK_OUT_UDB2
Prop. delay for clock in to data out,
Worst case.
–
25
–
ns
Document Number: 001-87197 Rev. *J
Page 33 of 45
PSoC® 4: PSoC 4200
Family Datasheet
Table 39. Block Specs
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID256*
TWS48*
Number of wait states at 48 MHz
1
–
–
CPU execution from
Flash. Guaranteed
by characterization
SID257
TWS24*
Number of wait states at 24 MHz
0
–
–
CPU execution from
Flash. Guaranteed
by characterization
SID260
VREFSAR
Trimmed internal reference to SAR
–1
–
+1
SID262
TCLKSWITCH
Clock switching from clk1 to clk2 in
clk1 periods
3
–
4
%
Percentage of Vbg
(1.024 V).
Guaranteed by
characterization
Periods . Guaranteed by
design
* Tws48 and Tws24 are guaranteed by Design
Table 40. UDB Port Adaptor Specifications
(Based on LPC Component Specs, Guaranteed by Characterization -10-pF load, 3-V VDDIO and VDDD)
Spec ID
Parameter
Description
Min
Typ
Max
Units Details/Conditions
SID263
TLCLKDO
LCLK to output delay
–
–
18
ns
SID264
TDINLCLK
Input setup time to LCLCK rising
edge
–
–
7
ns
SID265
TDINLCLKHLD
Input hold time from LCLK rising edge
5
–
–
ns
SID266
TLCLKHIZ
LCLK to output tristated
–
–
28
ns
SID267
TFLCLK
LCLK frequency
–
–
33
MHz
SID268
TLCLKDUTY
LCLK duty cycle (percentage high)
40
–
60
%
Document Number: 001-87197 Rev. *J
Page 34 of 45
PSoC® 4: PSoC 4200
Family Datasheet
Ordering Information
The PSoC 4200 part numbers and features are listed in the following table.
Table 41. PSoC 4200 Family Ordering Information
4200
Op-amp (CTBm)
CapSense
Direct LCD Drive
12-bit SAR ADC
LP Comparators
TCPWM Blocks
SCB Blocks
GPIO
28-SSOP
2
1
-
-
1 Msps
2
4
2
24
√
CY8C4244PVI-442
48
16
4
2
1
√
√
1 Msps
2
4
2
24
√
CY8C4244PVQ-432
48
16
4
2
1
-
-
1 Msps
2
4
2
24
√
CY8C4244PVQ-442
48
16
4
2
1
√
√
1 Msps
2
4
2
24
√
CY8C4244FNI-443
48
16
4
2
2
√
√
1 Msps
2
4
2
31
CY8C4244LQI-443
48
16
4
2
2
√
√
1 Msps
2
4
2
34
CY8C4244AXI-443
48
16
4
2
2
√
√
1 Msps
2
4
2
36
CY8C4244LQQ-443
48
16
4
2
2
√
√
1 Msps
2
4
2
34
CY8C4244AXQ-443
48
16
4
2
2
√
√
1 Msps
2
4
2
36
CY8C4244AZI-443
48
16
4
2
2
√
√
1 Msps
2
4
2
36
√
√
√
√
√
√
CY8C4245AXI-473
48
32
4
4
2
-
-
1 Msps
2
4
2
36
√
CY8C4245AXQ-473
48
32
4
4
2
-
-
1 Msps
2
4
2
36
√
CY8C4245AZI-473
48
32
4
4
2
-
-
1 Msps
2
4
2
36
CY8C4245PVI-482
48
32
4
4
1
√
√
1 Msps
2
4
2
24
√
CY8C4245PVQ-482
48
32
4
4
1
√
√
1 Msps
2
4
2
24
√
CY8C4245FNI-483(T)
48
32
4
4
2
√
√
1 Msps
2
4
2
31
CY8C4245LQI-483
48
32
4
4
2
√
√
1 Msps
2
4
2
34
CY8C4245AXI-483
48
32
4
4
2
√
√
1 Msps
2
4
2
36
CY8C4245LQQ-483
48
32
4
4
2
√
√
1 Msps
2
4
2
34
CY8C4245AXQ-483
48
32
4
4
2
√
√
1 Msps
2
4
2
36
CY8C4245AZI-483
48
32
4
4
2
√
√
1 Msps
2
4
2
36
Document Number: 001-87197 Rev. *J
48-TQFP
UDB
4
44-TQFP
SRAM (KB)
16
40-QFN
Flash (KB)
48
35-WLCSP
Max CPU Speed (MHz)
Package
CY8C4244PVI-432
MPN
Family
Features
√
√
√
√
√
√
√
Page 35 of 45
PSoC® 4: PSoC 4200
Family Datasheet
Part Numbering Conventions
PSoC 4 devices follow the part numbering convention described in the following table. All fields are single-character alphanumeric (0,
1, 2, …, 9, A,B, …, Z) unless stated otherwise.
The part numbers are of the form CY8C4ABCDEF-XYZ where the fields are defined as follows.
Example
CY8C
4 A B C D E F - X Y Z
Cypress Prefix
4 : PSoC 4
Architecture
2 : 4200 Family
Family within Architecture
4 : 48 MHz
Speed Grade
5 : 32 KB
Flash Capacity
AX: TQFP
Package Code
I : Industrial
Temperature Range
Attributes Set
The Field Values are listed in the following table.
Field
CY8C
Description
Values
Meaning
Cypress Prefix
4
Architecture
4
PSoC 4
A
Family within architecture
1
4100 Family
2
4200 Family
B
CPU Speed
2
24 MHz
4
48 MHz
C
Flash Capacity
4
16 KB
5
32 KB
AX, AZ
TQFP
LQ
QFN
PV
SSOP
FN
WLCSP
I
Industrial
Q
Extended Industrial
DE
F
XYZ
Package Code
Temperature Range
Attributes Code
000-999
Document Number: 001-87197 Rev. *J
Code of feature set in specific family
Page 36 of 45
PSoC® 4: PSoC 4200
Family Datasheet
Packaging
Table 42. Package Characteristics
Parameter
Description
Conditions
Min
Typ
Max
Units
TA
Operating ambient temperature
–40
25.00
105
°C
TJ
Operating junction temperature
–40
–
125
°C
TJA
Package JA (28-pin SSOP)
–
66.58
–
°C/Watt
TJA
Package JA (35-ball WLCSP)
–
28.00
–
°C/Watt
TJA
Package JA (40-pin QFN)
–
15.34
–
°C/Watt
TJA
Package JA (44-pin TQFP)
–
57.16
–
°C/Watt
TJA
Package JA (48-pin TQFP)
–
67.30
–
°C/Watt
TJC
Package JC (28-pin SSOP)
–
26.28
–
°C/Watt
TJC
Package JC (35-ball WLCSP)
–
00.40
–
°C/Watt
TJC
Package JC (40-pin QFN)
–
2.50
–
°C/Watt
TJC
Package JC (44-pin TQFP)
–
17.47
–
°C/Watt
TJC
Package JC (48-pin TQFP)
–
27.60
–
°C/Watt
Table 43. Solder Reflow Peak Temperature
Package
Maximum Peak
Temperature
Maximum Time at Peak Temperature
28-pin SSOP
260 °C
30 seconds
35-ball WLCSP
260 °C
30 seconds
40-pin QFN
260 °C
30 seconds
44-pin TQFP
260 °C
30 seconds
48-pin TQFP
260 °C
30 seconds
Table 44. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package
MSL
28-pin SSOP
MSL 3
35-ball WLCSP
MSL 3
40-pin QFN
MSL 3
44-pin TQFP
MSL 3
48-pin TQFP
MSL 3
PSoC 4 CAB Libraries with Schematics Symbols and PCB Footprints are on the Cypress web site at
http://www.cypress.com/cad-resources/psoc-4-cad-libraries?source=search&cat=technical_documents.
Document Number: 001-87197 Rev. *J
Page 37 of 45
PSoC® 4: PSoC 4200
Family Datasheet
Figure 17. 28-pin (210-mil) SSOP Package Outline
51-85079 *F
Figure 18. 35-ball WLCSP Package Outline
SIDE VIEW
TOP VIEW
1
2
3
4
5
6
7
A
BOTTOM VIEW
7
6
5
4
3
2
1
A
B
B
C
C
D
D
E
E
NOTES:
1. REFERENCE JEDEC PUBLICATION 95, DESIGN GUIDE 4.18
2. ALL DIMENSIONS ARE IN MILLIMETERS
001-93741 **
Document Number: 001-87197 Rev. *J
Page 38 of 45
PSoC® 4: PSoC 4200
Family Datasheet
Figure 19. 40-pin QFN Package Outline
001-80659 *A
The center pad on the QFN package should be connected to ground (VSS) for best mechanical, thermal, and electrical performance.
If not connected to ground, it should be electrically floating and not connected to any other signal.
Figure 20. 44-pin TQFP Package Outline
51-85064 *G
Document Number: 001-87197 Rev. *J
Page 39 of 45
PSoC® 4: PSoC 4200
Family Datasheet
Figure 21. 48-Pin TQFP Package Outline
51-85135 *C
Document Number: 001-87197 Rev. *J
Page 40 of 45
PSoC® 4: PSoC 4200
Family Datasheet
Acronyms
Table 45. Acronyms Used in this Document
Acronym
Description
Table 45. Acronyms Used in this Document (continued)
Acronym
Description
ETM
embedded trace macrocell
FIR
finite impulse response, see also IIR
FPB
flash patch and breakpoint
FS
full-speed
GPIO
general-purpose input/output, applies to a PSoC
pin
arithmetic logic unit
HVI
high-voltage interrupt, see also LVI, LVD
analog multiplexer bus
IC
integrated circuit
API
application programming interface
IDAC
current DAC, see also DAC, VDAC
APSR
application program status register
IDE
integrated development environment
ARM®
advanced RISC machine, a CPU architecture
I
ATM
automatic thump mode
BW
bandwidth
CAN
Controller Area Network, a communications
protocol
abus
analog local bus
ADC
analog-to-digital converter
AG
analog global
AHB
AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data
transfer bus
ALU
AMUXBUS
2C,
or IIC
Inter-Integrated Circuit, a communications
protocol
IIR
infinite impulse response, see also FIR
ILO
internal low-speed oscillator, see also IMO
IMO
internal main oscillator, see also ILO
integral nonlinearity, see also DNL
CMRR
common-mode rejection ratio
INL
CPU
central processing unit
I/O
input/output, see also GPIO, DIO, SIO, USBIO
CRC
cyclic redundancy check, an error-checking
protocol
IPOR
initial power-on reset
IPSR
interrupt program status register
DAC
digital-to-analog converter, see also IDAC, VDAC
IRQ
interrupt request
DFB
digital filter block
ITM
instrumentation trace macrocell
DIO
digital input/output, GPIO with only digital
capabilities, no analog. See GPIO.
LCD
liquid crystal display
DMIPS
Dhrystone million instructions per second
LIN
Local Interconnect Network, a communications
protocol.
DMA
direct memory access, see also TD
LR
link register
DNL
differential nonlinearity, see also INL
LUT
lookup table
DNU
do not use
LVD
low-voltage detect, see also LVI
DR
port write data registers
LVI
low-voltage interrupt, see also HVI
DSI
digital system interconnect
LVTTL
low-voltage transistor-transistor logic
DWT
data watchpoint and trace
MAC
multiply-accumulate
ECC
error correcting code
MCU
microcontroller unit
ECO
external crystal oscillator
MISO
master-in slave-out
EEPROM
electrically erasable programmable read-only
memory
NC
no connect
EMI
electromagnetic interference
NMI
nonmaskable interrupt
EMIF
external memory interface
NRZ
non-return-to-zero
EOC
end of conversion
NVIC
nested vectored interrupt controller
EOF
end of frame
NVL
nonvolatile latch, see also WOL
EPSR
execution program status register
ESD
electrostatic discharge
Document Number: 001-87197 Rev. *J
opamp
operational amplifier
PAL
programmable array logic, see also PLD
Page 41 of 45
PSoC® 4: PSoC 4200
Family Datasheet
Table 45. Acronyms Used in this Document (continued)
Acronym
Description
Table 45. Acronyms Used in this Document (continued)
Acronym
Description
PC
program counter
SWV
single-wire viewer
PCB
printed circuit board
TD
transaction descriptor, see also DMA
PGA
programmable gain amplifier
THD
total harmonic distortion
PHUB
peripheral hub
TIA
transimpedance amplifier
PHY
physical layer
TRM
technical reference manual
PICU
port interrupt control unit
TTL
transistor-transistor logic
PLA
programmable logic array
TX
transmit
PLD
programmable logic device, see also PAL
UART
PLL
phase-locked loop
Universal Asynchronous Transmitter Receiver, a
communications protocol
PMDD
package material declaration data sheet
UDB
universal digital block
POR
power-on reset
PRES
precise power-on reset
PRS
pseudo random sequence
PS
port read data register
PSoC®
Programmable System-on-Chip™
PSRR
power supply rejection ratio
PWM
pulse-width modulator
RAM
random-access memory
RISC
reduced-instruction-set computing
RMS
root-mean-square
RTC
real-time clock
RTL
register transfer language
RTR
remote transmission request
RX
receive
SAR
successive approximation register
SC/CT
switched capacitor/continuous time
SCL
I2C serial clock
SDA
I2C serial data
S/H
sample and hold
SINAD
signal to noise and distortion ratio
SIO
special input/output, GPIO with advanced
features. See GPIO.
SOC
start of conversion
SOF
start of frame
SPI
Serial Peripheral Interface, a communications
protocol
SR
slew rate
SRAM
static random access memory
SRES
software reset
SWD
serial wire debug, a test protocol
Document Number: 001-87197 Rev. *J
USB
Universal Serial Bus
USBIO
USB input/output, PSoC pins used to connect to
a USB port
VDAC
voltage DAC, see also DAC, IDAC
WDT
watchdog timer
WOL
write once latch, see also NVL
WRES
watchdog timer reset
XRES
external reset I/O pin
XTAL
crystal
Page 42 of 45
PSoC® 4: PSoC 4200
Family Datasheet
Document Conventions
Units of Measure
Table 46. Units of Measure
Symbol
Unit of Measure
°C
degrees Celsius
dB
decibel
fF
femto farad
Hz
hertz
KB
1024 bytes
kbps
kilobits per second
Khr
kilohour
kHz
kilohertz
k
kilo ohm
ksps
kilosamples per second
LSB
least significant bit
Mbps
megabits per second
MHz
megahertz
M
mega-ohm
Msps
megasamples per second
µA
microampere
µF
microfarad
µH
microhenry
µs
microsecond
µV
microvolt
µW
microwatt
mA
milliampere
ms
millisecond
mV
millivolt
nA
nanoampere
ns
nanosecond
nV
nanovolt
ohm
pF
picofarad
ppm
parts per million
ps
picosecond
s
second
sps
samples per second
sqrtHz
square root of hertz
V
volt
Document Number: 001-87197 Rev. *J
Page 43 of 45
PSoC® 4: PSoC 4200
Family Datasheet
Revision History
Description Title: PSoC® 4: PSoC 4200 Family Datasheet Programmable System-on-Chip (PSoC®)
Document Number: 001-87197
Orig. of Submission
Revision
ECN
Description of Change
Change
Date
*B
4108562
WKA
08/29/2013 Added clarifying note about the XRES pin in the Reset section.
Updated UDB Array diagram.
Added a link reference to the PSoC 4 TRM.
Updated the footnote in Absolute Maximum Ratings.
Updated Sleep Mode IDD specs in DC Specifications.
Updated Comparator DC Specifications
Updated SAR ADC AC Specifications
Updated LCD Direct Drive DC Specifications
Updated the number of GPIOs in Ordering Information.
*C
4568937
MKEA/
11/19/2014 Added More Information and PSoC Creator sections.
WKA
Added 48-pin TQFP pin and package details.
Added SID308A spec details.
Updated Ordering Information.
*D
4617283
WKA
01/08/2015 Corrected typo in the ordering information table.
Updated 28-pin SSOP package diagram.
*E
4643655
WKA
04/29/2015 Added 35 WLCSP pinout and package detail information.
Updated CSD specifications.
*F
5287114
WKA
06/09/2016 Added reference to AN90071 in the More Information section.
Updated Flash section with details of flash protection modes.
Added notes in the Pinouts section.
Updated 40-pin QFN and 28-pin SSOP pin diagrams.
Added PSoC 4 Power Supply diagram.
Updated the Bypass Capacitors column in the Power Supply table.
Updated values for SID32, SID34, SID38, SID269, SID270, SID271.
Added SID299A.
Updated Comparator Specifications.
Updated TCPWM Specifications.
Updated values for SID149, SID160, SID171.
Updated Conditions for SID190.
Added BID55.
Removed Conditions for SID237.
Added reference to PSoC 4 CAB Libraries with Schematics Symbols and PCB
Footprints in the Packaging section.
*G
5327384
WKA
06/28/2016 Removed capacitor connection for Pin 15 in Figure 13.
*H
5702140
GNKK
04/19/2017 Updated the Cypress logo and copyright information.
*I
5738586
WKA
05/16/2017 Updated max value of SID61.
*J
5795966
WKA
07/10/2017 Changed Pin 33 name in 40-pin QFN Pinout from VDDD to VDDA to correct
typo; pinout table is correct and not changed.
Removed reference to swd_io[1] and swd_clk[1].
Corrected 44-TQFP Package Example.
Document Number: 001-87197 Rev. *J
Page 44 of 45
PSoC® 4: PSoC 4200
Family Datasheet
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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Products
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cypress.com/interface
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Memory
cypress.com/iot
cypress.com/memory
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cypress.com/mcu
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cypress.com/psoc
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Cypress Developer Community
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation 2013-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you under its copyright rights in the Software, a personal, non-exclusive, nontransferable license (without the right to sublicense) (a) for Software provided in source code form, to modify
and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either
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CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes to this document without further notice. Cypress does not
assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or
programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application
made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of
weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or
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and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-87197 Rev. *J
Revised July 10, 2017
Page 45 of 45
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