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CY8C4245PVS-472Z

CY8C4245PVS-472Z

  • 厂商:

    CYPRESS(赛普拉斯)

  • 封装:

    SSOP28

  • 描述:

    IC MCU 32BIT 32KB FLASH 28SSOP

  • 数据手册
  • 价格&库存
CY8C4245PVS-472Z 数据手册
Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com Automotive PSoC® 4: PSoC 4200 Family Datasheet ® Programmable System-on-Chip (PSoC ) Programmable System-on-Chip (PSoC®) General Description PSoC® 4 is a scalable and reconfigurable platform architecture for a family of mixed-signal programmable embedded system controllers with an Arm® Cortex™-M0 CPU, while being AEC-Q100 compliant. It combines programmable and re-configurable analog and digital blocks with flexible automatic routing. The PSoC 4200 product family, based on this platform, is a combination of a microcontroller with digital programmable logic, high-performance analog-to-digital conversion, opamp with Comparator mode, and standard communication and timing peripherals. The PSoC 4200 products will be fully upward compatible with members of the PSoC 4 platform for new applications and design needs. The programmable analog and digital subsystems allow flexibility and in-field tuning of the design. Features 32-bit MCU Subsystem Segment LCD Drive ■ Automotive Electronics Council (AEC) AEC-Q100 qualified ■ 48 MHz Arm Cortex-M0 CPU with single cycle multiply ■ Up to 32 kB of flash with Read Accelerator ■ Up to 4 kB of SRAM LCD drive supported on all pins (common or segment) ■ Operates in Deep Sleep mode with 4 bits per pin memory Serial Communication ■ Programmable Analog ■ ■ One opamp with reconfigurable high-drive external and high-bandwidth internal drive, Comparator mode, and ADC input buffering capability Two independent run-time reconfigurable serial communication blocks (SCBs) with reconfigurable I2C, SPI, UART, or LIN Slave 1.3, 2.1/2.2 functionality Timing and Pulse-Width Modulation ■ 12-bit, 1-Msps SAR ADC with differential and single-ended modes; Channel Sequencer with signal averaging ■ Four 16-bit Timer/Counter Pulse-Width Modulator (TCPWM) blocks ■ Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin ■ Center-aligned, Edge, and Pseudo-random modes ■ Two low-power comparators that operate in Deep Sleep ■ Comparator-based triggering of Kill signals for motor drive and other high-reliability digital logic applications Programmable Digital Up to 24 Programmable GPIOs ■ Four programmable logic blocks called universal digital blocks, (UDBs), each with 8 Macrocells and data path ■ Cypress-provided peripheral component library, user-defined state machines, and Verilog input ■ 28-pin SSOP package ■ Any GPIO pin can be CapSense, LCD, analog, or digital ■ Drive modes, strengths, and slew rates are programmable Temperature Ranges: Low Power 1.71 to 5.5 V operation ■ 20-nA Stop Mode with GPIO pin wakeup ■ A Grade: –40 °C to +85 °C ■ Hibernate and Deep Sleep modes allow wakeup-time versus power trade-offs ■ S Grade: –40 °C to +105 °C Capacitive Sensing PSoC Creator Design Environment ■ Integrated Development Environment (IDE) provides schematic design entry and build (with analog and digital automatic routing) Cypress-supplied software component makes capacitive sensing design easy ■ Applications Programming Interface (API) component for all fixed-function and programmable peripherals Automatic hardware tuning (SmartSense™) Industry-Standard Tool Compatibility ■ Cypress Capacitive Sigma-Delta (CSD) provides best-in-class SNR (>5:1) and water tolerance ■ ■ ■ Cypress Semiconductor Corporation Document Number: 001-93573 Rev. *G • 198 Champion Court After schematic entry, development can be done with Arm-based industry-standard development tools • San Jose, CA 95134-1709 • 408-943-2600 Revised March 8, 2019 Automotive PSoC® 4: PSoC 4200 Family Datasheet Contents Block Diagram .................................................................. 3 Functional Description ..................................................... 3 Functional Overview ........................................................ 4 CPU and Memory Subsystem ..................................... 4 System Resources ...................................................... 4 Analog Blocks .............................................................. 5 Programmable Digital .................................................. 6 Fixed Function Digital .................................................. 7 GPIO ........................................................................... 7 Special Function Peripherals ....................................... 8 Pinouts .............................................................................. 9 Power ............................................................................... 11 Unregulated External Supply ..................................... 11 Regulated External Supply ........................................ 11 Development Support .................................................... 12 Documentation .......................................................... 12 Online ........................................................................ 12 Tools .......................................................................... 12 Electrical Specifications ................................................ 13 Absolute Maximum Ratings ....................................... 13 Document Number: 001-93573 Rev. *G Device-Level Specifications ...................................... 14 Analog Peripherals .................................................... 18 Digital Peripherals ..................................................... 23 Memory ..................................................................... 26 System Resources .................................................... 27 Ordering Information ...................................................... 31 Part Numbering Conventions .................................... 31 Packaging ........................................................................ 32 Acronyms ........................................................................ 34 Document Conventions ................................................. 36 Units of Measure ....................................................... 36 Document History Page ................................................. 37 Sales, Solutions, and Legal Information ...................... 38 Worldwide Sales and Design Support ....................... 38 Products .................................................................... 38 PSoC® Solutions ...................................................... 38 Cypress Developer Community ................................. 38 Technical Support ..................................................... 38 Page 2 of 38 Automotive PSoC® 4: PSoC 4200 Family Datasheet Block Diagram C P U S ubs y s tem P S oC 4200 SWD 32-bit AH B-Lite C ortex M0 48 MH z F LA S H U p to 32 kB SRAM U p to 4 kB R OM 4 kB F AST M U L N VIC, IRQM X R ead Accelerator SR AM C ontroller R OM C ontroller System R eso u rces System Interconnect (Single Layer AH B ) P eripherals T est D F T Logic D F T Analog x1 SM X C TBm 1x Op Am p x1 UDB ... UD B x4 2x LP Comparator Reset R eset C ontrol XR ES SAR AD C (12-b it) Programmable D igital LCD IOSS GPIO (5x ports) Programmable Analog Capsense Clock C lock C ontrol WD T IM O ILO 2x SCB-I2C/SPI/UART Peripheral Interconnect (MMIO ) PC LK 4x TCPWM Pow er Sleep C ontrol WIC POR LVD R EF BOD PWR SYS N VLatches Po rt Interfa ce & D igita l Syste m In te rco n ne ct (D SI) H igh Spee d I/O M a trix Pow er M odes Active /Sleep D eep Sleep H ibernate 24x GPIOs IO S ubs y s tem Functional Description The PSoC 4200 devices include extensive support for programming, testing, debugging, and tracing both hardware and firmware. The Arm Serial_Wire Debug (SWD) interface supports all programming and debug features of the device. Complete debug-on-chip functionality enables full-device debugging in the final system using the standard production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the standard programming connections are required to fully support debug. The PSoC Creator IDE provides fully integrated programming and debug support for the PSoC 4200 devices. The SWD interface is fully compatible with industry-standard third-party tools. With the ability to disable debug features, with very robust flash protection, and allowing customer-proprietary functionality Document Number: 001-93573 Rev. *G to be implemented in on-chip programmable blocks, the PSoC 4200 family provides a level of security not possible with multi-chip application solutions or with microcontrollers. The debug circuits are enabled by default and can only be disabled in firmware. If not enabled, the only way to re-enable them is to erase the entire device, clear flash protection, and reprogram the device with new firmware that enables debugging. Additionally, all device interfaces can be permanently disabled (device security) for applications concerned about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and interrupting flash programming sequences. Because all programming, debug, and test interfaces are disabled when maximum device security is enabled, PSoC 4200 with device security enabled may not be returned for failure analysis. This is a trade-off PSoC 4200 allows the customer to make. Page 3 of 38 Automotive PSoC® 4: PSoC 4200 Family Datasheet Functional Overview System Resources CPU and Memory Subsystem Power System CPU The Cortex-M0 CPU in PSoC 4200 is part of the 32-bit MCU subsystem, which is optimized for low-power operation with extensive clock gating. It mostly uses 16-bit instructions and executes a subset of the Thumb-2 instruction set. This enables fully compatible binary upward migration of the code to higher performance processors such as the Cortex-M3 and M4, thus enabling upward compatibility. The Cypress implementation includes a hardware multiplier that provides a 32-bit result in one cycle. It includes a nested vectored interrupt controller (NVIC) block with 32 interrupt inputs and also includes a Wakeup Interrupt Controller (WIC). The WIC can wake the processor up from the Deep Sleep mode, allowing power to be switched off to the main processor when the chip is in the Deep Sleep mode. The Cortex-M0 CPU provides a Non-Maskable Interrupt (NMI) input, which is made available to the user when it is not in use for system functions requested by the user. The CPU also includes a debug interface, the serial wire debug (SWD) interface, which is a two-wire form of JTAG; the debug configuration used for PSoC 4200 has four break-point (address) comparators and two watchpoint (data) comparators. The power system is described in detail in the section Power on page 11. It provides assurance that voltage levels are as required for each respective mode and either delay mode entry (on power-on reset (POR), for example) until voltage levels are as required for proper function or generate resets (Brown-Out Detect (BOD)) or interrupts (Low Voltage Detect (LVD)). PSoC 4200 operates with a single external supply over the range of 1.71 V to 5.5 V and has five different power modes, transitions between which are managed by the power system. The PSoC 4200 provides Sleep, Deep Sleep, Hibernate, and Stop low-power modes. Clock System The PSoC 4200 clock system is responsible for providing clocks to all subsystems that require clocks and for switching between different clock sources without glitching. In addition, the clock system ensures that no metastable conditions occur. The clock system for PSoC 4200 consists of the IMO and the ILO internal oscillators and provision for an external clock. Figure 1. PSoC 4200 MCU Clocking Architecture IMO HFCLK Flash The PSoC 4200 device has a flash module with a flash accelerator, tightly coupled to the CPU to improve average access times from the flash block. The flash block is designed to deliver 1 wait-state (WS) access time at 48 MHz and with 0-WS access time at 24 MHz. The flash accelerator delivers 85% of single-cycle SRAM access performance on average. Part of the flash module can be used to emulate EEPROM operation if required. The PSoC 4200 flash supports the following flash protection modes at the Memory subsystem level. EXTCLK ILO HFCLK LFCLK SYSCLK Prescaler Open: No Protection. Factory default mode that the product is shipped in. Protected: User may change from Open to Protected. This mode disables Debug interface accesses. The mode can be set back to Open but only after completely erasing the flash. Kill: User may change from Open to Kill. This mode disables all Debug accesses. The part cannot be erased externally thus obviating the possibility of partial erasure by power interruption and potential malfunction and security leaks. This is an irrecvocable mode. In addition, Row level Read/Write protection is also supported to prevent inadvertent Writes as well as selectively block Reads. Flash Read/Write/Erase operations are always available for internal code using system calls. SRAM SRAM memory is retained during Hibernate. SROM A supervisory ROM that contains boot and configuration routines is provided. Document Number: 001-93573 Rev. *G UDB Dividers UDBn Analog Divider SAR clock Peripheral Dividers PERXYZ_CLK The HFCLK signal can be divided down (see PSoC 4200 MCU Clocking Architecture) to generate synchronous clocks for the UDBs, and the analog and digital peripherals. There are a total of 12 clock dividers for PSoC 4200, each with 16-bit divide capability; this allows eight to be used for the fixed-function blocks and four for the UDBs. The analog clock leads the digital clocks to allow analog events to occur before digital clock-related noise is generated. The 16-bit capability allows a lot of flexibility in generating fine-grained frequency values and is fully supported in PSoC Creator. When UDB-generated Pulse Interrupts are used, SYSCLK must equal HFCLK. Page 4 of 38 Automotive PSoC® 4: PSoC 4200 Family Datasheet Analog Blocks IMO Clock Source The IMO is the primary source of internal clocking in PSoC 4200. It is trimmed during testing to achieve the specified accuracy. Trim values are stored in nonvolatile latches (NVL). Additional trim settings from flash can be used to compensate for changes. The IMO default frequency is 24 MHz and it can be adjusted between 3 to 48 MHz in steps of 1 MHz. IMO Tolerance with Cypress-provided calibration settings is ±2%. ILO Clock Source The ILO is a very low power oscillator, which is primarily used to generate clocks for peripheral operation in Deep Sleep mode. ILO-driven counters can be calibrated to the IMO to improve accuracy. Cypress provides a software component, which does the calibration. Watchdog Timer A watchdog timer is implemented in the clock block running from the ILO; this allows watchdog operation during Deep Sleep and generates a watchdog reset if not serviced before the timeout occurs. The watchdog reset is recorded in the Reset Cause register. Reset PSoC 4200 can be reset from a variety of sources including a software reset. Reset events are asynchronous and guarantee reversion to a known state. The reset cause is recorded in a register, which is sticky through reset and allows software to determine the cause of the Reset. An XRES pin is reserved for external reset to avoid complications with configuration and multiple pin functions during power-on or reconfiguration. The XRES pin has an internal pull-up resistor that is always enabled. Voltage Reference The PSoC 4200 reference system generates all internally required references. A 1% voltage reference spec is provided for the 12-bit ADC. To allow better signal to noise ratios (SNR) and better absolute accuracy, it is possible to bypass the internal reference using a GPIO pin or to use an external reference for the SAR. 12-bit SAR ADC The 12-bit 1 MSample/second SAR ADC can operate at a maximum clock rate of 18 MHz and requires a minimum of 18 clocks at that frequency to do a 12-bit conversion. The block functionality is augmented for the user by adding a reference buffer to it (trimmable to ±1%) and by providing the choice (for the PSoC 4200 case) of three internal voltage references: VDD, VDD/2, and VREF (nominally 1.024 V) as well as an external reference through a GPIO pin. The Sample-and-Hold (S/H) aperture is programmable allowing the gain bandwidth requirements of the amplifier driving the SAR inputs, which determine its settling time, to be relaxed if required. System performance will be 65 dB for true 12-bit precision providing appropriate references are used and system noise levels permit. To improve performance in noisy conditions, it is possible to provide an external bypass (through a fixed pin location) for the internal reference amplifier. The SAR is connected to a fixed set of pins through an 8-input sequencer. The sequencer cycles through selected channels autonomously (sequencer scan) and does so with zero switching overhead (that is, aggregate sampling bandwidth is equal to 1 Msps whether it is for a single channel or distributed over several channels). The sequencer switching is effected through a state machine or through firmware driven switching. A feature provided by the sequencer is buffering of each channel to reduce CPU interrupt service requirements. To accommodate signals with varying source impedance and frequency, it is possible to have different sample times programmable for each channel. Also, signal range specification through a pair of range registers (low and high range values) is implemented with a corresponding out-of-range interrupt if the digitized value exceeds the programmed range; this allows fast detection of out-of-range values without the necessity of having to wait for a sequencer scan to be completed and the CPU to read the values and check for out-of-range values in software. The SAR is able to digitize the output of the on-board temperature sensor for calibration and other temperature-dependent functions. The SAR is not available in Deep Sleep and Hibernate modes as it requires a high-speed clock (up to 18 MHz). The SAR operating range is 1.71 to 5.5 V. Figure 2. SAR ADC System Diagram AHB System Bus and Programmable Logic Interconnect SAR Sequencer vminus vplus P7 Port 2 (8 inputs) SARMUX P0 Sequencing and Control Data and Status Flags POS SARADC NEG External Reference and Bypass (optional) Reference Selection VDD/2 VDDD VREF Inputs from other Ports Document Number: 001-93573 Rev. *G Page 5 of 38 Automotive PSoC® 4: PSoC 4200 Family Datasheet Figure 3. UDB Array Opamp (CTBm Block) System Interconnect CPU Sub-system Clocks 8 to 32 4 to 8 UDBIF BUS IF IRQ IF CLK IF Other Digital Signals in Chip Temperature Sensor PSoC 4200 has one on-chip temperature sensor This consists of a diode, which is biased by a current source that can be disabled to save power. The temperature sensor is connected to the ADC, which digitizes the reading and produces a temperature value using Cypress supplied software that includes calibration and linearization. Port Port PortIFIF IF DSI Routing Channels DSI UDB UDB UDB UDB High-Speed I/O Matrix PSoC 4200 has an opamp with Comparator mode which allow most common analog functions to be performed on-chip eliminating external components; PGAs, Voltage Buffers, Filters, Trans-Impedance Amplifiers, and other functions can be realized with external passives saving power, cost, and space. The on-chip opamp is designed with enough bandwidth to drive the Sample-and-Hold circuit of the ADC without requiring external buffering. Low-power Comparators PSoC 4200 has a pair of low-power comparators, which can also operate in the Deep Sleep and Hibernate modes. This allows the analog system blocks to be disabled while retaining the ability to monitor external voltage levels during low-power modes. The comparator outputs are normally synchronized to avoid metastability unless operating in an asynchronous power mode (Hibernate) where the system wake-up circuit is activated by a comparator switch event. Programmable Digital Universal Digital Blocks (UDBs) and Port Interfaces PSoC 4200 has four UDBs; the UDB array also provides a switched Digital System Interconnect (DSI) fabric that allows signals from peripherals and ports to be routed to and through the UDBs for communication and control. The UDB array is shown in the following figure. DSI DSI Programmable Digital Subsystem UDBs can be clocked from a clock divider block, from a port interface (required for peripherals such as SPI), and from the DSI network directly or after synchronization. A port interface is defined, which acts as a register that can be clocked with the same source as the PLDs inside the UDB array. This allows faster operation because the inputs and outputs can be registered at the port interface close to the I/O pins and at the edge of the array. The port interface registers can be clocked by one of the I/Os from the same port. This allows interfaces such as SPI to operate at higher clock speeds by eliminating the delay for the port input to be routed over DSI and used to register other inputs (see Figure 4). The UDBs can generate interrupts (one UDB at a time) to the interrupt controller. The UDBs retain the ability to connect to any pin on the chip through the DSI. Figure 4. Port Interface High Speed I/O Matrix To Clock Tree 8 Input Registers 7 Digital GlobalClocks 3 DSI Signals , 1 I/O Signal 6 Clock Selector Block from UDB 0 ... 2 0 3 2 1 0 [1] 4 8 [1] [0] To DSI Document Number: 001-93573 Rev. *G 6 Enables [1] 8 Reset Selector Block from UDB 7 [0] 2 4 Output Registers ... 9 4 8 8 From DSI [1] From DSI Page 6 of 38 Automotive PSoC® 4: PSoC 4200 Family Datasheet Fixed Function Digital ■ Timer/Counter/PWM Block The Timer/Counter/PWM block consists of four 16-bit counters with user-programmable period length. There is a Capture register to record the count value at the time of an event (which may be an I/O event), a period register which is used to either stop or auto-reload the counter when its count is equal to the period register, and compare registers to generate compare value signals which are used as PWM duty cycle outputs. The block also provides true and complementary outputs with programmable offset between them to allow use as deadband programmable complementary PWM outputs. It also has a Kill input to force outputs to a predetermined state; for example, this is used in motor drive systems when an overcurrent state is indicated and the PWMs driving the FETs need to be shut off immediately with no time for software intervention. Serial Communication Blocks (SCB) PSoC 4200 has two SCBs, which can each implement an I2C, UART, SPI, or LIN Slave interface. I2C Mode: The hardware I2C block implements a full multi-master and slave interface (it is capable of multimaster arbitration). This block is capable of operating at speeds of up to 1 Mbps (Fast Mode Plus) and has flexible buffering options to reduce interrupt overhead and latency for the CPU. The FIFO mode is available in all channels and is very useful in the absence of DMA. The I2C peripheral is compatible with the I2C Standard-mode, Fast-mode, and Fast-mode Plus devices as defined in the NXP I2C-bus specification and user manual (UM10204). The I2C bus I/O is implemented with GPIO in open-drain modes. The I2C bus uses open-drain drivers for clock and data with pull-up resistors on the bus for clock and data connected to all nodes. Required Rise and Fall times for different I2C speeds are guaranteed by using appropriate pull-up resistor values depending on VDD, Bus Capacitance, and resistor tolerance. For detailed information on how to calculate the optimum pull-up resistor value for your design, please refer to the UM10204 I2C bus specification and user manual, the newest revision is available at www.nxp.com. UART Mode: This is a full-feature UART operating at up to 1 Mbps. It supports automotive single-wire interface (LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the basic UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows addressing of peripherals connected over common RX and TX lines. Common UART functions such as parity error, break detect, and frame error are supported. An 8-deep FIFO allows much greater CPU service latencies to be tolerated. Note that hardware handshaking is not supported. This is not commonly used and can be implemented with a UDB-based UART in the system, if required. SPI Mode: The SPI mode supports full Motorola SPI, TI SSP (essentially adds a start pulse used to synchronize SPI Codecs), and National Microwire (half-duplex form of SPI). The SPI block can use the FIFO and also supports an EzSPI mode in which data interchange is reduced to reading and writing an array in memory. LIN Slave Mode: The LIN Slave mode uses the SCB hardware block and implements a full LIN slave interface. This LIN slave is compliant with LIN v1.3 and LIN v2.1/2.2 specification standards. It is certified by C&S GmbH based on the standard protocol and data link layer conformance tests. LIN slave can be operated at baud rates of up to ~20 Kbps with a maximum of 40-meter cable length. PSoC Creator software supports up to two LIN slave interfaces in the PSoC 4 device, providing built-in application programming interfaces (APIs) based on the LIN specification standard. GPIO PSoC 4200 has 24 GPIOs. The GPIO block implements the following: ■ Eight drive strength modes: ❐ Analog input mode (input and output buffers disabled) ❐ Input only ❐ Weak pull-up with strong pull-down ❐ Strong pull-up with weak pull-down ❐ Open drain with strong pull-down ❐ Open drain with strong pull-up ❐ Strong pull-up with strong pull-down ❐ Weak pull-up with weak pull-down ■ Input threshold select (CMOS or LVTTL). ■ Individual control of input and output buffer enabling/disabling in addition to the drive strength modes. ■ Hold mode for latching previous state (used for retaining I/O state in Deep Sleep mode and Hibernate modes). ■ Selectable slew rates for dV/dt related noise control to improve EMI. PSoC 4200 is not completely compliant with the I2C spec in the following respects: ■ GPIO cells are not overvoltage tolerant and, therefore, cannot be hot-swapped or powered up independently of the rest of the I2C system. ■ Fast-mode Plus has an IOL specification of 20 mA at a VOL of 0.4 V. The GPIO cells can sink a maximum of 8 mA IOL with a VOL maximum of 0.6 V. ■ Fast-mode and Fast-mode Plus specify minimum Fall times, which are not met with the GPIO cell; Slow strong mode can help meet this spec depending on the Bus Load. ■ When the SCB is an I2C Master, it interposes an IDLE state between NACK and Repeated Start; the I2C spec defines Bus free as following a Stop condition so other Active Masters do not intervene but a Master that has just become activated may start an Arbitration cycle. Document Number: 001-93573 Rev. *G When the SCB is in I2C Slave mode, and Address Match on External Clock is enabled (EC_AM = 1) along with operation in the internally clocked mode (EC_OP = 0), then its I2C address must be even. Page 7 of 38 Automotive PSoC® 4: PSoC 4200 Family Datasheet The pins are organized in logical entities called ports, which are 8-bit in width. During power-on and reset, the blocks are forced to the disable state so as not to crowbar any inputs and/or cause excess turn-on current. A multiplexing network known as a high-speed I/O matrix is used to multiplex between various signals that may connect to an I/O pin. Pin locations for fixed-function peripherals are also fixed to reduce internal multiplexing complexity (these signals do not go through the DSI network). DSI signals are not affected by this and any pin may be routed to any UDB through the DSI network. Data output and pin state registers store, respectively, the values to be driven on the pins and the states of the pins themselves. Every I/O pin can generate an interrupt if so enabled and each I/O port has an interrupt request (IRQ) and interrupt service routine (ISR) vector associated with it (5 for PSoC 4200). Special Function Peripherals LCD Segment Drive PSoC 4200 has an LCD controller which can drive up to four commons and up to 32 segments. It uses full digital methods to drive the LCD segments requiring no generation of internal LCD voltages. The two methods used are referred to as digital correlation and PWM. PWM pertains to driving the panel with PWM signals to effectively use the capacitance of the panel to provide the integration of the modulated pulse-width to generate the desired LCD voltage. This method results in higher power consumption but can result in better results when driving TN displays. LCD operation is supported during Deep Sleep refreshing a small display buffer (4 bits; 1 32-bit register per port). CapSense CapSense is supported on all pins in PSoC 4200 through a CapSense Sigma-Delta (CSD) block that can be connected to any pin through an analog mux bus that any GPIO pin can be connected to via an Analog switch. CapSense function can thus be provided on any pin or group of pins in a system under software control. A component is provided for the CapSense block to make it easy for the user. Shield voltage can be driven on another Mux Bus to provide water tolerance capability. Water tolerance is provided by driving the shield electrode in phase with the sense electrode to keep the shield capacitance from attenuating the sensed input. The CapSense block has two IDACs which can be used for general purposes if CapSense is not being used.(both IDACs are available in that case) or if CapSense is used without water tolerance (one IDAC is available). Digital correlation pertains to modulating the frequency and levels of the common and segment signals to generate the highest RMS voltage across a segment to light it up or to keep the RMS signal zero. This method is good for STN displays but may result in reduced contrast with TN (cheaper) displays. Document Number: 001-93573 Rev. *G Page 8 of 38 Automotive PSoC® 4: PSoC 4200 Family Datasheet Pinouts The following is the pin-list for PSoC 4200. Port 2 comprises of the high-speed Analog inputs for the SAR Mux. P1.7 is the optional external input and bypass for the SAR reference. Ports 3 and 4 contain the Digital Communication channels. All pins support CSD CapSense and Analog Mux Bus connections. Pins 28-SSOP Name Alternate Functions for Pins Analog Alt 1 Alt 2 Alt 3 Alt 4 Pin Description Name Type Pin VSSD Power DN – – – – – – Digital Ground P2.2 GPIO 5 P2.2 sarmux.2 – – – – Port 2 Pin 2: gpio, lcd, csd, sarmux P2.3 GPIO 6 P2.3 sarmux.3 – – – – Port 2 Pin 3: gpio, lcd, csd, sarmux P2.4 GPIO 7 P2.4 sarmux.4 tcpwm0_p[1] – – – Port 2 Pin 4: gpio, lcd, csd, sarmux, pwm P2.5 GPIO 8 P2.5 sarmux.5 tcpwm0_n[1] – – – Port 2 Pin 5: gpio, lcd, csd, sarmux, pwm P2.6 GPIO 9 P2.6 sarmux.6 tcpwm1_p[1] – – – Port 2 Pin 6: gpio, lcd, csd, sarmux, pwm P2.7 GPIO 10 P2.7 sarmux.7 tcpwm1_n[1] – – – Port 2 Pin 7: gpio, lcd, csd, sarmux, pwm P3.0 GPIO 11 P3.0 – tcpwm0_p[0] scb1_uart_rx[0] scb1_i2c_scl[0] scb1_spi_mosi[0] Port 3 Pin 0: gpio, lcd, csd, pwm, scb1 P3.1 GPIO 12 P3.1 – tcpwm0_n[0] scb1_uart_tx[0] scb1_i2c_sda[0] scb1_spi_miso[0] Port 3 Pin 1: gpio, lcd, csd, pwm, scb1 P3.2 GPIO 13 P3.2 – tcpwm1_p[0] – swd_io scb1_spi_clk[0] Port 3 Pin 2: gpio, lcd, csd, pwm, scb1, swd P3.3 GPIO 14 P3.3 – tcpwm1_n[0] – swd_clk scb1_spi_ssel_0[0] Port 3 Pin 3: gpio, lcd, csd, pwm, scb1, swd P4.0 GPIO 15 P4.0 – – scb0_uart_rx scb0_i2c_scl scb0_spi_mosi Port 4 Pin 0: gpio, lcd, csd, scb0 P4.1 GPIO 16 P4.1 – – scb0_uart_tx scb0_i2c_sda scb0_spi_miso Port 4 Pin 1: gpio, lcd, csd, scb0 P4.2 GPIO 17 P4.2 csd_c_mod – – – scb0_spi_clk Port 4 Pin 2: gpio, lcd, csd, scb0 P4.3 GPIO 18 P4.3 csd_c_sh_tan k – – – scb0_spi_ssel_0 Port 4 Pin 3: gpio, lcd, csd, scb0 P0.0 GPIO 19 P0.0 comp1_inp – – – scb0_spi_ssel_1 Port 0 Pin 0: gpio, lcd, csd, scb0, comp P0.1 GPIO 20 P0.1 comp1_inn – – – scb0_spi_ssel_2 Port 0 Pin 1: gpio, lcd, csd, scb0, comp P0.2 GPIO 21 P0.2 comp2_inp – – – scb0_spi_ssel_3 Port 0 Pin 2: gpio, lcd, csd, scb0, comp P0.3 GPIO 22 P0.3 comp2_inn – – – – Port 0 Pin 3: gpio, lcd, csd, comp P0.6 GPIO 23 P0.6 – ext_clk – – scb1_spi_clk[1] Port 0 Pin 6: gpio, lcd, csd, scb1, ext_clk P0.7 GPIO 24 P0.7 – – – wakeup scb1_spi_ssel_0[1] Port 0 Pin 7: gpio, lcd, csd, scb1, wakeup XRES XRES 25 XRES – – – – – Chip reset, active low VCCD Power 26 VCCD – – – – – Regulated supply, connect to 1 µF cap or 1.8 V VDDD Power 27 VDDD – – – – – Common power supply (Analog and Digital) 1.8 V–5.5 V VSSA Power 28(DN) VSS – – – – – Analog Ground P1.0 GPIO 1 P1.0 ctb.oa0.inp tcpwm2_p[1] – – – Port 1 Pin 0: gpio, lcd, csd, ctb, pwm P1.1 GPIO 2 P1.1 ctb.oa0.inm tcpwm2_n[1] – – – Port 1 Pin 1: gpio, lcd, csd, ctb, pwm P1.2 GPIO 3 P1.2 ctb.oa0.out tcpwm3_p[1] – – – Port 1 Pin 2: gpio, lcd, csd, ctb, pwm P1.7 GPIO 4 P1.7 ctb.oa1.inp_alt ext_vref – – – – Port 1 Pin 7: gpio, lcd, csd, ext_ref Notes: 1. tcpwm_p and tcpwm_n refer to tcpwm non-inverted and inverted outputs respectively. 2. P3.2 and P3.3 are SWD pins after boot (reset). Descriptions of the Pin functions are as follows: VDDD: Power supply for both analog and digital sections (where there is no VDDA pin). VDDA: Analog VDD pin where package pins allow; shorted to VDDD otherwise. Document Number: 001-93573 Rev. *G Page 9 of 38 Automotive PSoC® 4: PSoC 4200 Family Datasheet VSSA: Analog ground pin where package pins allow; shorted to VSS otherwise VSS: Ground pin. VCCD: Regulated Digital supply (1.8 V ±5%). Port Pins can all be used as LCD Commons, LCD Segment drivers, or CSD sense and shield pins can be connected to AMUXBUS A or B or can all be used as GPIO pins that can be driven by firmware or DSI signals. The following package is supported: 28-pin SSOP. Figure 5. 28-pin SSOP pinout (GPIO)P1[0] (GPIO)P1[1] (GPIO)P1[2] (GPIO)P1[7] (GPIO)P2[2] (GPIO)P2[3] (GPIO)P2[4] (GPIO)P2[5] (GPIO)P2[6] (GPIO)P2[7] (GPIO)P3[0] (GPIO)P3[1] (GPIO)P3[2] (GPIO)P3[3] Document Number: 001-93573 Rev. *G 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SSOP (Top View) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS VDDD VCCD XRES (GPIO)P0[7] (GPIO)P0[6] (GPIO)P0[3] (GPIO)P0[2] (GPIO)P0[1] (GPIO)P0[0] (GPIO)P4[3] (GPIO)P4[2] (GPIO)P4[1] (GPIO)P4[0] Page 10 of 38 Automotive PSoC® 4: PSoC 4200 Family Datasheet Power The following power system diagram shows the minimum set of power supply pins as implemented for PSoC 4200. The system has one regulator in Active mode for the digital circuitry. There is no analog regulator; the analog circuits run directly from the VDDA input. There are separate regulators for the Deep Sleep and Hibernate (lowered power supply and retention) modes. There is a separate low-noise regulator for the bandgap. The supply voltage range is 1.71 to 5.5 V with all functions and circuits operating over that range. Figure 6. PSoC 4 Power Supply Digital Domain Bypass capacitors must be used from VDDD to ground, typical practice for systems in this frequency range is to use a capacitor in the 1 µF range in parallel with a smaller capacitor (0.1 µF for example). Note that these are simply rules of thumb and that, for critical applications, the PCB layout, lead inductance, and the Bypass capacitor parasitic should be simulated to design and obtain optimal bypassing. Table 1. Example of a bypass scheme Power Supply VDDD–VSS Bypass Capacitors 0.1 µF ceramic capacitor (C2) plus bulk capacitor 1 to 10 µF (C1). Total Capacitance may be greater than 10 µF. VCCD–VSS 1 µF ceramic capacitor at the VCCD pin (C3) VREF–VSS (optional) The internal bandgap may be bypassed with a 1 µF to 10 µF capacitor. Total capacitance may be greater than 10 µF. Figure 7. 28-pin SSOP Example VDDD VDDD 1.8 Volt Reg VCCD VSS 0.1 µF C2 VSSD The PSoC 4200 family allows two distinct modes of power supply operation: Unregulated External Supply, and Regulated External Supply modes. Unregulated External Supply In this mode, the PSoC 4200 is powered by an External Power Supply that can be anywhere in the range of 1.8 to 5.5V. This range is also designed for battery-powered operation, for instance, the chip can be powered from a battery system that starts at 3.5V and works down to 1.8V. In this mode, the internal regulator of the PSoC 4200 supplies the internal logic and the VCCD output of the PSoC 4200 must be bypassed to ground via an external Capacitor (in the range of 1 to 1.6 µF; X5R ceramic or better). Document Number: 001-93573 Rev. *G C1 1µF VSS (GPIO )P1[0] (GPIO)P1[1] (GPIO )P1[2] ( GPIO) P1[7] ( GPIO) P2[2] (GPIO ) P2[3] (GPIO ) P2[4] (GPIO ) P2[5] (GPIO) P2[6] (GPIO) P2[7] ( GPIO) P3[0] (GPIO )P3[1] (GPIO )P3[2] (GPIO )P3[3] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SSOP ( Top View) VSS 28 VDDD27 VCCD26 25 24 23 22 21 20 19 18 17 16 15 XRES ( GPIO) P0[7] ( GPIO) P0[6] ( GPIO) P0[3] ( GPIO) P0[2] ( GPIO) P0[1] ( GPIO) P0[0] ( GPIO) P4[3] ( GPIO)P4[2] ( GPIO)P4[1] ( GPIO)P4[0] C3 1µF VSS Regulated External Supply In this mode, PSoC 4200 is powered by an external power supply that must be within the range of 1.71 to 1.89 V (1.8 ± 5%); note that this range needs to include power supply ripple too. In this mode, VCCD, and VDDD pins are all shorted together and bypassed. The internal regulator is disabled in firmware. Page 11 of 38 Automotive PSoC® 4: PSoC 4200 Family Datasheet Development Support The PSoC 4200 family has a rich set of documentation, development tools, and online resources to assist you during your development process. Visit www.cypress.com/go/psoc4 to find out more. Documentation A suite of documentation supports the PSoC 4200 family to ensure that you can find answers to your questions quickly. This section contains a list of some of the key documents. Software User Guide: A step-by-step guide for using PSoC Creator. The software user guide shows you how the PSoC Creator build process works in detail, how to use source control with PSoC Creator, and much more. Component Datasheets: The flexibility of PSoC allows the creation of new peripherals (components) long after the device has gone into production. Component data sheets provide all of the information needed to select and use a particular component, including a functional description, API documentation, example code, and AC/DC specifications. motor control and on-chip filtering. Application notes often include example projects in addition to the application note document. Technical Reference Manual: The Technical Reference Manual (TRM) contains all the technical detail you need to use a PSoC device, including a complete description of all PSoC registers. The TRM is available in the Documentation section at www.cypress.com/psoc4. Online In addition to print documentation, the Cypress PSoC forums connect you with fellow PSoC users and experts in PSoC from around the world, 24 hours a day, 7 days a week. Tools With industry standard cores, programming, and debugging interfaces, the PSoC 4200 family is part of a development tool ecosystem. Visit us at www.cypress.com/go/psoccreator for the latest information on the revolutionary, easy to use PSoC Creator IDE, supported third party compilers, programmers, debuggers, and development kits. Application Notes: PSoC application notes discuss a particular application of PSoC in depth; examples include brushless DC Document Number: 001-93573 Rev. *G Page 12 of 38 Automotive PSoC® 4: PSoC 4200 Family Datasheet Electrical Specifications Absolute Maximum Ratings Table 2. Absolute Maximum Ratings[1] Spec ID# Parameter Description Min Typ Max Units Details/ Conditions SID1 VDDD_ABS Digital supply relative to Vssd –0.5 – 6 V Absolute max SID2 VCCD_ABS –0.5 – 1.95 V Absolute max SID3 VGPIO_ABS Direct digital core voltage input relative to Vssd GPIO voltage –0.5 – VDD+0.5 V Absolute max SID4 IGPIO_ABS Maximum current per GPIO –25 – 25 mA Absolute max SID5 IGPIO_injection GPIO injection current, Max for VIH > VDDD, and Min for VIL < VSS –0.5 – 0.5 mA Absolute max, current injected per pin BID44 ESD_HBM 2200 – – V BID45 ESD_CDM 500 – – V BID46 LU Electrostatic discharge human body model Electrostatic discharge charged device model Pin current for latch-up –200 – 200 mA Note 1. Usage above the absolute maximum conditions listed in Table 2 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods of time may affect device reliability. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification. Document Number: 001-93573 Rev. *G Page 13 of 38 Automotive PSoC® 4: PSoC 4200 Family Datasheet Device-Level Specifications All specifications are valid for –40 °C  TA  85 °C for A grade devices and -40 °C  TA  105 °C for S grade devices, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. Table 3. DC Specifications Spec ID# Parameter Description Min Typ Max Units Details/ Conditions SID53 VDD Power supply input voltage (VDDA = VDDD = VDD) 1.8 – 5.5 V With regulator enabled SID255 VDDD Power supply input voltage unregulated 1.71 1.8 1.89 V Internally unregulated supply SID54 VCCD Output voltage (for core logic) – 1.8 – V SID55 CEFC External regulator voltage bypass 1 1.3 1.6 µF X5R ceramic or better SID56 CEXC Power supply decoupling capacitor – 1 – µF X5R ceramic or better 2.8 mA Active Mode, VDD = 1.71 V to 5.5 V. Typical values measured at VDD = 3.3 V SID9 IDD4 Execute from Flash; CPU at 6 MHz – – SID10 IDD5 Execute from Flash; CPU at 6 MHz – 2.2 – mA SID12 IDD7 Execute from Flash; CPU at 12 MHz – – 4.2 mA SID13 IDD8 Execute from Flash; CPU at 12 MHz – 3.7 – mA T = 25 °C SID16 IDD11 Execute from Flash; CPU at 24 MHz – 6.7 – mA T = 25 °C SID17 IDD12 Execute from Flash; CPU at 24 MHz – – 7.2 mA SID19 IDD14 Execute from Flash; CPU at 48 MHz – 12.8 – mA SID20 IDD15 Execute from Flash; CPU at 48 MHz – – 13.8 mA T = 25 °C T = 25 °C Sleep Mode, VDD = 1.7 V to 5.5 V SID25 IDD20 I2C wakeup, WDT, and Comparators on. 6 MHz – 1.3 1.8 mA VDD = 1.71 V to 5.5 V SID25A IDD20A I2C wakeup, WDT, and Comparators on. 12 MHz – 1.7 2.2 mA VDD = 1.71 V to 5.5 V – 1.3 – µA T = 25 °C – – 45 µA T = 85 °C – 1.5 15 µA Typ at 25 °C Max at 85 °C Deep Sleep Mode, VDD = 1.8 V to 3.6V (Regulator on) SID31 SID32 IDD26 IDD27 I2C wakeup and WDT on 2 I C wakeup and WDT on Deep Sleep Mode, VDD = 3.6 V to 5.5 V SID34 IDD29 I2C wakeup and WDT on Deep Sleep Mode, VDD = 1.71 V to 1.89 V (Regulator bypassed) SID37 SID38 IDD32 I2C wakeup and WDT on – 1.7 – µA T = 25 °C IDD33 I2C – – 60 µA T = 85 °C wakeup and WDT on Deep Sleep Mode, +105 °C SID33Q IDD28Q I2C wakeup and WDT on. Regulator Off. – – 135 µA VDD = 1.71 V to 1.89 V SID34Q IDD29Q I2C wakeup and WDT on – – 180 µA VDD = 1.8 V to 3.6 V SID35Q IDD30Q I2C wakeup and WDT on – – 140 µA VDD = 3.6 V to 5.5 V Hibernate Mode, VDD = 1.8 V to 3.6 V (Regulator on) SID40 IDD35 GPIO & Reset active – 150 – nA T = 25 °C SID41 IDD36 GPIO & Reset active – – 1000 nA T = 85 °C Document Number: 001-93573 Rev. *G Page 14 of 38 Automotive PSoC® 4: PSoC 4200 Family Datasheet Table 3. DC Specifications (continued) Spec ID# Parameter Description Details/ Conditions Min Typ Max Units – 150 – nA T = 25 °C Hibernate Mode, VDD = 3.6 V to 5.5 V SID43 IDD38 GPIO & Reset active Hibernate Mode, VDD = 1.71 V to 1.89 V (Regulator bypassed) SID46 IDD41 GPIO & Reset active – 150 – nA T = 25 °C SID47 IDD42 GPIO & Reset active – – 1000 nA T = 85 °C Regulator Off – – 19.4 µA VDD = 1.71 V to 1.89 V Hibernate Mode, +105 °C SID42Q IDD37Q SID43Q IDD38Q – – 17 µA VDD = 1.8 V to 3.6 V SID44Q IDD39Q – – 16 µA VDD = 3.6 V to 5.5 V Stop Mode current; VDD = 3.3 V – 20 80 nA Typ at 25 °C Max at 85 °C Stop Mode current; VDD = 5.5 V – 20 750 nA Typ at 25 °C Max at 85 °C IDD43AQ Stop Mode current; VDD = 3.6 V – – 5645 nA IDD_XR Supply current while XRES asserted – 2 5 mA Min Typ Max Units Stop Mode SID304 IDD43A Stop Mode, +105 °C SID304Q XRES current SID307 Table 4. AC Specifications Spec ID# Parameter Description SID48 FCPU CPU frequency DC – 48 MHz SID49 TSLEEP Wakeup from sleep mode – 0 – µs SID50 TDEEPSLEEP Wakeup from Deep Sleep mode – – 25 µs SID51 THIBERNATE Wakeup from Hibernate and Stop modes – – 2 ms SID52 TRESETWIDTH External reset pulse width 1 – – µs Document Number: 001-93573 Rev. *G Details/ Conditions 1.71 VDD 5.5 Guaranteed by characterization 24-MHz IMO. Guaranteed by characterization Guaranteed by characterization Guaranteed by characterization Page 15 of 38 Automotive PSoC® 4: PSoC 4200 Family Datasheet GPIO Table 5. GPIO DC Specifications SID57 VIH[2] Input voltage high threshold 0.7 × VDDD – – V Details/ Conditions CMOS Input SID58 VIL Input voltage low threshold – – V CMOS Input VIH[2] 0.3 × VDDD LVTTL input, VDDD < 2.7 V 0.7× VDDD – – V VIL LVTTL input, VDDD < 2.7 V – – 0.3 × VDDD V LVTTL input, VDDD  2.7 V 2.0 – – V Spec ID# SID241 SID242 SID243 Parameter VIH[2] Description Min Typ Max Units SID244 VIL LVTTL input, VDDD  2.7 V – – 0.8 V SID59 VOH Output voltage high level VDDD –0.6 – – V SID60 VOH Output voltage high level VDDD –0.5 – – V SID61 VOL Output voltage low level – – 0.6 V SID62 VOL Output voltage low level – – 0.6 V SID62A VOL Output voltage low level – – 0.4 V SID63 RPULLUP Pull-up resistor 3.5 5.6 8.5 kΩ SID64 RPULLDOWN Pull-down resistor 3.5 5.6 8.5 kΩ SID65 IIL Input leakage current (absolute value) – – 2 nA SID65A IIL_CTBM – – 4 nA SID66 CIN Input leakage current (absolute value) for CTBM pins Input capacitance – – 7 pF SID67 VHYSTTL Input hysteresis LVTTL 25 40 – mV SID68 VHYSCMOS Input hysteresis CMOS 0.05 × VDDD – – mV SID69 IDIODE Current through protection diode to VDD/VSS – – 100 µA SID69A ITOT_GPIO Maximum Total Source or Sink Chip Current – – 200 mA IOH = 4 mA at 3 V VDDD IOH = 1 mA at 1.8 V VDDD IOL = 4 mA at 1.8 V VDDD IOL = 8 mA at 3 V VDDD IOL = 3 mA at 3 V VDDD 25 °C, VDDD = 3.0 V VDDD  2.7 V. Guaranteed by characterization Guaranteed by characterization Guaranteed by characterization Guaranteed by characterization Note 2. VIH must not exceed VDDD + 0.2 V. Document Number: 001-93573 Rev. *G Page 16 of 38 Automotive PSoC® 4: PSoC 4200 Family Datasheet Table 6. GPIO AC Specifications (Guaranteed by Characterization) Spec ID# Parameter Description Min Typ Max Units Details/ Conditions SID70 TRISEF Rise time in fast strong mode 2 – 12 ns 3.3 V VDDD, Cload = 25 pF SID71 TFALLF Fall time in fast strong mode 2 – 12 ns 3.3 V VDDD, Cload = 25 pF SID72 TRISES Rise time in slow strong mode 10 – 60 3.3 V VDDD, Cload = 25 pF SID73 TFALLS Fall time in slow strong mode 10 – 60 3.3 V VDDD, Cload = 25 pF SID74 FGPIOUT1 GPIO Fout;3.3 V  VDDD 5.5 V. Fast strong mode. – – 33 MHz 90/10%, 25 pF load, 60/40 duty cycle SID75 FGPIOUT2 GPIO Fout;1.7 VVDDD3.3 V. Fast strong mode. – – 16.7 MHz 90/10%, 25 pF load, 60/40 duty cycle SID76 FGPIOUT3 GPIO Fout;3.3 V VDDD 5.5 V. Slow strong mode. – – 7 MHz 90/10%, 25 pF load, 60/40 duty cycle SID245 FGPIOUT4 GPIO Fout;1.7 V VDDD 3.3 V. Slow strong mode. – – 3.5 MHz 90/10%, 25 pF load, 60/40 duty cycle SID246 FGPIOIN GPIO input operating frequency; 1.71 V VDDD 5.5 V – – 48 MHz 90/10% VIO Min Typ Max Units XRES Table 7. XRES DC Specifications Spec ID# Parameter Description Details/ Conditions SID77 VIH Input voltage high threshold 0.7 × VDDD – – V CMOS Input SID78 VIL Input voltage low threshold – – 0.3 × VDDD V CMOS Input SID79 RPULLUP Pull-up resistor 3.5 5.6 8.5 kΩ SID80 CIN Input capacitance – 3 – pF SID81 VHYSXRES Input voltage hysteresis – 100 – mV Guaranteed by characterization SID82 IDIODE Current through protection diode to VDDD/VSS – – 100 µA Guaranteed by characterization Min 1 Typ – Max – Units µs Table 8. XRES AC Specifications Spec ID# SID83 Parameter TRESETWIDTH Description Reset pulse width Document Number: 001-93573 Rev. *G Details/ Conditions Guaranteed by characterization Page 17 of 38 Automotive PSoC® 4: PSoC 4200 Family Datasheet Analog Peripherals Opamp Table 9. Opamp Specifications (Guaranteed by Characterization) Spec ID# Parameter Description Min Typ Max Units – – – – IDD Opamp block current. No load. SID269 IDD_HI Power = high – 1100 1850 µA SID270 IDD_MED Power = medium – 550 950 µA SID271 IDD_LOW Power = low – 150 350 µA GBW Load = 20 pF, 0.1 mA. VDDA = 2.7 V – – – – SID272 GBW_HI Power = high 6 – – MHz SID273 GBW_MED Power = medium 4 – – MHz SID274 GBW_LO Power = low – 1 – MHz IOUT_MAX VDDA  2.7 V, 500 mV from rail – – – – SID275 IOUT_MAX_HI Power = high 10 – – mA SID276 IOUT_MAX_MID Power = medium 10 – – mA SID277 IOUT_MAX_LO Power = low – 5 – mA IOUT VDDA = 1.71 V, 500 mV from rail – – – – SID278 IOUT_MAX_HI Power = high 4 – – mA SID279 IOUT_MAX_MID Power = medium 4 – – mA SID280 IOUT_MAX_LO Power = low – 2 – mA SID281 VIN Charge pump on, VDDA  2.7 V –0.05 – VDDA – 0.2 V SID282 VCM Charge pump on, VDDA  2.7 V –0.05 – VDDA – 0.2 V VOUT VDDA  2.7 V – – – Details/ Conditions SID283 VOUT_1 Power = high, Iload=10 mA 0.5 – VDDA – 0.5 V SID284 VOUT_2 Power = high, Iload=1 mA 0.2 – VDDA – 0.2 V SID285 VOUT_3 Power = medium, Iload=1 mA 0.2 – VDDA – 0.2 V SID286 VOUT_4 Power = low, Iload=0.1mA 0.2 – VDDA – 0.2 V SID288 VOS_TR Offset voltage, trimmed 1 ±0.5 1 mV High mode SID288A VOS_TR Offset voltage, trimmed – ±1 – mV Medium mode SID288B VOS_TR Offset voltage, trimmed – ±2 – mV Low mode SID290 VOS_DR_TR Offset voltage drift, trimmed –10 ±3 10 µV/°C SID290Q VOS_DR_TR Offset voltage drift, trimmed –15 ±3 15 μV/°C SID290A VOS_DR_TR Offset voltage drift, trimmed – ±10 – µV/°C High mode. TA < 85 °C. High mode. TA ≤ 105 °C Medium mode SID290B VOS_DR_TR Offset voltage drift, trimmed – ±10 – µV/°C Low mode SID291 CMRR DC 70 80 – dB VDDD = 3.6 V PSRR At 1 kHz, 100 mV ripple 70 85 – dB VDDD = 3.6 V – – – – SID292 Noise SID293 VN1 SID294 SID295 SID296 – 94 – µVrms VN2 Input referred, 1 Hz - 1GHz, power = high Input referred, 1 kHz, power = high – 72 – nV/rtHz VN3 Input referred, 10kHz, power = high – 28 – nV/rtHz VN4 Input referred, 100kHz, power = high – 15 – nV/rtHz Document Number: 001-93573 Rev. *G Page 18 of 38 Automotive PSoC® 4: PSoC 4200 Family Datasheet Table 9. Opamp Specifications (continued) (Guaranteed by Characterization) Spec ID# Parameter SID297 Cload SID298 Slew_rate SID299 T_op_wake Description Min Typ Max Units – – 125 pF 6 – – V/µs – 300 – µs – – – – 90 – dB – 150 – ns SID299A OL_GAIN Stable up to maximum load. Performance specs at 50 pF. Cload = 50 pF, Power = High, VDDA  2.7 V From disable to enable, no external RC dominating Comparator mode; 50 mV drive, Trise = Tfall (approx.) Open Loop Gain SID300 TPD1 Response time; power = high SID301 TPD2 Response time; power = medium – 400 – ns SID302 TPD3 Response time; power = low – 2000 – ns SID303 Vhyst_op Hysteresis – 10 – mV Min Typ Max Units Comp_mode Details/ Conditions Guaranteed by Design Comparator Table 10. Comparator DC Specifications Spec ID# Parameter Description Details/ Conditions SID85 VOFFSET2 Input offset voltage, Common Mode voltage range from 0 to VDD-1 – – ±4 mV SID85A VOFFSET3 Input offset voltage. Ultra low-power mode (VDDD ≥ 2.2 V for Temp < 0 °C, VDDD ≥ 1.8 V for Temp > 0 °C) – ±12 – mV SID86 VHYST Hysteresis when enabled, Common Mode voltage range from 0 to VDD -1. – 10 35 mV Guaranteed by characterization SID87 VICM1 Input common mode voltage in normal mode 0 – VDDD – 0.1 V Modes 1 and 2. SID247 VICM2 Input common mode voltage in low power mode (VDDD ≥ 2.2 V for Temp < 0 °C, VDDD ≥ 1.8 V for Temp > 0 °C) 0 – VDDD V SID247A VICM3 Input common mode voltage in ultra low power mode 0 – VDDD – 1.15 V SID88 CMRR Common mode rejection ratio 50 – – dB VDDD  2.7 V. Guaranteed by characterization SID88A CMRR Common mode rejection ratio 42 – – dB VDDD  2.7 V. Guaranteed by characterization SID89 ICMP1 Block current, normal mode – – 400 µA Guaranteed by characterization SID248 ICMP2 Block current, low power mode – – 100 µA Guaranteed by characterization SID259 ICMP3 Block current, ultra low power mode (VDDD ≥ 2.2 V for Temp < 0 °C, VDDD ≥ 1.8 V for Temp > 0 °C) – 6 28 µA Guaranteed by characterization SID90 ZCMP DC input impedance of comparator 35 – – MΩ Guaranteed by characterization Document Number: 001-93573 Rev. *G Page 19 of 38 Automotive PSoC® 4: PSoC 4200 Family Datasheet Table 11. Comparator AC Specifications (Guaranteed by Characterization) Min Typ Max Units SID91 Spec ID# TRESP1 Parameter Response time, normal mode Description – – 110 ns 50 mV overdrive Details/Conditions SID258 TRESP2 Response time, low power mode – – 200 ns 50 mV overdrive SID92 TRESP3 Response time, ultra low power mode (VDDD ≥ 2.2 V for Temp < 0 °C, VDDD ≥ 1.8 V for Temp > 0 °C) – – 15 µs 200 mV overdrive Min Typ Max Units Details/Conditions –5 ±1 +5 °C –40 to +85 °C Min Typ Max Units bits Temperature Sensor Table 12. Temperature Sensor Specifications Spec ID# SID93 Parameter TSENSACC Description Temperature sensor accuracy SAR ADC Table 13. SAR ADC DC Specifications Spec ID# Parameter Description Details/Conditions SID94 A_RES Resolution – – 12 SID95 A_CHNIS_S Number of channels - single ended – – 8 8 full speed SID96 A-CHNKS_D Number of channels - differential – – 4 Diff inputs use neighboring I/O SID97 A-MONO Monotonicity – – – Yes. Based on characterization SID98 A_GAINERR Gain error – – ±0.1 % SID99 A_OFFSET Input offset voltage – – 2 mV SID100 A_ISAR Current consumption – – 1 mA SID101 A_VINS Input voltage range - single ended VSS – VDDA V Based on device characterization SID102 A_VIND Input voltage range - differential VSS – VDDA V Based on device characterization SID103 A_INRES Input resistance – – 2.2 KΩ Based on device characterization SID104 A_INCAP Input capacitance – – 10 pF Based on device characterization Document Number: 001-93573 Rev. *G With external reference. Guaranteed by characterization Measured with 1-V VREF. Guaranteed by characterization Page 20 of 38 Automotive PSoC® 4: PSoC 4200 Family Datasheet Table 14. SAR ADC AC Specifications (Guaranteed by Characterization) Spec ID# SID106 Parameter A_PSRR Description Power supply rejection ratio Min 70 Typ – Max – Units dB SID107 A_CMRR Common mode rejection ratio 66 – – dB SID108 A_SAMP_1 – – 1 Msps SID108A A_SAMP_2 – – 500 Ksps SID108B A_SAMP_3 – – 100 Ksps SID109 A_SNDR 65 – – dB SID111 A_INL Sample rate with external reference bypass cap Sample rate with no bypass cap. Reference = VDD Sample rate with no bypass cap. Internal reference Signal-to-noise and distortion ratio (SINAD) Integral non linearity –1.7 – +2 LSB –1.9 – +2 LSB –1.5 – +1.7 LSB –1.9 – +2 LSB –1.5 – +1.7 LSB –1 – +2.2 LSB –1 – +2.3 LSB –1 – +2 LSB –1 – +2.2 LSB SID111A A_INL Integral non linearity SID111B A_INL Integral non linearity SID112 A_DNL Differential non linearity SID112A A_DNL Differential non linearity SID112B A_DNL Differential non linearity –1 – +2.2 LSB SID113 A_THD Total harmonic distortion – – –65 dB Document Number: 001-93573 Rev. *G Details/Conditions Measured at 1 V FIN = 10 kHz VDD = 1.71 to 5.5, 1 Msps, Vref = 1 to 5.5. –40 °C ≤ TA ≤ 85 °C VDD = 1.71 to 5.5, 1 Msps, Vref = 1 to 5.5. –40 °C ≤ TA ≤ 105 °C VDDD = 1.71 to 3.6, 1 Msps, Vref = 1.71 to VDDD. –40 °C ≤ TA ≤ 85 °C VDDD = 1.71 to 3.6, 1 Msps, Vref = 1.71 to VDDD. –40 °C ≤ TA ≤ 105 °C VDDD = 1.71 to 5.5, 500 Ksps, Vref = 1 to 5.5. VDDD = 1.71 to 5.5, 1 Msps, Vref = 1 to 5.5. –40 °C ≤ TA ≤ 85 °C VDDD = 1.71 to 5.5, 1 Msps, Vref = 1 to 5.5. –40 °C ≤ TA ≤ 105 °C VDDD = 1.71 to 3.6, 1 Msps, Vref = 1.71 to VDDD. –40 °C ≤ TA ≤ 85 °C VDDD = 1.71 to 3.6, 1 Msps, Vref = 1.71 to VDDD. –40 °C ≤ TA ≤ 105 °C VDDD = 1.71 to 5.5, 500 Ksps, Vref = 1 to 5.5. FIN = 10 kHz. Page 21 of 38 Automotive PSoC® 4: PSoC 4200 Family Datasheet CSD Table 15. CSD Block Specification Spec ID# Parameter Description Min Typ Max Units 1.71 – 5.5 V Details/ Conditions CSD Specification SID308 VCSD Voltage range of operation SID309 IDAC1 DNL for 8-bit resolution –1 – 1 LSB SID310 IDAC1 INL for 8-bit resolution –3 – 3 LSB SID311 IDAC2 DNL for 7-bit resolution –1 – 1 LSB SID312 IDAC2 INL for 7-bit resolution –3 – 3 LSB SID313 SNR Ratio of counts of finger to noise. Guaranteed by characterization 5 – – Ratio SID314 IDAC1_CRT1 Output current of Idac1 (8-bits) in High range – 612 – µA SID314A IDAC1_CRT2 Output current of Idac1(8-bits) in Low range – 306 – µA SID315 IDAC2_CRT1 Output current of Idac2 (7-bits) in High range – 304.8 – µA SID315A IDAC2_CRT2 Output current of Idac2 (7-bits) in Low range – 152.4 – µA Document Number: 001-93573 Rev. *G Capacitance range of 9 to 35 pF, 0.1 pF sensitivity Page 22 of 38 Automotive PSoC® 4: PSoC 4200 Family Datasheet Digital Peripherals The following specifications apply to the Timer/Counter/PWM peripherals in the Timer mode. Timer/Counter/PWM Table 16. TCPWM Specifications (Guaranteed by Characterization) Spec ID Parameter Description Min Typ Max Units SID.TCPWM.1 ITCPWM1 Block current consumption at 3 MHz – – 45 µA SID.TCPWM.2 ITCPWM2 Block current consumption at 12 MHz – – 155 µA SID.TCPWM.2A ITCPWM3 Block current consumption at 48 MHz – – 650 µA – – Fc MHz SID.TCPWM.3 TCPWMFREQ Operating frequency SID.TCPWM.4 TPWMENEXT Input Trigger Pulse Width for all Trigger Events 2/Fc – – ns SID.TCPWM.5 TPWMEXT Output Trigger Pulse widths 2/Fc – – ns SID.TCPWM.5A TCRES Resolution of Counter 1/Fc – – ns SID.TCPWM.5B PWMRES PWM Resolution 1/Fc – – ns SID.TCPWM.5C QRES Quadrature inputs resolution 1/Fc – – ns Details/Conditions All modes (Timer/Counter/PWM) All modes (Timer/Counter/PWM) All modes (Timer/Counter/PWM) Fc max = Fcpu. Maximum = 24 MHz Trigger Events can be Stop, Start, Reload, Count, Capture, or Kill depending on which mode of operation is selected. Minimum possible width of Overflow, Underflow, and CC (Counter equals Compare value) trigger outputs Minimum time between successive counts Minimum pulse width of PWM Output Minimum pulse width between Quadrature phase inputs. I2C Table 17. Fixed I2C DC Specifications (Guaranteed by Characterization) Spec ID Parameter Description Min Typ Max Units SID149 II2C1 Block current consumption at 100 kHz – – 50 µA SID150 II2C2 Block current consumption at 400 kHz – – 135 µA SID151 II2C3 Block current consumption at 1 Mbps – – 310 µA II2C4 I2C – – 1.4 µA Min Typ Max Units – – 1 Mbps SID152 enabled in Deep Sleep mode Details/Conditions Table 18. Fixed I2C AC Specifications (Guaranteed by Characterization) Spec ID SID153 Parameter FI2C1 Description Bit rate Document Number: 001-93573 Rev. *G Details/Conditions Page 23 of 38 Automotive PSoC® 4: PSoC 4200 Family Datasheet LCD Direct Drive Table 19. LCD Direct Drive DC Specifications (Guaranteed by Characterization) Spec ID Parameter Description Min Typ Max Units Details/Conditions SID154 ILCDLOW Operating current in low power mode – 5 – µA 16 × 4 small segment disp. at 50 Hz SID155 CLCDCAP LCD capacitance per segment/common driver – 500 5000 pF Guaranteed by Design SID156 LCDOFFSET Long-term segment offset – 20 – mV SID157 ILCDOP1 PWM Mode current. 5-V bias. 24-MHz IMO. 25 °C – 0.6 – mA 32 × 4 segments. 50 Hz SID158 ILCDOP2 PWM Mode current. 3.3-V bias. 24-MHz IMO. 25 °C – 0.5 – mA 32 × 4 segments. 50 Hz Min Typ Max Units 10 50 150 Hz Min Typ Max Units Table 20. LCD Direct Drive AC Specifications (Guaranteed by Characterization) Spec ID SID159 Parameter FLCD Description LCD frame rate Details/Conditions Table 21. Fixed UART DC Specifications (Guaranteed by Characterization) Spec ID Parameter Description SID160 IUART1 Block current consumption at 100 Kbits/sec – – 55 µA SID161 IUART2 Block current consumption at 1000 Kbits/sec – – 312 µA Details/Conditions Table 22. Fixed UART AC Specifications (Guaranteed by Characterization) Spec ID SID162 Parameter FUART Document Number: 001-93573 Rev. *G Description Bit rate Min Typ Max Units – – 1 Mbps Page 24 of 38 Automotive PSoC® 4: PSoC 4200 Family Datasheet SPI Specifications Table 23. Fixed SPI DC Specifications (Guaranteed by Characterization) Spec ID Parameter Description Min Typ Max Units SID163 ISPI1 Block current consumption at 1 Mbits/sec – – 360 µA SID164 ISPI2 Block current consumption at 4 Mbits/sec – – 560 µA SID165 ISPI3 Block current consumption at 8 Mbits/sec – – 600 µA Min Typ Max Units – – 8 MHz Min Typ Max Units Table 24. Fixed SPI AC Specifications (Guaranteed by Characterization) Spec ID SID166 Parameter FSPI Description SPI operating frequency (master; 6X oversampling) Table 25. Fixed SPI Master mode AC Specifications (Guaranteed by Characterization) Spec ID Parameter Description SID167 TDMO MOSI valid after Sclock driving edge – – 15 ns SID168 TDSI MISO valid before Sclock capturing edge. Full clock, late MISO Sampling used 20 – – ns SID169 THMO Previous MOSI data hold time with respect to capturing edge at Slave 0 – – ns Table 26. Fixed SPI Slave mode AC Specifications (Guaranteed by Characterization) Spec ID Parameter Description Min Typ Max Units SID170 TDMI MOSI valid before Sclock capturing edge 40 – – ns SID171 TDSO MISO valid after Sclock driving edge – – 42 + 3 × Tscbclk ns SID171A TDSO_ext MISO valid after Sclock driving edge in Ext. Clock mode – – 48 ns SID172 THSO Previous MISO data hold time 0 – – ns SID172A TSSELSCK SSEL Valid to first SCK Valid edge 100 – – ns Document Number: 001-93573 Rev. *G Details/Conditions Page 25 of 38 Automotive PSoC® 4: PSoC 4200 Family Datasheet Memory Table 27. Flash DC Specifications Spec ID SID173 Parameter VPE Description Min Typ Max Units 1.71 – 5.5 V Description Min Typ Max Units Row (block) write time (erase and program) – – 20 ms Row (block) = 128 bytes. –40 °C  TA  85 °C – – 26 ms Row (block) = 128 bytes. –40 °C  TA  105 °C – – 13 ms – – 7 ms –40 °C  TA  85 °C –40 °C  TA  105 °C Erase and program voltage Details/Conditions Table 28. Flash AC Specifications Spec ID SID174 Parameter TROWWRITE[3] Details/Conditions SID175 TROWERASE[3] SID176 TROWPROGRAM[3] Row program time after erase – – 13 ms SID178 TBULKERASE[3] Bulk erase time (32 KB) – – 35 ms SID180 TDEVPROG[3] Total device program time – – 7 SID181 FEND Flash endurance 100 K – – cycles Guaranteed by characterization SID182 FRET Flash retention. TA  55 °C, 100 K P/E cycles 20 – – years Guaranteed by characterization Flash retention. TA  85 °C, 10 K P/E cycles 10 – – years Guaranteed by characterization Flash retention. TA  105 °C, 10K P/E cycles,  three years at TA > 85 °C. 10 20 – SID182A SID182B FRETQ Row erase time seconds Guaranteed by characterization Guaranteed by characterization. Note 3. It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or Flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated. Document Number: 001-93573 Rev. *G Page 26 of 38 Automotive PSoC® 4: PSoC 4200 Family Datasheet System Resources Power-on-Reset (POR) with Brown Out Table 29. Imprecise Power On Reset (PRES) Min Typ Max Units SID185 Spec ID VRISEIPOR Parameter Rising trip voltage Description 0.80 – 1.45 V Guaranteed by characterization Details/Conditions SID186 VFALLIPOR Falling trip voltage 0.75 – 1.4 V Guaranteed by characterization SID187 VIPORHYST Hysteresis 15 – 200 mV Guaranteed by characterization Table 30. Precise Power On Reset (POR) Min Typ Max Units SID190 Spec ID VFALLPPOR Parameter BOD trip voltage in active and sleep modes Description 1.64 – – V Full functionality between 1.71 V and BOD trip voltage is guaranteed by characterization Details/Conditions SID192 VFALLDPSLP BOD trip voltage in Deep Sleep 1.4 – – V Guaranteed by characterization BID55 Svdd Maximum power supply ramp rate – – 67 kV/sec Min Typ Max Units Voltage Monitors Table 31. Voltage Monitors DC Specifications Spec ID Parameter Description SID195 VLVI1 LVI_A/D_SEL[3:0] = 0000b 1.71 1.75 1.79 V SID196 VLVI2 LVI_A/D_SEL[3:0] = 0001b 1.76 1.80 1.85 V SID197 VLVI3 LVI_A/D_SEL[3:0] = 0010b 1.85 1.90 1.95 V SID198 VLVI4 LVI_A/D_SEL[3:0] = 0011b 1.95 2.00 2.05 V SID199 VLVI5 LVI_A/D_SEL[3:0] = 0100b 2.05 2.10 2.15 V SID200 VLVI6 LVI_A/D_SEL[3:0] = 0101b 2.15 2.20 2.26 V SID201 VLVI7 LVI_A/D_SEL[3:0] = 0110b 2.24 2.30 2.36 V SID202 VLVI8 LVI_A/D_SEL[3:0] = 0111b 2.34 2.40 2.46 V SID203 VLVI9 LVI_A/D_SEL[3:0] = 1000b 2.44 2.50 2.56 V SID204 VLVI10 LVI_A/D_SEL[3:0] = 1001b 2.54 2.60 2.67 V SID205 VLVI11 LVI_A/D_SEL[3:0] = 1010b 2.63 2.70 2.77 V SID206 VLVI12 LVI_A/D_SEL[3:0] = 1011b 2.73 2.80 2.87 V SID207 VLVI13 LVI_A/D_SEL[3:0] = 1100b 2.83 2.90 2.97 V SID208 VLVI14 LVI_A/D_SEL[3:0] = 1101b 2.93 3.00 3.08 V SID209 VLVI15 LVI_A/D_SEL[3:0] = 1110b 3.12 3.20 3.28 V SID210 VLVI16 LVI_A/D_SEL[3:0] = 1111b 4.39 4.50 4.61 V SID211 LVI_IDD Block current – – 100 µA Document Number: 001-93573 Rev. *G Details/Conditions Guaranteed by characterization Page 27 of 38 Automotive PSoC® 4: PSoC 4200 Family Datasheet Table 32. Voltage Monitors AC Specifications Spec ID SID212 Parameter TMONTRIP Description Voltage monitor trip time Min Typ Max Units – – 1 µs Details/Conditions Guaranteed by characterization SWD Interface Table 33. SWD Interface Specifications Min Typ Max Units Details/Conditions SID213 Spec ID F_SWDCLK1 Parameter 3.3 V  VDD  5.5 V Description – – 14 MHz SWDCLK ≤ 1/3 CPU clock frequency SID214 F_SWDCLK2 1.71 V  VDD  3.3 V – – 7 MHz SWDCLK ≤ 1/3 CPU clock frequency SID215 T_SWDI_SETUP T = 1/f SWDCLK 0.25*T – – ns Guaranteed by characterization SID216 T_SWDI_HOLD 0.25*T – – ns Guaranteed by characterization SID217 T_SWDO_VALID T = 1/f SWDCLK – – 0.5*T ns Guaranteed by characterization SID217A T_SWDO_HOLD T = 1/f SWDCLK 1 – – ns Guaranteed by characterization T = 1/f SWDCLK Internal Main Oscillator Table 34. IMO DC Specifications (Guaranteed by Design) Min Typ Max Units SID218 Spec ID IIMO1 Parameter IMO operating current at 48 MHz Description – – 1000 µA SID219 IIMO2 IMO operating current at 24 MHz – – 325 µA SID220 IIMO3 IMO operating current at 12 MHz – – 225 µA SID221 IIMO4 IMO operating current at 6 MHz – – 180 µA SID222 IIMO5 IMO operating current at 3 MHz – – 150 µA Details/Conditions Table 35. IMO AC Specifications Min Typ Max Units Details/Conditions SID223 Spec ID FIMOTOL1 Parameter Frequency variation from 3 to 48 MHz Description – – ±2 % +3% if TA > 85 °C and IMO frequency < 24 MHz SID226 TSTARTIMO IMO startup time – – 12 µs SID227 TJITRMSIMO1 RMS Jitter at 3 MHz – 156 – ps SID228 TJITRMSIMO2 RMS Jitter at 24 MHz – 145 – ps SID229 TJITRMSIMO3 RMS Jitter at 48 MHz – 139 – ps Document Number: 001-93573 Rev. *G Page 28 of 38 Automotive PSoC® 4: PSoC 4200 Family Datasheet Internal Low-Speed Oscillator Table 36. ILO DC Specifications (Guaranteed by Design) Spec ID Parameter Description Min Typ Max Units Details/Conditions SID231 IILO1 ILO operating current at 32 kHz – 0.3 1.05 µA Guaranteed by characterization SID233 IILOLEAK ILO leakage current – 2 15 nA Guaranteed by design Table 37. ILO AC Specifications Min Typ Max Units SID234 Spec ID TSTARTILO1 Parameter ILO startup time Description – – 2 ms Guaranteed by characterization Details/Conditions SID236 TILODUTY ILO duty cycle 40 50 60 % Guaranteed by characterization SID237 FILOTRIM1 32 kHz trimmed frequency 15 32 50 kHz Max. ILO frequency is 70 kHz if TA > 85 °C Table 38. External Clock Specifications Min Typ Max Units SID305 Spec ID ExtClkFreq Parameter External Clock input Frequency Description 0 – 48 MHz Guaranteed by characterization Details/Conditions SID306 ExtClkDuty Duty cycle; Measured at VDD/2 45 – 55 % Guaranteed by characterization Table 39. UDB AC Specifications (Guaranteed by Characterization) Spec ID Parameter Description Min Typ Max Units Details/Conditions Datapath performance SID249 FMAX-TIMER Max frequency of 16-bit timer in a UDB pair – – 48 MHz SID250 FMAX-ADDER Max frequency of 16-bit adder in a UDB pair – – 48 MHz SID251 FMAX_CRC Max frequency of 16-bit CRC/PRS in a UDB pair – – 48 MHz Max frequency of 2-pass PLD function in a UDB pair – – 48 MHz PLD Performance in UDB SID252 FMAX_PLD Clock to Output Performance SID253 TCLK_OUT_UDB1 Prop. delay for clock in to data out at 25 °C, Typ. – 15 – ns SID254 TCLK_OUT_UDB2 Prop. delay for clock in to data out, Worst case. – 25 – ns Document Number: 001-93573 Rev. *G Page 29 of 38 Automotive PSoC® 4: PSoC 4200 Family Datasheet Table 40. Block Specs Min Typ Max SID256* Spec ID TWS48* Parameter Number of wait states at 48 MHz Description 1 – – Units CPU execution from Flash. Guaranteed by characterization SID257 TWS24* Number of wait states at 24 MHz 0 – – CPU execution from Flash. Guaranteed by characterization SID260 VREFSAR Trimmed internal reference to SAR –1 – +1 SID262 TCLKSWITCH Clock switching from clk1 to clk2 in clk1 periods 3 – 4 % Details/Conditions Percentage of Vbg (1.024 V). Guaranteed by characterization Periods Guaranteed by design * Tws48 and Tws24 are guaranteed by Design Table 41. UDB Port Adaptor Specifications (Based on LPC Component Specs, Guaranteed by Characterization -10-pF load, 3-V VDDIO and VDDD) Min Typ Max SID263 Spec ID TLCLKDO Parameter LCLK to output delay Description – – 18 ns SID264 TDINLCLK Input setup time to LCLCK rising edge – – 7 ns SID265 TDINLCLKHLD Input hold time from LCLK rising edge 5 – – ns SID266 TLCLKHIZ LCLK to output tristated – – 28 ns SID267 TFLCLK LCLK frequency – – 33 MHz SID268 TLCLKDUTY LCLK duty cycle (percentage high) 40 – 60 % Document Number: 001-93573 Rev. *G Units Details/Conditions Page 30 of 38 Automotive PSoC® 4: PSoC 4200 Family Datasheet Ordering Information The PSoC 4200 part numbers and features are listed in the following table. Table 42. PSoC 4200 Family Ordering Information Flash (KB) SRAM (KB) UDB Opamp (CTBm) CapSense Direct LCD Drive 12-bit SAR ADC LP Comparators TCPWM Blocks SCB Blocks GPIO 28-SSOP –40 to +85 °C (A grade) –40 to +105 °C (S grade) Operating Temperature CY8C4244PVA-442Z 48 16 4 2 1 ✔ ✔ 1 Msps 2 4 2 24 ✔ ✔ – CY8C4245PVA-452Z 48 32 4 4 0 – ✔ – 0 4 2 24 ✔ ✔ – CY8C4245PVA-472Z 48 32 4 4 1 – ✔ 1 Msps 2 4 2 24 ✔ ✔ – Family 4200 Package Max CPU Speed (MHz) Features MPN CY8C4245PVA-482Z 48 32 4 4 1 ✔ ✔ 1 Msps 2 4 2 24 ✔ ✔ – CY8C4244PVS-442Z 48 16 4 2 1 ✔ ✔ 1 Msps 2 4 2 24 ✔ – ✔ CY8C4245PVS-452Z 48 32 4 4 0 – ✔ – 0 4 2 24 ✔ – ✔ CY8C4245PVS-472Z 48 32 4 4 1 – ✔ 1 Msps 2 4 2 24 ✔ – ✔ CY8C4245PVS-482Z 32 4 4 1 ✔ ✔ 1 Msps 2 4 2 24 ✔ – ✔ 48 Part Numbering Conventions PSoC 4 devices follow the part numbering convention described in the following table. All fields are single-character alphanumeric (0, 1, 2, …, 9, A,B, …, Z) unless stated otherwise. The part numbers are of the form CY8C4ABCDEF-GHI where the fields are defined as follows. Example CY8C 4 A B C DE F - GH I Z Cypress Prefix 4 : PSoC4 2 : 4200Family 4 : 48 MHz Architecture Family within Architecture Speed Grade 5 : 32 KB Flash Capacity PV : SSOP Package Code A: Automotive -40 to +85 °C S: Automotive: -40 to +105 °C Temperature Range Attributes Set Fab Location Change: Z Document Number: 001-93573 Rev. *G Page 31 of 38 Automotive PSoC® 4: PSoC 4200 Family Datasheet The field values are listed in the following table. Table 43. Field Values Field Description CY8C Values Meaning Cypress prefix 4 Architecture 4 PSoC 4 A Family within architecture 1 4100 Family 2 4200 Family B CPU speed 2 24 MHz 4 48 MHz C Flash capacity 4 16 KB 5 32 KB DE Package code PV SSOP A/S Automotive F Temperature range GHI Attributes code Z 000-999 Code of feature set in specific family Fab location change Packaging Table 44. Package Characteristics Parameter Description Conditions Min Typ Max Units –40 25.00 85 °C For S grade devices –40 25.00 105 °C For A grade devices –40 – 100 °C For S grade devices –40 – 120 °C – 66.58 – °C/W – 46.28 – °C/W TA Operating ambient temperature For A grade devices TA Operating ambient temperature TJ Operating junction temperature TJ Operating junction temperature TJA Package JA (28-pin SSOP) TJC Package JC (28-pin SSOP) Table 45. Solder Reflow Peak Temperature Package Maximum Peak Temperature Maximum Time at Peak Temperature 28-pin SSOP 260 °C 30 seconds Table 46. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2 Package MSL 28-pin SSOP MSL 3 PSoC4 CAB Libraries with Schematics Symbols and PCB Footprints are on the http://www.cypress.com/cad-resources/psoc-4-cad-libraries?source=search&cat=technical_documents Document Number: 001-93573 Rev. *G Cypress web site at Page 32 of 38 Automotive PSoC® 4: PSoC 4200 Family Datasheet Figure 8. 28-pin SSOP (210 Mils) Package Outline, 51-85079 51-85079 *F Document Number: 001-93573 Rev. *G Page 33 of 38 Automotive PSoC® 4: PSoC 4200 Family Datasheet Acronyms Table 47. Acronyms Used in this Document (continued) Acronym Table 47. Acronyms Used in this Document Acronym Description abus analog local bus ADC analog-to-digital converter AG analog global AHB AMBA (advanced microcontroller bus architecture) high-performance bus, an Arm data transfer bus ALU arithmetic logic unit Description ETM embedded trace macrocell FIR finite impulse response, see also IIR FPB flash patch and breakpoint FS full-speed GPIO general-purpose input/output, applies to a PSoC pin HVI high-voltage interrupt, see also LVI, LVD IC integrated circuit AMUXBUS analog multiplexer bus IDAC current DAC, see also DAC, VDAC API application programming interface IDE integrated development environment APSR application program status register 2C, Arm® advanced RISC machine, a CPU architecture ATM automatic thump mode BW bandwidth CAN Controller Area Network, a communications protocol CMRR I or IIC IIR Inter-Integrated Circuit, a communications protocol infinite impulse response, see also FIR ILO internal low-speed oscillator, see also IMO IMO internal main oscillator, see also ILO INL integral nonlinearity, see also DNL common-mode rejection ratio I/O input/output, see also GPIO, DIO, SIO, USBIO CPU central processing unit IPOR initial power-on reset CRC cyclic redundancy check, an error-checking protocol IPSR interrupt program status register DAC digital-to-analog converter, see also IDAC, VDAC IRQ interrupt request DFB digital filter block ITM instrumentation trace macrocell DIO digital input/output, GPIO with only digital capabilities, no analog. See GPIO. DMIPS Dhrystone million instructions per second DMA direct memory access, see also TD DNL differential nonlinearity, see also INL DNU do not use DR port write data registers DSI digital system interconnect DWT data watchpoint and trace ECC error correcting code ECO external crystal oscillator EEPROM electrically erasable programmable read-only memory EMI electromagnetic interference EMIF external memory interface EOC end of conversion EOF end of frame EPSR execution program status register ESD electrostatic discharge Document Number: 001-93573 Rev. *G LCD liquid crystal display LIN Local Interconnect Network, a communications protocol. LR link register LUT lookup table LVD low-voltage detect, see also LVI LVI low-voltage interrupt, see also HVI LVTTL low-voltage transistor-transistor logic MAC multiply-accumulate MCU microcontroller unit MISO master-in slave-out NC no connect NMI nonmaskable interrupt NRZ non-return-to-zero NVIC nested vectored interrupt controller NVL nonvolatile latch, see also WOL opamp operational amplifier PAL programmable array logic, see also PLD PC program counter PCB printed circuit board Page 34 of 38 Automotive PSoC® 4: PSoC 4200 Family Datasheet Table 47. Acronyms Used in this Document (continued) Acronym Description Table 47. Acronyms Used in this Document (continued) Acronym Description PGA programmable gain amplifier THD total harmonic distortion PHUB peripheral hub TIA transimpedance amplifier PHY physical layer TRM technical reference manual PICU port interrupt control unit TTL transistor-transistor logic PLA programmable logic array TX transmit PLD programmable logic device, see also PAL UART PLL phase-locked loop Universal Asynchronous Transmitter Receiver, a communications protocol PMDD package material declaration data sheet UDB universal digital block POR power-on reset USB Universal Serial Bus PRES precise power-on reset USBIO PRS pseudo random sequence USB input/output, PSoC pins used to connect to a USB port PS port read data register VDAC voltage DAC, see also DAC, IDAC PSoC® Programmable System-on-Chip™ WDT watchdog timer PSRR power supply rejection ratio WOL write once latch, see also NVL PWM pulse-width modulator WRES watchdog timer reset RAM random-access memory XRES external reset I/O pin RISC reduced-instruction-set computing XTAL crystal RMS root-mean-square RTC real-time clock RTL register transfer language RTR remote transmission request RX receive SAR successive approximation register SC/CT switched capacitor/continuous time SCL I2C serial clock SDA I2C serial data S/H sample and hold SINAD signal to noise and distortion ratio SIO special input/output, GPIO with advanced features. See GPIO. SOC start of conversion SOF start of frame SPI Serial Peripheral Interface, a communications protocol SR slew rate SRAM static random access memory SRES software reset SWD serial wire debug, a test protocol SWV single-wire viewer TD transaction descriptor, see also DMA Document Number: 001-93573 Rev. *G Page 35 of 38 Automotive PSoC® 4: PSoC 4200 Family Datasheet Document Conventions Units of Measure Table 48. Units of Measure Symbol Unit of Measure °C degrees Celsius dB decibel fF femtofarad Hz hertz KB 1024 bytes kbps kilobits per second Khr kilohour kHz kilohertz k kilo ohm ksps kilosamples per second LSB least significant bit Mbps megabits per second MHz megahertz M mega-ohm Msps megasamples per second µA microampere µF microfarad µH microhenry µs microsecond µV microvolt µW microwatt mA milliampere ms millisecond mV millivolt nA nanoampere ns nanosecond nV nanovolt  ohm pF picofarad ppm parts per million ps picosecond s second sps samples per second sqrtHz square root of hertz V volt Document Number: 001-93573 Rev. *G Page 36 of 38 Automotive PSoC® 4: PSoC 4200 Family Datasheet Document History Page Document Title: Automotive PSoC® 4: PSoC 4200 Family Datasheet Programmable System-on-Chip (PSoC®) Document Number: 001-93573 Revision ECN Orig. of Change Submission Date *D 5325598 MVRE 07/04/2016 Changed status from Preliminary to Final. *E 5675099 SNPR 03/28/2017 Updated Ordering Information: Updated part numbers. Updated to new template. *F 5754059 SNPR 05/29/2017 No technical updates. Completing Sunset Review. *G 6504548 SNPR 03/08/2019 Added CY84245PVA-472Z and CY84245PVS-472Z in Ordering Information. Document Number: 001-93573 Rev. *G Description of Change Page 37 of 38 Automotive PSoC® 4: PSoC 4200 Family Datasheet Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i) Cypress's published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 001-93573 Rev. *G Revised March 8, 2019 Page 38 of 38
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