CY9AF1A2MPMC1-G-SNE2

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Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CY9A1A0N Series 32-bit Arm® Cortex®-M3 FM3 Microcontroller The CY9A1A0N Series are highly integrated 32-bit microcontrollers that dedicated for embedded controllers with low-power consumption mode and competitive cost. The CY9A1A0N Series are based on the Arm® Cortex® -M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions such as Motor Control Timers, ADCs, DACs and Communication Interfaces (UART, CSIO, I2C). The products which are described in this data sheet are placed into TYPE7 product categories in FM3 Family Peripheral Manual. Features 32-bit Arm® Cortex®-M3 Core [CSIO]  Processor version: r2p1  Full duplex double buffer  Up to 20 MHz Operation Frequency  Built-in dedicated baud rate generator  Integrated Nested Vectored Interrupt Controller (NVIC): 1  Overrun error detection function available channel NMI (non-maskable interrupt) and 32 channels' peripheral interrupts and 8 priority levels [I2C]  24-bit System timer (Sys Tick): System timer for OS task Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported On-chip Memories A/D Converter (Max 16 channels) [Flash memory] [12-bit A/D Converter]  Up to 128 Kbytes  Successive Approximation type  Read cycle: 0 wait-cycle  Conversion time: Min 1.0 μs  Security function for code protection  Priority conversion available (priority at 2levels) management  Scanning conversion mode [SRAM] This series contains a total of up to 16 Kbyte on-chip SRAM that is connected to System bus of Cortex-M3 core.  Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion: 4steps)  SRAM1: Up to 16 Kbytes D/A Converter (Max 2 channels) Multi-function Serial Interface (Max 8 channels)  R-2R type Operation mode is selectable from the followings for each channel.  10-bit resolution  UART Base Timer (Max 8 channels)  CSIO Operation mode is selectable from the followings for each channel.  I2 C  16-bit PWM timer [UART]  16-bit PPG timer  Full duplex double buffer  16-/32-bit reload timer  Selection with or without parity supported  16-/32-bit PWC timer  Built-in dedicated baud rate generator  External clock available as a serial clock  Various error detection functions available (parity errors, framing errors, and overrun errors) Cypress Semiconductor Corporation Document Number: 002-05675 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 17, 2019 CY9A1A0N Series General-Purpose I/O Port This series can use its pins as general-purpose I/O ports when they are not used for peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated to.  Capable of pull-up control per pin  Capable of reading pin level directly  Built-in the port relocate function HDMI-CEC transmitter  Header block automatic transmission by judging Signal free  Generating status interrupt by detecting Arbitration lost  Generating START, EOM, ACK automatically to output CEC transmission by setting 1 byte data  Generating transmission status interrupt when transmitting 1 block (1 byte data and EOM/ACK)  Up to 84 high-speed general-purpose I/O Ports@100 pin Real-time clock (RTC)  Some ports are 5 V tolerant I/O The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 00 to 99. Package See List of Pin Functions and I/O Circuit Type to confirm the corresponding pins. Multi-function Timer The Multi-function timer is composed of the following blocks.  The interrupt function with specifying date and time (Year/Month/Day/Hour/Minute) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute.  16-bit free-run timer × 3ch.  Timer interrupt function after set time or each set time.  Input capture × 4ch.  Capable of rewriting the time with continuing the time count.  Output compare × 6ch.  Leap year automatic count is available.  A/D activation compare × 1ch.  Waveform generator × 3ch.  16-bit PPG timer × 3ch. IGBT mode is contained The following function can be used to achieve the motor control.  PWM signal output function  DC chopper waveform output function External Interrupt Controller Unit  Up to 16 external interrupt input pins  Include one non-maskable interrupt (NMI) input pin Watchdog Timer (2 channels) A watchdog timer can generate interrupts or a reset when a time-out value is reached. This series consists of two different watchdogs, a Hardware watchdog and a Software watchdog.  A/D convertor activate function The Hardware watchdog timer is clocked by the built-in Low-speed CR oscillator. Therefore, the Hardware watchdog is active in any low-power consumption mode except RTC, Stop, Deep Standby RTC and Deep Standby Stop modes.  DTIF (Motor emergency stop) interrupt function Clock and Reset HDMI-CEC/Remote Control Receiver (Up to 2 channels) [Clocks]  Dead time function  Input capture function HDMI- CEC receiver / Remote control receiver  Operating modes supporting the following standards can be selected  SIRCS  NEC/Association for Electric Home Appliances  HDMI-CEC  Capable of adjusting detection timings for start bit and data Selectable from five clock sources (2 external oscillators, 2 built-in CR oscillators, and Main PLL).  Main Clock: 4 MHz to 20 MHz  Sub Clock: 32.768 kHz  Built-in High-speed CR Clock: 4 MHz  Built-in Low-speed CR Clock: 100 kHz  Main PLL Clock bit  Equipped with noise filter Document Number: 002-05675 Rev. *E Page 2 of 99 CY9A1A0N Series [Resets]  Reset requests from INITX pin  Power-on reset  Software reset  Watchdog timers reset  Low-voltage detection reset  Clock Super Visor reset Low-Power Consumption Mode Six low-power consumption modes supported.  Sleep  Timer  RTC  Stop  Deep Standby RTC  Deep Standby Stop Clock Super Visor (CSV) The back up register is 16 bytes. Clocks generated by built-in CR oscillators are used to supervise abnormality of the external clocks. Debug  If external clock failure (clock stop) is detected, reset is asserted.  If external frequency anomaly is detected, interrupt or reset is asserted. Serial Wire JTAG Debug Port (SWJ-DP) Power Supply Wide range voltage: VCC = 1.8 V to 5.5 V Low-Voltage Detector (LVD) This Series includes 2-stage monitoring of voltage on the VCC. When the voltage falls below the voltage that has been set, Low-Voltage Detector generates an interrupt or reset.  LVD1: error reporting via interrupt  LVD2: auto-reset operation Document Number: 002-05675 Rev. *E Page 3 of 99 CY9A1A0N Series Contents 1. Product Lineup .................................................................................................................................................................. 6 2. Packages ........................................................................................................................................................................... 7 3. Pin Assignment ................................................................................................................................................................. 8 4. List of Pin Functions....................................................................................................................................................... 12 5. I/O Circuit Type ............................................................................................................................................................... 31 6. Handling Precautions ..................................................................................................................................................... 35 6.1 Precautions for Product Design ................................................................................................................................... 35 6.2 Precautions for Package Mounting .............................................................................................................................. 36 6.3 Precautions for Use Environment ................................................................................................................................ 37 7. Handling Devices ............................................................................................................................................................ 38 8. Block Diagram ................................................................................................................................................................. 40 9. Memory Size .................................................................................................................................................................... 41 10. Memory Map .................................................................................................................................................................... 41 11. Pin Status in Each CPU State ........................................................................................................................................ 44 12. Electrical Characteristics ............................................................................................................................................... 52 12.1 Absolute Maximum Ratings ......................................................................................................................................... 52 12.2 Recommended Operating Conditions ......................................................................................................................... 53 12.3 DC Characteristics ...................................................................................................................................................... 54 12.3.1 Current Rating .............................................................................................................................................................. 54 12.3.2 Pin Characteristics ....................................................................................................................................................... 57 12.4 AC Characteristics ....................................................................................................................................................... 58 12.4.1 Main Clock Input Characteristics .................................................................................................................................. 58 12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 59 12.4.3 Built-in CR Oscillation Characteristics .......................................................................................................................... 59 12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input of PLL) .................................................. 60 12.4.5 Operating Conditions of Main PLL (In the case of using the built-in High-speed CR for the input clock of the Main PLL) ............................................................................................................................................................................. 60 12.4.6 Reset Input Characteristics .......................................................................................................................................... 61 12.4.7 Power-on Reset Timing ................................................................................................................................................ 61 12.4.8 Base Timer Input Timing .............................................................................................................................................. 62 12.4.9 CSIO/UART Timing ...................................................................................................................................................... 64 12.4.10 External Input Timing ................................................................................................................................................ 72 12.4.11 I2C Timing ................................................................................................................................................................. 73 12.4.12 JTAG Timing............................................................................................................................................................. 74 12.5 12-bit A/D Converter .................................................................................................................................................... 75 12.6 10-bit D/A Converter .................................................................................................................................................... 78 12.7 Low-Voltage Detection Characteristics ........................................................................................................................ 79 12.7.1 Low-Voltage Detection Reset ....................................................................................................................................... 79 12.7.2 Interrupt of Low-Voltage Detection ............................................................................................................................... 80 12.8 Flash Memory Write/Erase Characteristics ................................................................................................................. 82 12.8.1 Write / Erase time......................................................................................................................................................... 82 12.8.2 Write cycles and data hold time ................................................................................................................................... 82 12.9 Return Time from Low-Power Consumption Mode ...................................................................................................... 83 12.9.1 Return Factor: Interrupt/WKUP .................................................................................................................................... 83 12.9.2 Return Factor: Reset .................................................................................................................................................... 85 13. Ordering Information ...................................................................................................................................................... 87 14. Package Dimensions ...................................................................................................................................................... 88 Document Number: 002-05675 Rev. *E Page 4 of 99 CY9A1A0N Series 15. Errata................................................................................................................................................................................ 94 15.1 Part Numbers Affected ................................................................................................................................................ 94 15.2 Qualification Status ..................................................................................................................................................... 94 15.3 Errata Summary .......................................................................................................................................................... 94 15.4 Errata Detail ................................................................................................................................................................ 94 15.4.1 HDMI-CEC polling message issue ............................................................................................................................... 94 15.4.2 RTC delay issue ........................................................................................................................................................... 95 Major Changes ...................................................................................................................................................................... 96 Document History ................................................................................................................................................................. 98 Sales, Solutions, and Legal Information ............................................................................................................................. 99 Document Number: 002-05675 Rev. *E Page 5 of 99 CY9A1A0N Series 1. Product Lineup Memory size Product name On-chip Flash memory On-chip SRAM SRAM1 CY9AF1A1L/M/N 64 Kbytes 12 Kbytes CY9AF1A2L/M/N 128 Kbytes 16 Kbytes Function Product name Pin count CY9AF1A1L CY9AF1A2L 64 CPU Freq. Power supply voltage range Multi-function Serial Interface (UART/CSIO/I2C) Base Timer (PWC/ Reload timer/PWM/PPG) A/D activation 1ch. compare Input capture 4ch. Free-run timer 3ch. MFOutput 6ch. Timer compare Waveform 3ch. generator PPG 3ch. (IGBT mode) HDMI-CEC/ Remote Control Receiver Real-time clock (RTC) Watchdog timer External Interrupts General-purpose I/O ports 12-bit A/D converter 10-bit D/A converter CSV (Clock Super Visor) LVD (Low-Voltage Detector) High-speed Built-in CR Low-speed Debug Function CY9AF1A1M CY9AF1A2M 80 Cortex-M3 20 MHz 1.8 V to 5.5 V CY9AF1A1N CY9AF1A2N 100 8ch. (Max) 8ch. (Max) 1 unit (Max) 2ch. (Max) 8 pins (Max)+ NMI × 1 52 pins (Max) 9ch. (1 unit) 1 unit 1ch. (SW) + 1ch. (HW) 11 pins (Max)+ NMI × 1 67 pins (Max) 12ch. (1 unit) 2ch. (Max) Yes 2ch. 4 MHz 100 kHz SWJ-DP 16 pins (Max)+ NMI × 1 84 pins (Max) 16ch. (1 unit) Note: − All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the I/O port according to your function use. See Electrical Characteristics 12.4 AC Characteristics 12.4.3 Built-in CR Oscillation Characteristics for accuracy of built-in CR. Document Number: 002-05675 Rev. *E Page 6 of 99 CY9A1A0N Series 2. Packages Product name Package CY9AF1A1L CY9AF1A2L CY9AF1A1M CY9AF1A2M CY9AF1A1N CY9AF1A2N LQD064 (0.5mm pitch)  LQFP: LQG064 (0.65mm pitch)  LQFP: LQH080 (0.5mm pitch) -  LQFP: LQJ080 (0.65mm pitch) -  - LQFP: LQI100 (0.5mm pitch) - -  QFP: PQH100 (0.65mm pitch) - -  LQFP: - - - - : Supported Note: − See Package Dimensions for detailed information on each package. Document Number: 002-05675 Rev. *E Page 7 of 99 CY9A1A0N Series 3. Pin Assignment LQD064/LQG064 P03 / TMS / SWDIO P02 / TDI P01 / TCK / SWCLK P00 / TRSTX 52 51 50 49 P0A / SIN4_0 / INT00_2 P04 / TDO / SWO 54 53 P0C / SCK4_0 / TIOA6_1 P0B / SOT4_0 / TIOB6_1 56 55 P62 / SCK5_0 / ADTG_3 P0F / NMIX / CROUT_1 / RTCCO_0 / SUBOUT_0 / WKUP0 58 57 P60 / SIN5_0 / TIOA2_2 / INT15_1 / WKUP3 / CEC1 P61 / SOT5_0 / TIOB2_2 / DTTI0X_2 60 59 P81 / SOT7_2 P80 / SIN7_2 62 61 VSS P82 / SCK7_2 64 63 (TOP VIEW) VCC 1 48 P21 / SIN0_0 / INT06_1 / WKUP2 P50 / SIN3_1 / INT00_0 2 47 P22 / SOT0_0 / TIOB7_1 P51 / SOT3_1 / INT01_0 3 46 P23 / SCK0_0 / TIOA7_1 P52 / SCK3_1 / INT02_0 4 45 P19 / AN09 / SCK2_2 P30 / TIOB0_1 / INT03_2 5 44 P18 / AN08 / SOT2_2 P31 / SCK6_1 / TIOB1_1 / INT04_2 6 43 AVSS P32 / SOT6_1 / TIOB2_1 / INT05_2 7 42 AVRH P33 / SIN6_1 / TIOB3_1 / INT04_0 / ADTG_6 8 41 AVCC P39 / DTTI0X_0 / ADTG_2 9 40 P17 / AN07 / SIN2_2 / INT04_1 P3A / TIOA0_1 / RTO00_0 / RTCCO_2 / SUBOUT_2 10 39 P15 / AN05 / IC03_2 P3B / TIOA1_1 / RTO01_0 11 38 P14 / AN04 / INT03_1 / IC02_2 P3C / TIOA2_1 / RTO02_0 12 37 P13 / AN03 / SCK1_1 / IC01_2 / RTCCO_1 / SUBOUT_1 P3D / TIOA3_1 / RTO03_0 13 36 P12 / AN02 / SOT1_1 / IC00_2 P3E / TIOA4_1 / RTO04_0 14 35 P11 / AN01 / SIN1_1 / INT02_1 / FRCK0_2 / WKUP1 P3F / TIOA5_1 / RTO05_0 15 34 P10 / AN00 VSS 16 33 VCC 29 30 31 32 MD0 PE2 / X0 PE3 / X1 VSS 27 28 PE0 / MD1 P4D / SOT7_1 / TIOB4_0 / DA0 P4E / SIN7_1 / TIOB5_0 / INT06_2 / DA1 25 26 P4C / SCK7_1 / TIOB3_0 / CEC0 23 24 P4A / TIOB1_0 P4B / TIOB2_0 / IGTRG 21 22 INITX 19 20 P46 / X0A P47 / X1A P49 / TIOB0_0 17 18 C VCC LQFP - 64 Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-05675 Rev. *E Page 8 of 99 CY9A1A0N Series LQH080/LQJ080 P02 / TDI P01 / TCK / SWCLK P00 / TRSTX 63 62 61 P07 / ADTG_0 P04 / TDO / SWO P03 / TMS / SWDIO 66 65 64 P0B / SOT4_0 / TIOB6_1 P0A / SIN4_0 / INT00_2 68 67 P0D / RTS4_0 / TIOA3_2 P0C / SCK4_0 / TIOA6_1 70 69 P63 / INT03_0 P0F / NMIX / CROUT_1 / RTCCO_0 / SUBOUT_0 / WKUP0 P0E / CTS4_0 / TIOB3_2 73 72 71 P61 / SOT5_0 / TIOB2_2 / DTTI0X_2 P62 / SCK5_0 / ADTG_3 75 74 P81 / SOT7_2 P80 / SIN7_2 P60 / SIN5_0 / TIOA2_2 / INT15_1 / WKUP3 / CEC1 78 77 76 VSS P82 / SCK7_2 80 79 (TOP VIEW) VCC 1 60 P20 / INT05_0 / CROUT_0 P50 / SIN3_1 / INT00_0 2 59 P21 / SIN0_0 / INT06_1 / WKUP2 P51 / SOT3_1 / INT01_0 3 58 P22 / SOT0_0 / TIOB7_1 P52 / SCK3_1 / INT02_0 4 57 P23 / SCK0_0 / TIOA7_1 P53 / SIN6_0 / TIOA1_2 / INT07_2 5 56 P1B / AN11 / SOT4_1 / IC01_1 P54 / SOT6_0 / TIOB1_2 6 55 P1A / AN10 / SIN4_1 / INT05_1 / IC00_1 P55 / SCK6_0 / ADTG_1 7 54 P19 / AN09 / SCK2_2 P56 / INT08_2 8 53 P18 / AN08 / SOT2_2 P30 / TIOB0_1 / INT03_2 9 52 AVSS P31 / SCK6_1 / TIOB1_1 / INT04_2 10 51 AVRH P32 / SOT6_1 / TIOB2_1 / INT05_2 11 50 AVCC P33 / SIN6_1 / TIOB3_1 / INT04_0 / ADTG_6 12 49 P17 / AN07 / SIN2_2 / INT04_1 P39 / DTTI0X_0 / ADTG_2 13 48 P16 / AN06 / SCK0_1 P3A / TIOA0_1 / RTO00_0 / RTCCO_2 / SUBOUT_2 14 47 P15 / AN05 / SOT0_1 / IC03_2 P3B / TIOA1_1 / RTO01_0 15 46 P14 / AN04 / SIN0_1 / INT03_1 / IC02_2 P3C / TIOA2_1 / RTO02_0 16 45 P13 / AN03 / SCK1_1 / IC01_2 / RTCCO_1 / SUBOUT_1 P3D / TIOA3_1 / RTO03_0 17 44 P12 / AN02 / SOT1_1 / IC00_2 P3E / TIOA4_1 / RTO04_0 18 43 P11 / AN01 / SIN1_1 / INT02_1 / FRCK0_2 / WKUP1 P3F / TIOA5_1 / RTO05_0 19 42 P10 / AN00 VSS 20 41 VCC 38 39 40 VSS MD0 PE2 / X0 PE0 / MD1 PE3 / X1 35 36 37 P4E / SIN7_1 / TIOB5_0 / INT06_2 / DA1 33 34 P4D / SOT7_1 / TIOB4_0 / DA0 P4B / TIOB2_0 / IGTRG P4C / SCK7_1 / TIOB3_0 / CEC0 31 32 P4A / SCK3_2 / TIOB1_0 28 29 30 INITX P48 / SIN3_2 / INT14_1 P49 / SOT3_2 / TIOB0_0 26 27 P46 / X0A P47 / X1A 23 24 25 C VSS VCC 21 22 P44 / TIOA4_0 P45 / TIOA5_0 LQFP - 80 Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-05675 Rev. *E Page 9 of 99 CY9A1A0N Series LQI100 P82 / SCK7_2 P81 / SOT7_2 P80 / SIN7_2 P60 / SIN5_0 / TIOA2_2 / INT15_1 / WKUP3 / CEC1 P61 / SOT5_0 / TIOB2_2 / DTTI0X_2 P62 / SCK5_0 / ADTG_3 P63 / INT03_0 P0F / NMIX / CROUT_1 / RTCCO_0 / SUBOUT_0 / WKUP0 P0E / CTS4_0 / TIOB3_2 P0D / RTS4_0 / TIOA3_2 P0C / SCK4_0 / TIOA6_1 P0B / SOT4_0 / TIOB6_1 P0A / SIN4_0 / INT00_2 P09 / RTS4_2 / TIOB0_2 P08 / CTS4_2 / TIOA0_2 P07 / SCK4_2 / ADTG_0 P06 / SOT4_2 / TIOB5_2 / INT01_1 P05 / SIN4_2 / TIOA5_2 / INT00_1 P04 / TDO / SWO P03 / TMS / SWDIO P02 / TDI P01 / TCK / SWCLK P00 / TRSTX VCC 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 100 VSS (TOP VIEW) VCC 1 75 VSS P50 / SIN3_1 / INT00_0 2 74 P20 / INT05_0 / CROUT_0 P51 / SOT3_1 / INT01_0 3 73 P21 / SIN0_0 / INT06_1 / WKUP2 P52 / SCK3_1 / INT02_0 4 72 P22 / SOT0_0 / TIOB7_1 P53 / SIN6_0 / TIOA1_2 / INT07_2 5 71 P23 / SCK0_0 / TIOA7_1 / RTO00_1 P54 / SOT6_0 / TIOB1_2 6 70 P1F / AN15 / FRCK0_1 / ADTG_5 P55 / SCK6_0 / ADTG_1 7 69 P1E / AN14 / RTS4_1 / DTTI0X_1 P56 / INT08_2 8 68 P1D / AN13 / CTS4_1 / IC03_1 P30 / TIOB0_1 / INT03_2 9 67 P1C / AN12 / SCK4_1 / IC02_1 P31 / SCK6_1 / TIOB1_1 / INT04_2 10 66 P1B / AN11 / SOT4_1 / IC01_1 P32 / SOT6_1 / TIOB2_1 / INT05_2 11 65 P1A / AN10 / SIN4_1 / INT05_1 / IC00_1 P33 / SIN6_1 / TIOB3_1 / INT04_0 / ADTG_6 12 64 P19 / AN09 / SCK2_2 P34 / TIOB4_1 / FRCK0_0 13 63 P18 / AN08 / SOT2_2 P35 / TIOB5_1 / INT08_1 / IC03_0 14 62 AVSS LQFP - 100 P36 / SIN5_2 / INT09_1 / IC02_0 15 61 AVRH P37 / SOT5_2 / INT10_1 / IC01_0 16 60 AVCC P38 / SCK5_2 / INT11_1 / IC00_0 17 59 P17 / AN07 / SIN2_2 / INT04_1 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P46 / X0A P47 / X1A INITX P48 / SIN3_2 / INT14_1 P49 / SOT3_2 / TIOB0_0 P4A / SCK3_2 / TIOB1_0 P4B / TIOB2_0 / IGTRG P4C / SCK7_1 / TIOB3_0 / CEC0 P4D / SOT7_1 / TIOB4_0 / DA0 P4E / SIN7_1 / TIOB5_0 / INT06_2 / DA1 PE0 / MD1 MD0 PE2 / X0 PE3 / X1 VSS VCC 35 51 VCC 25 34 P10 / AN00 VSS 33 52 C 24 VSS P11 / AN01 / SIN1_1 / INT02_1 / FRCK0_2 / WKUP1 P3F / TIOA5_1 / RTO05_0 32 P12 / AN02 / SOT1_1 / IC00_2 53 P45 / TIOA5_0 54 23 31 22 P3E / TIOA4_1 / RTO04_0 P44 / TIOA4_0 P13 / AN03 / SCK1_1 / IC01_2 / RTCCO_1 / SUBOUT_1 P3D / TIOA3_1 / RTO03_0 30 55 29 21 P42 / TIOA2_0 P14 / AN04 / SIN0_1 / INT03_1 / IC02_2 P3C / TIOA2_1 / RTO02_0 P43 / TIOA3_0 / ADTG_7 56 28 20 P41 / TIOA1_0 / INT13_1 P15 / AN05 / SOT0_1 / IC03_2 P3B / TIOA1_1 / RTO01_0 27 P16 / AN06 / SCK0_1 57 26 58 19 VCC 18 P40 / TIOA0_0 / INT12_1 P39 / DTTI0X_0 / ADTG_2 P3A / TIOA0_1 / RTO00_0 / RTCCO_2 / SUBOUT_2 Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-05675 Rev. *E Page 10 of 99 CY9A1A0N Series PQH100 VSS P20 / INT05_0 / CROUT_0 P21 / SIN0_0 / INT06_1 / WKUP2 53 52 51 P01 / TCK / SWCLK P00 / TRSTX VCC 56 55 54 P04 / TDO / SWO P03 / TMS / SWDIO P02 / TDI 59 58 57 P06 / SOT4_2 / TIOB5_2 / INT01_1 P05 / SIN4_2 / TIOA5_2 / INT00_1 61 60 P09 / RTS4_2 / TIOB0_2 P08 / CTS4_2 / TIOA0_2 P07 / SCK4_2 / ADTG_0 64 63 62 P0B / SOT4_0 / TIOB6_1 P0A / SIN4_0 / INT00_2 66 65 P0E / CTS4_0 / TIOB3_2 P0D / RTS4_0 / TIOA3_2 P0C / SCK4_0 / TIOA6_1 69 68 67 P62 / SCK5_0 / ADTG_3 P63 / INT03_0 P0F / NMIX / CROUT_1 / RTCCO_0 / SUBOUT_0 / WKUP0 72 71 70 P80 / SIN7_2 P60 / SIN5_0 / TIOA2_2 / INT15_1 / WKUP3 / CEC1 P61 / SOT5_0 / TIOB2_2 / DTTI0X_2 75 74 73 VSS P82 / SCK7_2 P81 / SOT7_2 78 77 76 P50 / SIN3_1 / INT00_0 VCC 80 79 (TOP VIEW) P51 / SOT3_1 / INT01_0 81 50 P22 / SOT0_0 / TIOB7_1 P52 / SCK3_1 / INT02_0 82 49 P23 / SCK0_0 / TIOA7_1 / RTO00_1 P53 / SIN6_0 / TIOA1_2 / INT07_2 83 48 P1F / AN15 / FRCK0_1 / ADTG_5 P54 / SOT6_0 / TIOB1_2 84 47 P1E / AN14 / RTS4_1 / DTTI0X_1 P55 / SCK6_0 / ADTG_1 85 46 P1D / AN13 / CTS4_1 / IC03_1 P56 / INT08_2 86 45 P1C / AN12 / SCK4_1 / IC02_1 P30 / TIOB0_1 / INT03_2 87 44 P1B / AN11 / SOT4_1 / IC01_1 P31 / SCK6_1 / TIOB1_1 / INT04_2 88 43 P1A / AN10 / SIN4_1 / INT05_1 / IC00_1 P32 / SOT6_1 / TIOB2_1 / INT05_2 89 42 P19 / AN09 / SCK2_2 P33 / SIN6_1 / TIOB3_1 / INT04_0 / ADTG_6 90 41 P18 / AN08 / SOT2_2 P34 / TIOB4_1 / FRCK0_0 91 40 AVSS P35 / TIOB5_1 / INT08_1 / IC03_0 92 39 AVRH P36 / SIN5_2 / INT09_1 / IC02_0 93 38 AVCC P37 / SOT5_2 / INT10_1 / IC01_0 94 37 P17 / AN07 / SIN2_2 / INT04_1 P38 / SCK5_2 / INT11_1 / IC00_0 95 36 P16 / AN06 / SCK0_1 P39 / DTTI0X_0 / ADTG_2 96 35 P15 / AN05 / SOT0_1 / IC03_2 P3A / TIOA0_1 / RTO00_0 / RTCCO_2 / SUBOUT_2 97 34 P14 / AN04 / SIN0_1 / INT03_1 / IC02_2 P3B / TIOA1_1 / RTO01_0 98 33 P13 / AN03 / SCK1_1 / IC01_2 / RTCCO_1 / SUBOUT_1 P3C / TIOA2_1 / RTO02_0 99 32 P12 / AN02 / SOT1_1 / IC00_2 P3D / TIOA3_1 / RTO03_0 100 31 P11 / AN01 / SIN1_1 / INT02_1 / FRCK0_2 / WKUP1 28 29 30 VSS VCC P10 / AN00 25 26 27 MD0 PE2 / X0 PE0 / MD1 PE3 / X1 22 23 24 P4D / SOT7_1 / TIOB4_0 / DA0 P4E / SIN7_1 / TIOB5_0 / INT06_2 / DA1 20 21 P4B / TIOB2_0 / IGTRG P4C / SCK7_1 / TIOB3_0 / CEC0 17 18 19 P48 / SIN3_2 / INT14_1 P49 / SOT3_2 / TIOB0_0 INITX P4A / SCK3_2 / TIOB1_0 15 16 P47 / X1A 12 13 14 VSS VCC C P46 / X0A 9 10 11 P44 / TIOA4_0 P45 / TIOA5_0 6 7 8 P42 / TIOA2_0 P41 / TIOA1_0 / INT13_1 P43 / TIOA3_0 / ADTG_7 3 4 5 VSS VCC P3F / TIOA5_1 / RTO05_0 P40 / TIOA0_0 / INT12_1 1 2 P3E / TIOA4_1 / RTO04_0 QFP - 100 Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-05675 Rev. *E Page 11 of 99 CY9A1A0N Series 4. List of Pin Functions List of pin numbers The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. LQFP-64 1 Pin No LQFP-80 LQFP-100 1 1 QFP-100 79 Pin name VCC I/O circuit type Pin state type - P50 2 2 2 80 INT00_0 E F E F E F E F E H E H E O E F E F E F SIN3_1 P51 3 3 3 81 INT01_0 SOT3_1 (SDA3_1) P52 4 4 4 82 INT02_0 SCK3_1 (SCL3_1) P53 - 5 5 83 SIN6_0 TIOA1_2 INT07_2 P54 - 6 6 84 SOT6_0 (SDA6_0) TIOB1_2 P55 - 7 7 85 SCK6_0 (SCL6_0) ADTG_1 - 8 8 86 5 9 9 87 P56 INT08_2 P30 TIOB0_1 INT03_2 P31 TIOB1_1 6 10 10 88 SCK6_1 (SCL6_1) INT04_2 P32 TIOB2_1 7 11 11 89 SOT6_1 (SDA6_1) INT05_2 Document Number: 002-05675 Rev. *E Page 12 of 99 CY9A1A0N Series Pin No LQFP-80 LQFP-100 LQFP-64 Pin name QFP-100 I/O circuit type Pin state type P33 INT04_0 8 12 12 90 TIOB3_1 E F E H E F E F E F E F E H E H E H E H SIN6_1 ADTG_6 P34 - - 13 91 FRCK0_0 TIOB4_1 P35 - - 14 92 IC03_0 TIOB5_1 INT08_1 P36 - - 15 93 IC02_0 SIN5_2 INT09_1 P37 IC01_0 - - 16 94 SOT5_2 (SDA5_2) INT10_1 P38 IC00_0 - - 17 95 SCK5_2 (SCL5_2) INT11_1 P39 9 13 18 96 DTTI0X_0 ADTG_2 P3A 10 14 19 97 RTO00_0 (PPG00_0) TIOA0_1 RTCCO_2 SUBOUT_2 P3B 11 15 20 98 RTO01_0 (PPG00_0) TIOA1_1 P3C 12 16 21 99 RTO02_0 (PPG02_0) TIOA2_1 Document Number: 002-05675 Rev. *E Page 13 of 99 CY9A1A0N Series Pin No LQFP-80 LQFP-100 LQFP-64 Pin name QFP-100 I/O circuit type Pin state type P3D 13 17 22 100 RTO03_0 (PPG02_0) E H E H E H TIOA3_1 P3E 14 18 23 1 RTO04_0 (PPG04_0) TIOA4_1 P3F 15 19 24 2 RTO05_0 (PPG04_0) TIOA5_1 16 20 25 3 VSS - - - 26 4 VCC - P40 - - 27 5 TIOA0_0 E F E F E H E H E H E H INT12_1 P41 - - 28 6 TIOA1_0 INT13_1 - - 29 7 P42 TIOA2_0 P43 - - 30 8 TIOA3_0 ADTG_7 P44 - 21 31 9 - 22 32 10 17 23 33 11 C - - 24 34 12 VSS - 18 25 35 13 VCC - 19 26 36 14 20 27 37 15 21 28 38 16 - 29 39 17 TIOA4_0 P45 TIOA5_0 P46 X0A P47 X1A INITX D M D N B C E F P48 INT14_1 SIN3_2 Document Number: 002-05675 Rev. *E Page 14 of 99 CY9A1A0N Series LQFP-64 Pin No LQFP-80 LQFP-100 Pin name QFP-100 I/O circuit type Pin state type P49 22 30 40 18 - TIOB0_0 SOT3_2 (SDA3_2) E H E H E H G Q J T J S C P H D A A A B P4A 23 31 41 19 - TIOB1_0 SCK3_2 (SCL3_2) P4B 24 32 42 20 TIOB2_0 IGTRG P4C TIOB3_0 25 33 43 21 SCK7_1 (SCL7_1) CEC0 P4D TIOB4_0 26 34 44 22 SOT7_1 (SDA7_1) DA0 P4E TIOB5_0 27 35 45 23 INT06_2 SIN7_1 DA1 PE0 28 36 46 24 29 37 47 25 30 38 48 26 31 39 49 27 32 40 50 28 VSS - 33 41 51 29 VCC - 34 42 52 30 MD1 MD0 PE2 X0 PE3 X1 P10 AN00 F J F L P11 AN01 35 43 53 31 SIN1_1 INT02_1 FRCK0_2 WKUP1 Document Number: 002-05675 Rev. *E Page 15 of 99 CY9A1A0N Series LQFP-64 Pin No LQFP-80 LQFP-100 Pin name QFP-100 I/O circuit type Pin state type P12 AN02 36 44 54 32 SOT1_1 (SDA1_1) F J F J F K F J F J F K IC00_2 P13 AN03 37 45 55 33 SCK1_1 (SCL1_1) IC01_2 RTCCO_1 SUBOUT_1 P14 38 AN04 46 56 34 IC02_2 INT03_1 SIN0_1 - P15 39 AN05 47 57 35 IC03_2 SOT0_1 (SDA0_1) - P16 - 48 58 36 AN06 SCK0_1 (SCL0_1) P17 40 49 59 37 AN07 SIN2_2 INT04_1 41 50 60 38 AVCC - 42 51 61 39 AVRH - 43 52 62 40 AVSS - P18 44 53 63 41 AN08 SOT2_2 (SDA2_2) F J F J P19 45 54 64 Document Number: 002-05675 Rev. *E 42 AN09 SCK2_2 (SCL2_2) Page 16 of 99 CY9A1A0N Series Pin No LQFP-80 LQFP-100 LQFP-64 Pin name QFP-100 I/O circuit type Pin state type P1A AN10 - 55 65 43 SIN4_1 F K F J F J F J F J F J E H E H E G E F INT05_1 IC00_1 P1B AN11 - 56 66 44 SOT4_1 (SDA4_1) IC01_1 P1C AN12 - - 67 45 SCK4_1 (SCL4_1) IC02_1 P1D - - 68 46 AN13 CTS4_1 IC03_1 P1E - - 69 47 AN14 RTS4_1 DTTI0X_1 P1F - - 70 48 AN15 ADTG_5 FRCK0_1 P23 46 57 71 49 SCK0_0 (SCL0_0) TIOA7_1 - RTO00_1 - P22 47 58 72 50 SOT0_0 (SDA0_0) TIOB7_1 P21 48 59 73 51 SIN0_0 INT06_1 WKUP2 P20 - 60 74 52 INT05_0 CROUT_0 Document Number: 002-05675 Rev. *E Page 17 of 99 CY9A1A0N Series - Pin No LQFP-80 LQFP-100 75 76 QFP-100 53 54 49 61 77 55 50 62 78 56 51 63 79 57 52 64 80 58 53 65 81 59 - - 82 60 - - 83 61 84 62 LQFP-64 66 - - 85 63 - - 86 64 54 67 87 65 55 68 88 66 56 69 89 67 Document Number: 002-05675 Rev. *E I/O circuit type Pin name VSS VCC P00 TRSTX P01 TCK SWCLK P02 TDI P03 TMS SWDIO P04 TDO SWO P05 TIOA5_2 SIN4_2 INT00_1 P06 TIOB5_2 SOT4_2 (SDA4_2) INT01_1 P07 ADTG_0 SCK4_2 (SCL4_2) P08 TIOA0_2 CTS4_2 P09 TIOB0_2 RTS4_2 P0A SIN4_0 INT00_2 P0B SOT4_0 (SDA4_0) TIOB6_1 P0C SCK4_0 (SCL4_0) TIOA6_1 Pin state type E E E E E E E E E E E F E F E H E H E H G F G H G H Page 18 of 99 CY9A1A0N Series LQFP-64 Pin No LQFP-80 LQFP-100 I/O circuit type Pin name QFP-100 Pin state type P0D - 70 90 68 RTS4_0 E H E H E I E O E H E H G R G H G H H TIOA3_2 P0E - 71 91 69 CTS4_0 TIOB3_2 P0F NMIX 57 72 92 70 CROUT_1 RTCCO_0 SUBOUT_0 WKUP0 - 73 93 71 P63 INT03_0 P62 58 74 94 72 SCK5_0 (SCL5_0) ADTG_3 P61 59 75 95 73 SOT5_0 (SDA5_0) TIOB2_2 DTTI0X_2 P60 SIN5_0 60 76 96 74 TIOA2_2 INT15_1 WKUP3 CEC1 61 77 97 75 P80 SIN7_2 P81 62 78 98 76 SOT7_2 (SDA7_2) P82 63 79 99 77 SCK7_2 (SCL7_2) G 64 80 100 78 VSS - Document Number: 002-05675 Rev. *E Page 19 of 99 CY9A1A0N Series List of pin functions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin function ADC ADTG_0 - Pin No LQFP-80 LQFP-100 66 84 ADTG_1 - 7 7 85 ADTG_2 9 13 18 96 58 74 94 72 - - - - ADTG_5 - - 70 48 ADTG_6 8 12 12 90 ADTG_7 - - 30 8 ADTG_8 - - - - AN00 34 42 52 30 AN01 35 43 53 31 AN02 36 44 54 32 AN03 37 45 55 33 AN04 38 46 56 34 AN05 39 47 57 35 AN06 - 48 58 36 40 49 59 37 44 53 63 41 AN09 45 54 64 42 AN10 - 55 65 43 AN11 - 56 66 44 AN12 - - 67 45 AN13 - - 68 46 AN14 - - 69 47 AN15 - - 70 48 Pin name Function description ADTG_3 ADTG_4 AN07 AN08 A/D converter external trigger input pin A/D converter analog input pin. ANxx describes ADC ch.xx. Document Number: 002-05675 Rev. *E LQFP-64 QFP-100 62 Page 20 of 99 CY9A1A0N Series Pin function Base Timer 0 Base Timer 1 Base Timer 2 Base Timer 3 Base Timer 4 Base Timer 5 Base Timer 6 Base Timer 7 Pin name TIOA0_0 TIOA0_1 TIOA0_2 TIOB0_0 TIOB0_1 TIOB0_2 TIOA1_0 TIOA1_1 TIOA1_2 TIOB1_0 TIOB1_1 TIOB1_2 TIOA2_0 TIOA2_1 TIOA2_2 TIOB2_0 TIOB2_1 TIOB2_2 TIOA3_0 TIOA3_1 TIOA3_2 TIOB3_0 TIOB3_1 TIOB3_2 TIOA4_0 TIOA4_1 TIOA4_2 TIOB4_0 TIOB4_1 TIOB4_2 TIOA5_0 TIOA5_1 TIOA5_2 TIOB5_0 TIOB5_1 TIOB5_2 Function description Base timer ch.0 TIOA pin Base timer ch.0 TIOB pin Base timer ch.1 TIOA pin Base timer ch.1 TIOB pin Base timer ch.2 TIOA pin Base timer ch.2 TIOB pin Base timer ch.3 TIOA pin Base timer ch.3 TIOB pin Base timer ch.4 TIOA pin Base timer ch.4 TIOB pin Base timer ch.5 TIOA pin Base timer ch.5 TIOB pin 10 22 5 11 23 6 12 60 24 7 59 13 25 8 14 26 15 27 - Pin No LQFP-80 LQFP-100 27 14 19 85 30 40 9 9 86 28 15 20 5 5 31 41 10 10 6 6 29 16 21 76 96 32 42 11 11 75 95 30 17 22 70 90 33 43 12 12 71 91 21 31 18 23 34 44 13 22 32 19 24 82 35 45 14 83 5 97 63 18 87 64 6 98 83 19 88 84 7 99 74 20 89 73 8 100 68 21 90 69 9 1 22 91 10 2 60 23 92 61 LQFP-64 QFP-100 TIOA6_1 Base timer ch.6 TIOA pin 56 69 89 67 TIOB6_1 Base timer ch.6 TIOB pin 55 68 88 66 46 47 - 57 58 - 71 72 - 49 50 - TIOA7_0 TIOA7_1 TIOA7_2 TIOB7_0 TIOB7_1 TIOB7_2 Base timer ch.7 TIOA pin Base timer ch.7 TIOB pin Document Number: 002-05675 Rev. *E Page 21 of 99 CY9A1A0N Series Pin function Debugger Pin name SWCLK Pin No LQFP-100 78 LQFP-64 50 LQFP-80 62 QFP-100 56 52 64 80 58 53 65 81 59 SWO Serial wire debug interface clock input pin Serial wire debug interface data input / output pin Serial wire viewer output pin TRSTX JTAG reset input pin 49 61 77 55 TCK JTAG test clock input pin 50 62 78 56 TDI JTAG test data input pin 51 63 79 57 TMS JTAG test mode state input/output pin 52 64 80 58 TDO JTAG debug data output pin 53 65 81 59 2 2 2 80 - - 82 60 54 67 87 65 3 3 3 81 - - 83 61 4 4 4 82 35 43 53 31 - 73 93 71 38 46 56 34 INT03_2 5 9 9 87 INT04_0 8 12 12 90 40 49 59 37 6 10 10 88 - 60 74 52 - 55 65 43 INT05_2 7 11 11 89 INT06_1 48 59 73 51 27 35 45 23 - 5 5 83 - - 14 92 - 8 8 86 SWDIO External Interrupt Function description INT00_0 INT00_1 External interrupt request 00 input pin INT00_2 INT01_0 INT01_1 INT02_0 INT02_1 External interrupt request 01 input pin External interrupt request 02 input pin INT03_0 INT03_1 INT04_1 External interrupt request 03 input pin External interrupt request 04 input pin INT04_2 INT05_0 INT05_1 INT06_2 INT07_2 INT08_1 INT08_2 External interrupt request 05 input pin External interrupt request 06 input pin External interrupt request 07 input pin External interrupt request 08 input pin INT09_1 External interrupt request 09 input pin - - 15 93 INT10_1 External interrupt request 10 input pin - - 16 94 INT11_1 External interrupt request 11 input pin - - 17 95 INT12_1 External interrupt request 12 input pin - - 27 5 INT13_1 External interrupt request 13 input pin - - 28 6 INT14_1 External interrupt request 14 input pin - 29 39 17 INT15_1 External interrupt request 15 input pin 60 76 96 74 NMIX Non-Maskable Interrupt input pin 57 72 92 70 Document Number: 002-05675 Rev. *E Page 22 of 99 CY9A1A0N Series Pin function GPIO P00 LQFP-64 49 Pin No LQFP-80 LQFP-100 61 77 QFP-100 55 P01 50 62 78 56 P02 51 63 79 57 P03 52 64 80 58 P04 53 65 81 59 P05 - - 82 60 P06 - - 83 61 P07 - 66 84 62 Pin name P08 Function description General-purpose I/O port 0 - - 85 63 P09 - - 86 64 P0A 54 67 87 65 P0B 55 68 88 66 P0C 56 69 89 67 P0D - 70 90 68 P0E - 71 91 69 P0F 57 72 92 70 P10 34 42 52 30 P11 35 43 53 31 P12 36 44 54 32 P13 37 45 55 33 P14 38 46 56 34 P15 39 47 57 35 P16 - 48 58 36 40 49 59 37 44 53 63 41 P19 45 54 64 42 P1A - 55 65 43 P1B - 56 66 44 P1C - - 67 45 P1D - - 68 46 P1E - - 69 47 P1F - - 70 48 P20 - 60 74 52 48 59 73 51 47 58 72 50 46 57 71 49 P17 P18 P21 P22 General-purpose I/O port 1 General-purpose I/O port 2 P23 Document Number: 002-05675 Rev. *E Page 23 of 99 CY9A1A0N Series Pin function GPIO Pin name P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P3A P3B P3C P3D P3E P3F P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P4A P4B P4C P4D P4E P50 P51 P52 P53 P54 P55 P56 P60 P61 P62 P63 P80 P81 P82 PE0 PE2 PE3 Function description General-purpose I/O port 3 General-purpose I/O port 4 General-purpose I/O port 5 General-purpose I/O port 6 General-purpose I/O port 8 General-purpose I/O port E Document Number: 002-05675 Rev. *E LQFP-64 5 6 7 8 9 10 11 12 13 14 15 19 20 22 23 24 25 26 27 2 3 4 60 59 58 61 62 63 28 30 31 LQFP-80 9 10 11 12 13 14 15 16 17 18 19 21 22 26 27 29 30 31 32 33 34 35 2 3 4 5 6 7 8 76 75 74 73 77 78 79 36 38 39 Pin No LQFP-100 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 27 28 29 30 31 32 36 37 39 40 41 42 43 44 45 2 3 4 5 6 7 8 96 95 94 93 97 98 99 46 48 49 QFP-100 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 5 6 7 8 9 10 14 15 17 18 19 20 21 22 23 80 81 82 83 84 85 86 74 73 72 71 75 76 77 24 26 27 Page 24 of 99 CY9A1A0N Series Pin function Multifunction Serial 0 Pin name SIN0_0 SIN0_1 SOT0_0 (SDA0_0) SOT0_1 (SDA0_1) SCK0_0 (SCL0_0) SCK0_1 (SCL0_1) Multifunction Serial 1 Multifunction Serial 2 Function description Multi-function serial interface ch.0 input pin Multi-function serial interface ch.0 output pin. This pin operates as SOT0 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA0 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.0 clock I/O pin. This pin operates as SCK0 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL0 when it is used in an I2C (operation mode 4). Pin No LQFP-64 48 LQFP-80 59 LQFP-100 73 QFP-100 51 - 46 56 34 47 58 72 50 - 47 57 35 46 57 71 49 - 48 58 36 SIN1_1 Multi-function serial interface ch.1 input pin 35 43 53 31 SOT1_1 (SDA1_1) Multi-function serial interface ch.1 output pin. This pin operates as SOT1 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA1 when it is used in an I2C (operation mode 4). 36 44 54 32 SCK1_1 (SCL1_1) Multi-function serial interface ch.1 clock I/O pin. This pin operates as SCK1 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL1 when it is used in an I2C (operation mode 4). 37 45 55 33 40 49 59 37 44 53 63 41 45 54 64 42 SIN2_2 SOT2_2 (SDA2_2) SCK2_2 (SCL2_2) Multi-function serial interface ch.2 input pin Multi-function serial interface ch.2 output pin. This pin operates as SOT2 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA2 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.2 clock I/O pin. This pin operates as SCK2 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL2 when it is used in an I2C (operation mode 4). Document Number: 002-05675 Rev. *E Page 25 of 99 CY9A1A0N Series Pin function Multifunction Serial 3 SIN3_1 SIN3_2 SOT3_1 (SDA3_1) SOT3_2 (SDA3_2) SCK3_1 (SCL3_1) SCK3_2 (SCL3_2) Multifunction Serial 4 LQFP-64 2 Pin No LQFP-80 LQFP-100 2 2 QFP-100 80 - 29 39 17 3 3 3 81 - 30 40 18 4 4 4 82 - 31 41 19 54 67 87 65 - 55 65 43 - - 82 60 Multi-function serial interface ch.4 output pin. This pin operates as SOT4 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA4 when it is used in an I2C (operation mode 4). 55 68 88 66 - 56 66 44 - - 83 61 Multi-function serial interface ch.4 clock I/O pin. This pin operates as SCK4 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL4 when it is used in an I2C (operation mode 4). 56 69 89 67 - - 67 45 - - 84 62 - 70 90 68 - - 69 47 - - 86 64 - 71 91 69 - - 68 46 - - 85 63 Pin name Function description Multi-function serial interface ch.3 input pin Multi-function serial interface ch.3 output pin. This pin operates as SOT3 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA3 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.3 clock I/O pin. This pin operates as SCK3 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL3 when it is used in an I2C (operation mode 4). SIN4_0 SIN4_1 SIN4_2 SOT4_0 (SDA4_0) SOT4_1 (SDA4_1) SOT4_2 (SDA4_2) SCK4_0 (SCL4_0) SCK4_1 (SCL4_1) SCK4_2 (SCL4_2) Multi-function serial interface ch.4 input pin RTS4_0 RTS4_1 RTS4_2 Multi-function serial interface ch.4 RTS output pin CTS4_0 CTS4_1 CTS4_2 Multi-function serial interface ch.4 CTS input pin Document Number: 002-05675 Rev. *E Page 26 of 99 CY9A1A0N Series Pin function Multifunction Serial 5 Pin name SIN5_0 SIN5_2 SOT5_0 (SDA5_0) SOT5_2 (SDA5_2) SCK5_0 (SCL5_0) SCK5_2 (SCL5_2) Multifunction Serial 6 SIN6_0 SIN6_1 SOT6_0 (SDA6_0) SOT6_1 (SDA6_1) SCK6_0 (SCL6_0) SCK6_1 (SCL6_1) Multifunction Serial 7 SIN7_1 SIN7_2 SOT7_1 (SDA7_1) SOT7_2 (SDA7_2) SCK7_1 (SCL7_1) SCK7_2 (SCL7_2) Function description Multi-function serial interface ch.5 input pin Multi-function serial interface ch.5 output pin. This pin operates as SOT5 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA5 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.5 clock I/O pin. This pin operates as SCK5 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL5 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.6 input pin Multi-function serial interface ch.6 output pin. This pin operates as SOT6 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA6 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.6 clock I/O pin. This pin operates as SCK6 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL6 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.7 input pin Multi-function serial interface ch.7 output pin. This pin operates as SOT7 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA7 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.7 clock I/O pin. This pin operates as SCK7 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL7 when it is used in an I2C (operation mode 4). Document Number: 002-05675 Rev. *E LQFP-64 60 Pin No LQFP-80 LQFP-100 76 96 - - 15 93 59 75 95 73 - - 16 94 58 74 94 72 - - 17 95 - 5 5 83 8 12 12 90 - 6 6 84 7 11 11 89 - 7 7 85 6 10 10 88 27 35 45 23 61 77 97 75 26 34 44 22 62 78 98 76 25 33 43 21 63 79 99 77 QFP-100 74 Page 27 of 99 CY9A1A0N Series Pin function Multifunction Timer 0 Pin name DTTI0X_0 DTTI0X_1 DTTI0X_2 Input signal of waveform generator to control outputs RTO00 to RTO05 of Multi-function timer 0 FRCK0_0 FRCK0_1 FRCK0_2 9 Pin No LQFP-80 LQFP-100 13 18 - - 69 47 59 75 95 73 - - 13 91 - - 70 48 Function description 16-bit free-run timer ch.0 external clock input pin LQFP-64 QFP-100 96 35 43 53 31 IC00_0 - - 17 95 IC00_1 - 55 65 43 IC00_2 36 44 54 32 IC01_0 - - 16 94 IC01_1 - 56 66 44 37 45 55 33 - - 15 93 IC02_1 - - 67 45 IC02_2 38 46 56 34 IC03_0 - - 14 92 IC03_1 - - 68 46 IC03_2 RTO00_0 (PPG00_0) RTO00_1 (PPG00_1) 39 47 57 35 10 14 19 97 - - 71 49 11 15 20 98 12 16 21 99 13 17 22 100 14 18 23 1 15 19 24 2 24 32 42 20 IC01_2 IC02_0 RTO01_0 (PPG00_0) RTO02_0 (PPG02_0) RTO03_0 (PPG02_0) RTO04_0 (PPG04_0) RTO05_0 (PPG04_0) IGTRG 16-bit input capture input pin of Multi-function timer 0. ICxx describes a channel number. Waveform generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output mode. Waveform generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output mode. Waveform generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output mode. Waveform generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output mode. Waveform generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output mode. Waveform generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output mode. PPG IGBT mode external trigger input pin Document Number: 002-05675 Rev. *E Page 28 of 99 CY9A1A0N Series Pin function Real-time clock Pin name Function description RTCCO_0 RTCCO_1 Pulse output pin of Real-time clock RTCCO_2 SUBOUT_0 SUBOUT_1 Sub clock output pin SUBOUT_2 LowPower Consumption Mode QFP-100 70 37 45 55 33 10 14 19 97 57 72 92 70 37 45 55 33 10 14 19 97 57 72 92 70 35 43 53 31 48 59 73 51 60 76 96 74 26 34 44 22 DA0 DA1 D/A converter ch.1 analog output pin 27 35 45 23 CEC0 HDMI-CEC ch.0 pin 25 33 43 21 CEC1 HDMI-CEC ch.1 pin 60 76 96 74 WKUP0 WKUP1 WKUP3 HDMICEC Pin No LQFP-80 LQFP-100 72 92 Deep standby mode return signal input pin 0 Deep standby mode return signal input pin 1 Deep standby mode return signal input pin 2 Deep standby mode return signal input pin 3 D/A converter ch.0 analog output pin WKUP2 DAC LQFP-64 57 Document Number: 002-05675 Rev. *E Page 29 of 99 CY9A1A0N Series Pin function Reset Pin name INITX Mode MD0 MD1 Function description External Reset Input Pin. A reset is valid when INITX = L. Mode 0 pin. During normal operation, MD0 = L must be input. During serial programming to Flash memory, MD0 = H must be input. Mode 1 pin. During normal operation, input is not needed. During serial programming to Flash memory, MD1 = L must be input. Power VCC Power supply pin GND VSS Clock QFP-100 21 28 38 16 29 37 47 25 28 36 46 24 1 1 1 79 - - 26 4 18 25 35 13 33 41 51 29 - - 76 54 16 20 25 3 - 24 34 12 32 40 50 28 - - 75 53 64 80 100 78 Main clock (oscillation) input pin 30 38 48 26 X0A Sub clock (oscillation) input pin 19 26 36 14 X1 Main clock (oscillation) I/O pin 31 39 49 27 X1A Sub clock (oscillation) I/O pin 20 27 37 15 Built-in High-speed CR-osc clock output port - 60 74 52 57 72 92 70 A/D converter and D/A converter analog power supply pin A/D converter analog reference voltage input pin A/D converter and D/A converter GND pin 41 50 60 38 42 51 61 39 43 52 62 40 Power supply stabilization capacity pin 17 23 33 11 CROUT_1 AVCC AVRH Analog GND C pin Pin No LQFP-80 LQFP-100 X0 CROUT_0 Analog Power GND pin LQFP-64 AVSS C Note: − While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP controller. Document Number: 002-05675 Rev. *E Page 30 of 99 CY9A1A0N Series 5. I/O Circuit Type Type Circuit Remarks It is possible to select the main oscillation / GPIO function. A Pull-up When the main oscillation is selected. resistor P-ch P-ch Digital output X1 • Oscillation feedback resistor : Approximately 1 MΩ • With standby mode control When the GPIO is selected. N-ch Digital output R Pull-up resistor control • • • • • CMOS level output. CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ • IOH = -4 mA, IOL = 4 mA Digital input Standby mode control Clock input Feedback resistor Standby mode control Digital input Standby mode control Pull-up resistor R P-ch P-ch Digital output N-ch Digital output X0 Pull-up resistor control B • CMOS level hysteresis input • Pull-up resistor : Approximately 50 kΩ Pull-up resistor Digital input Document Number: 002-05675 Rev. *E Page 31 of 99 CY9A1A0N Series Type Circuit Remarks C Digital input • Open drain output • CMOS level hysteresis input Digital output N-ch It is possible to select the sub oscillation / GPIO function D Pull-up When the sub oscillation is selected. resistor P-ch P-ch Digital output X1A N-ch Digital output R Pull-up resistor control • Oscillation feedback resistor : Approximately 5 MΩ • With standby mode control When the GPIO is selected. • CMOS level output. • CMOS level hysteresis input • With pull-up resistor control • With standby mode control • Pull-up resistor : Approximately 50 kΩ • IOH = -4 mA, IOL = 4 mA Digital input Standby mode control Clock input Feedback resistor Standby mode control Digital input Standby mode control Pull-up resistor R P-ch P-ch Digital output N-ch Digital output X0A Pull-up resistor control Document Number: 002-05675 Rev. *E Page 32 of 99 CY9A1A0N Series Type Circuit Remarks E • • • • • P-ch P-ch N-ch Digital output CMOS level output CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ • IOH = -4 mA, IOL = 4 mA • When this pin is used as an I2C pin, the digital output P-ch transistor is always off Digital output R Pull-up resistor control Digital input Standby mode control F P-ch P-ch N-ch R Digital output Digital output • • • • • • • CMOS level output CMOS level hysteresis input With input control Analog input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ • IOH = -4 mA, IOL = 4 mA • When this pin is used as an I2C pin, the digital output P-ch transistor is always off Pull-up resistor control Digital input Standby mode control Analog input Input control Document Number: 002-05675 Rev. *E Page 33 of 99 CY9A1A0N Series Type Circuit Remarks G P-ch N-ch Digital output • • • • • • CMOS level output CMOS level hysteresis input With standby mode control 5 V tolerant input IOH = -4 mA, IOL = 4 mA Available to control PZR registers. P0B, P0C, P4C, P60, P81, P82 only. • When this pin is used as an I2C pin, the digital output P-ch transistor is always off Digital output R Digital input Standby mode control CMOS level hysteresis input H Mode input J P-ch P-ch N-ch R Digital output Digital output • • • • • • • CMOS level output CMOS level hysteresis input With input control Analog output With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kΩ • IOH = -4 mA, IOL = 4 mA • When this pin is used as an I2C pin, the digital output P-ch transistor is always off Pull-up resistor control Digital input Standby mode control Analog output Document Number: 002-05675 Rev. *E Page 34 of 99 CY9A1A0N Series 6. Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices. 6.1 Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. 1. Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. 2. Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. 3. Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: 1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. 2. Be sure that abnormal current flows do not occur during the power-on sequence. Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Document Number: 002-05675 Rev. *E Page 35 of 99 CY9A1A0N Series Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 6.2 Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Cypress' recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress Inc. recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions. Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: 1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. 2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. 3. When necessary, Cypress Inc. packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. 4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125°C/24 h Document Number: 002-05675 Rev. *E Page 36 of 99 CY9A1A0N Series Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: 1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. 2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. 3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. 4. Ground all fixtures and instruments, or protect with anti-static measures. 5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. 6.3 Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: 1. 2. 3. 4. 5. Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives. Document Number: 002-05675 Rev. *E Page 37 of 99 CY9A1A0N Series 7. Handling Devices Power supply pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each Power supply pins and GND pins of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pin and GND pin, between AVCC pin and AVSS pin near this device. Stabilizing power supply voltage A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary fluctuation on switching the power supply. Crystal oscillator circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation. Evaluate oscillation of your using crystal oscillator by your mount board. Using an external clock To use the external clock, set general-purpose I/O ports to input the clock to X0/PE2 and X0A/P46 pin.  Example of Using an External Clock Device X0/PE2 (X0A/P46) Can be used as general-purpose I/O ports. X1/PE3 (X1A/P47) Set as general-purpose I/O ports. Handling when using Multi-function serial pin as I2C pin If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled. However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external I2C bus system with power OFF. Document Number: 002-05675 Rev. *E Page 38 of 99 CY9A1A0N Series C Pin This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7μF would be recommended for this series. C Device Cs VSS GND Mode pins (MD0, MD1) Connect the MD pin (MD0, MD1) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise. Notes on power-on Turn power on/off in the following order or at the same time. If not using the A/D converter, connect AVCC = VCC and AVSS = VSS. Turning on: VCC  AVCC  AVRH Turning off: AVRH  AVCC  VCC Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data. Differences in features among the products with different memory sizes and between Flash memory products and MASK products The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash memory products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. Document Number: 002-05675 Rev. *E Page 39 of 99 CY9A1A0N Series 8. Block Diagram MB9AF1A1/1A2 ROM Table SWJ-DP Cortex-M3 Core @20MHz(Max) Flash I/F I Multi-layer AHB (Max 20MHz) TRSTX,TCK, TDI,TMS TDO D Sys AHB-APB Bridge: APB0 (Max 20MHz) NVIC Watchdog Timer (Software) Clock Reset Generator INITX Watchdog Timer (Hardware) Security On-Chip Flash 64/128Kbyte SRAM1 12/16Kbyte CSV CLK X0 X1 X0A X1A Main Osc Sub Osc PLL Source Clock CR 4MHz CR 100kHz CROUT AVCC, AVSS,AVRH ANxx Deep Standby Ctrl WKUPx 12-bit A/D Converter Power On Reset Unit 0 LVD Ctrl ADTGx LVD Regulator TIOBx Base Timer 16-bit 8ch./ 32-bit 4ch. A/D Activation Compare 1ch. IC0x FRCK0 16-bit Input Capture 4ch. 16-bit FreeRun Timer 3ch. 16-bit Output Compare 6ch. DTTI0X RTO0x IGTRG AHB-APB Bridge : APB2 (Max 20MHz) TIOAx AHB-APB Bridge : APB1 (Max 20MHz) DAx HDMI-CEC/ Remote Receiver Control Multi-Function Timer ×1 CECx RTCCO SUBOUT Real Time Clock External Interrupt Controller 16-pin + NMI INTxx NMIX MODE-Ctrl MD1, MD0 P0x, P1x, GPIO Waveform Generator 3ch. 16-bit PPG 3ch. C IRQ-Monitor 10-bit D/A Converter 2ch. PIN-Function-Ctrl . . . Pxx Multi-Function Serial IF 8ch. HW flow control(ch.4)* SCKx SINx SOTx CTS4 RTS4 *: For the CY9AF1A1L and CY9AF1A2L, Multi-function Serial Interface does not support hardware flow control in these products. Document Number: 002-05675 Rev. *E Page 40 of 99 CY9A1A0N Series 9. Memory Size See Memory size in Product Lineup to confirm the memory size. 10. Memory Map Memory Map (1) Peripherals Area 0x41FF_FFFF 0xFFFF_FFFF Reserved 0xE010_0000 0xE000_0000 Cortex-M3 Private Peripherals Reserved Reserved 0x4003_C000 0x4003_B000 0x4003_9000 0x4003_8000 0x4400_0000 0x4200_0000 32Mbytes Bit band alias 0x4003_6000 0x4003_5000 Peripherals 0x4003_4000 0x4003_3000 0x4003_2000 0x4003_1000 0x4003_0000 0x4002_F000 0x4002_E000 0x4000_0000 Reserved 0x2400_0000 0x2200_0000 32Mbytes Bit band alias Reserved 0x2008_0000 0x2000_0000 SRAM1 0x4002_9000 0x4002_8000 0x4002_7000 0x4002_6000 0x4002_5000 0x4002_4000 Reserved See " Memory Map (2)" for the memory size details. 0x0010_0008 0x0010_0000 Security/CR Trim MFS Reserved LVD/DS mode HDMI-CEC/ Remote Control Receiver GPIO Reserved Int-Req.Read EXTI Reserved CR Trim Reserved D/AC A/DC Reserved Base Timer PPG MFT unit0 Reserved 0x4001_3000 0x4001_2000 0x4001_1000 0x4001_0000 0x4000_1000 0x4000_0000 Document Number: 002-05675 Rev. *E Reserved Reserved 0x4002_1000 0x4002_0000 Flash 0x0000_0000 RTC SW WDT HW WDT Clock/Reset Reserved Flash I/F Page 41 of 99 CY9A1A0N Series Memory Map (2) *: See CY9AAA0N/1A0N/A30N/130N/130L Series Flash Programming Manual to confirm the detail of Flash memory. Peripheral Address Map Document Number: 002-05675 Rev. *E Page 42 of 99 CY9A1A0N Series Start address End address Bus Peripherals 0x4000_0000 0x4000_0FFF 0x4000_1000 0x4000_FFFF 0x4001_0000 0x4001_0FFF Clock/Reset Control 0x4001_1000 0x4001_1FFF Hardware Watchdog timer 0x4001_2000 0x4001_2FFF 0x4001_3000 0x4001_4FFF 0x4001_5000 0x4001_5FFF Reserved 0x4001_6000 0x4001_FFFF Reserved 0x4002_0000 0x4002_0FFF Multi-function timer unit0 0x4002_1000 0x4002_1FFF Reserved 0x4002_2000 0x4002_3FFF Reserved 0x4002_4000 0x4002_4FFF PPG 0x4002_5000 0x4002_5FFF 0x4002_6000 0x4002_6FFF 0x4002_7000 0x4002_7FFF A/D Converter 0x4002_8000 0x4002_8FFF D/A Converter 0x4002_9000 0x4002_DFFF Reserved 0x4002_E000 0x4002_EFFF Built-in CR trimming 0x4002_F000 0x4002_FFFF Reserved 0x4003_0000 0x4003_0FFF External Interrupt 0x4003_1000 0x4003_1FFF Interrupt Source Check Register 0x4003_2000 0x4003_2FFF Reserved 0x4003_3000 0x4003_3FFF GPIO 0x4003_4000 0x4003_4FFF HDMI-CEC/ Remote Control Receiver 0x4003_5000 0x4003_50FF Low-Voltage Detector 0x4003_5100 0x4003_5FFF 0x4003_6000 0x4003_6FFF 0x4003_7000 0x4003_7FFF Reserved 0x4003_8000 0x4003_8FFF Multi-function serial 0x4003_9000 0x4003_9FFF Reserved 0x4003_A000 0x4003_AFFF Reserved 0x4003_B000 0x4003_BFFF Real-time clock 0x4003_C000 0x4003_FFFF Reserved 0x4004_0000 0x4004_FFFF Reserved 0x4005_0000 0x4005_FFFF Reserved 0x4006_0000 0x4006_0FFF Reserved 0x4006_1000 0x4006_1FFF 0x4006_2000 0x4006_2FFF Reserved 0x4006_3000 0x4006_3FFF Reserved 0x4006_4000 0x41FF_FFFF Reserved Document Number: 002-05675 Rev. *E AHB APB0 Flash memory I/F register Reserved Software Watchdog timer Reserved Base Timer APB1 APB2 AHB Reserved Deep standby mode Controller Reserved Reserved Page 43 of 99 CY9A1A0N Series 11. Pin Status in Each CPU State The terms used for pin status have the following meanings.  INITX = 0 This is the period when the INITX pin is the L level.  INITX = 1 This is the period when the INITX pin is the H level.  SPL = 0 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 0.  SPL = 1 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 1.  Input enabled Indicates that the input function can be used.  Internal input fixed at 0 This is the status that the input function cannot be used. Internal input is fixed at L.  Hi-Z Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.  Setting disabled Indicates that the setting is disabled.  Maintain previous state Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained.  Analog input is enabled Indicates that the analog input is enabled.  Trace output Indicates that the trace function can be used.  GPIO selected In Deep Standby mode, pins switch to the general-purpose I/O port. Document Number: 002-05675 Rev. *E Page 44 of 99 CY9A1A0N Series Pin status type List of Pin Status Power-on Run Device mode reset or INITX or internal low-voltage input Sleep reset detection state mode state state state Function group Power Power supply Power supply stable supply unstable stable Main crystal oscillator input pin External main clock input A selected GPIO selected Main crystal oscillator output pin Input enabled Setting disabled Input enabled Setting disabled Input enabled Setting disabled Setting disabled Input enabled Maintain previous state Maintain previous state Setting disabled Setting disabled Hi-Z / Internal input fixed at 0 Maintain previous state / When Hi-Z / Hi-Z / oscillation Internal Internal stops*1, input fixed input fixed Hi-Z at 0 at 0 output / Internal input fixed at 0 B C INITX = 0 INITX = 1 INITX = 1 - Timer mode, RTC mode, or Stop mode state Power supply stable Power supply stable Power supply stable INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 SPL = 1 INITX = 1 - Input enabled Maintain previous state / When oscillation stops*1, output maintains previous state / Internal input fixed at 0 Output maintains previous state / Internal input fixed at 0 Maintain previous state / When oscillation stops*1, Hi-Z output / Internal input fixed at 0 Input enabled Input enabled Hi-Z / Input enabled / When oscillation stops*1, Hi-Z / Internal input fixed at 0 Output maintains Hi-Z / previous Internal input GPIO selected state / fixed at 0 Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Output maintains Hi-Z / previous Maintain Internal input state / previous state fixed at 0 Internal input fixed at 0 Maintain previous state / When oscillation stops*1, Hi-Z output / Internal input fixed at 0 Maintain previous state / When oscillation stops*1, Hi-Z output / Internal input fixed at 0 GPIO selected Setting disabled Setting disabled Setting disabled Maintain Maintain previous previous state state Hi-Z / Internal input fixed at 0 INITX input pin Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Document Number: 002-05675 Rev. *E Deep Standby RTC mode Return from or Deep Standby Stop Deep Standby mode state mode state Pull-up / Input enabled Output maintains previous state / Internal input fixed at 0 Pull-up / Input enabled Input enabled Maintain previous state / When oscillation stops*1, Hi-Z output / Internal input fixed at 0 Input enabled Maintain previous state / When oscillation stops*1, Hi-Z output / Internal input fixed at 0 Hi-Z / Maintain Internal input previous state fixed at 0 Pull-up / Input enabled Pull-up / Input enabled Page 45 of 99 Pin status type CY9A1A0N Series D Power-on Run Device mode reset or INITX or internal low-voltage input Sleep reset detection state mode state state state Function group Power Power supply Power supply stable supply unstable stable Mode input pin Input enabled JTAG selected Hi-Z GPIO selected Setting disabled INITX = 0 Input enabled Pull-up / Input enabled INITX = 1 Input enabled Pull-up / Input enabled Setting disabled Setting disabled Setting disabled Setting disabled E External interrupt Setting enabled disabled selected Resource other than above F selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled GPIO selected WKUP enabled External interrupt Setting enabled disabled selected G Resource other than above selected Hi-Z GPIO selected Timer mode, RTC mode, or Stop mode state Power supply stable INITX = 1 INITX = 1 SPL = 0 SPL = 1 Input Input Input enabled enabled enabled Maintain previous state Maintain Maintain previous previous Hi-Z / state state Internal input fixed at 0 Maintain previous state Maintain Maintain previous previous state state Hi-Z / Input enabled Document Number: 002-05675 Rev. *E Hi-Z / Input enabled Power supply stable Power supply stable INITX = 1 INITX = 1 SPL = 0 SPL = 1 Input Input Input enabled enabled enabled Maintain previous state Maintain Maintain previous previous state Hi-Z / state Internal input fixed at 0 GPIO selected Internal input fixed at 0 GPIO selected Hi-Z / Internal input fixed at 0 Hi-Z / Internal Output input fixed maintains at 0 previous Maintain state / previous state Internal input fixed at 0 Hi-Z / Hi-Z / Internal WKUP input WKUP input input fixed enabled enabled at 0 Maintain previous state Maintain Maintain previous previous state state Deep Standby RTC mode Return from or Deep Standby Stop Deep Standby mode state mode state GPIO selected Internal input fixed at 0 Hi-Z / Internal Output input fixed maintains at 0 previous state / Internal input fixed at 0 GPIO selected Hi-Z / Internal input fixed at 0 Maintain previous state Page 46 of 99 Pin status type CY9A1A0N Series Power-on Run Device mode reset or INITX or internal low-voltage input Sleep reset detection state mode state state state Function group Power Power supply Power supply stable supply unstable stable - INITX = 0 INITX = 1 INITX = 1 - Timer mode, RTC mode, or Stop mode state Power supply stable Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Setting disabled Setting disabled Setting disabled GPIO selected NMIX selected I J Resource other than above selected Hi-Z GPIO selected Hi-Z / Input enabled Hi-Z / Input enabled Analog input selected Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z Resource other than above selected Setting disabled Setting disabled GPIO selected Document Number: 002-05675 Rev. *E Setting disabled Maintain Maintain previous previous state state Maintain Maintain previous previous state state Hi-Z / Internal input fixed at 0 / Analog input enabled Power supply stable Power supply stable INITX = 1 SPL = 0 SPL = 1 Resource selected H Deep Standby RTC mode Return from or Deep Standby Stop Deep Standby mode state mode state Hi-Z / Internal input fixed at 0 / Analog input enabled Maintain Maintain previous previous state state INITX = 1 INITX = 1 SPL = 0 SPL = 1 GPIO selected GPIO selected Internal input fixed at 0 Hi-Z / Hi-Z / Internal Output Internal input input fixed maintains fixed at 0 at 0 previous Maintain state / previous state Internal input fixed at 0 Maintain previous state GPIO selected Hi-Z / WKUP input WKUP input Hi-Z / enabled enabled Internal input fixed at 0 Maintain previous state Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO selected GPIO selected Internal input fixed at 0 Hi-Z / Hi-Z / Internal Output Internal input input fixed maintains fixed at 0 at 0 previous Maintain state / previous state Internal input fixed at 0 Page 47 of 99 Pin status type CY9A1A0N Series Power-on Run Device mode reset or INITX or internal low-voltage input Sleep reset detection state mode state state state Function group Power Power supply Power supply stable supply unstable stable - Analog input selected Hi-Z External interrupt enabled K selected Resource other than above Setting selected disabled INITX = 0 INITX = 1 INITX = 1 Hi-Z / Hi-Z / Hi-Z / Internal Internal Internal input input fixed input fixed fixed at 0 at 0 / at 0 / / Analog Analog Analog input input input enabled enabled enabled Timer mode, RTC mode, or Stop mode state Power supply stable Power supply stable Power supply stable INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 SPL = 1 INITX = 1 - Hi-Z / Internal input fixed at 0 / Analog input enabled Setting disabled Maintain Maintain previous previous state state GPIO selected Analog input selected Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO selected Internal input fixed at 0 Hi-Z / Internal Output input fixed maintains at 0 previous state / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO selected Hi-Z / Internal input fixed at 0 Maintain previous state Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Hi-Z / Internal WKUP input WKUP input input fixed enabled enabled at 0 WKUP enabled L External interrupt enabled selected Resource Setting other than disabled above selected Hi-Z / Internal input fixed at 0 / Analog input enabled Maintain previous state Setting disabled Deep Standby RTC mode Return from or Deep Standby Stop Deep Standby mode state mode state Maintain previous state Setting disabled GPIO selected Document Number: 002-05675 Rev. *E Setting disabled Maintain Maintain previous previous state state GPIO selected Internal input fixed at 0 GPIO selected Hi-Z / Internal input Hi-Z / fixed at 0 Internal Output input fixed maintains at 0 previous Maintain state / previous state Internal input fixed at "0" Page 48 of 99 Pin status type CY9A1A0N Series Power-on Run Device mode reset or INITX or internal low-voltage input Sleep reset detection state mode state state state Function group Power Power supply Power supply stable supply unstable stable Sub crystal oscillator input pin Input enabled External sub clock Setting input disabled M selected GPIO selected Sub crystal oscillator output pin Setting disabled Hi-Z / Internal input fixed at 0 INITX = 0 INITX = 1 INITX = 1 - Input enabled Setting disabled Setting disabled Hi-Z / Internal input fixed at 0 Input enabled Setting disabled Setting disabled GPIO selected Setting disabled Setting disabled Setting disabled External interrupt enabled selected Setting disabled Setting disabled Setting disabled GPIO selected Hi-Z O Document Number: 002-05675 Rev. *E Maintain previous state Maintain previous state Hi-Z / Maintain Internal previous input fixed state at 0 N Hi-Z / Input enabled Input enabled Hi-Z / Input enabled Timer mode, RTC mode, or Stop mode state Deep Standby RTC mode Return from or Deep Standby Stop Deep Standby mode state mode state Power supply stable Power supply stable Power supply stable INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 SPL = 1 INITX = 1 - Input enabled Maintain previous state / When oscillation stops*2, output maintains previous state / Internal input fixed at 0 Output maintains previous state / Internal input fixed at 0 Maintain previous state / When oscillation stops*2, Hi-Z / Internal input fixed at 0 Maintain Maintain previous previous state state Maintain Maintain previous previous state state Input enabled Input enabled Input enabled Input enabled Hi-Z / Input enabled / When oscillation stops*2, Hi-Z / Internal input fixed at 0 Maintain previous state / When oscillation stops*2, output maintains previous state / Internal input fixed at 0 Hi-Z / Input enabled / When oscillation stops*2, Hi-Z / Internal input fixed at 0 Maintain previous state / When Return from Deep Standby STOP mode, GPIO is selected Hi-Z / Internal input fixed at 0 Output maintains Hi-Z / previous Maintain Internal input state / previous state fixed at 0 Internal input fixed at 0 Maintain previous state / When oscillation stops*2, Hi-Z / Internal input fixed at 0 Maintain previous state / When oscillation stops*2, Hi-Z / Internal input fixed at 0 Output maintains previous state / Internal input fixed at 0 GPIO Maintain selected / previous Internal input state fixed at 0 Output maintains Hi-Z / Internal previous input fixed state / Internal input at 0 fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state / When oscillation stops*2, Hi-Z / Internal input fixed at 0 Maintain previous state / When oscillation stops*2, Hi-Z / Internal input fixed at 0 Hi-Z / Maintain Internal input previous state fixed at 0 GPIO selected Hi-Z / Internal input fixed at 0 Maintain previous state Page 49 of 99 Pin status type CY9A1A0N Series P Power-on Run Device mode reset or INITX or internal low-voltage input Sleep reset detection state mode state state state Function group Power Power supply Power supply stable supply unstable stable Mode input pin Input enabled GPIO selected Setting disabled CEC enabled Setting disabled Resource other than above Q selected Hi-Z GPIO selected CEC enabled Setting disabled INITX = 0 INITX = 1 INITX = 1 Input Input Input enabled enabled enabled Maintain Setting Setting previous disabled disabled state Maintain Setting Setting previous disabled disabled state Timer mode, RTC mode, or Stop mode state Power supply stable Hi-Z / Input enabled Hi-Z / Input enabled Maintain Maintain previous previous state state Setting disabled Setting disabled Maintain Maintain previous previous state state Hi-Z GPIO selected Setting disabled Setting disabled Document Number: 002-05675 Rev. *E Hi-Z / Input enabled INITX = 1 SPL = 0 SPL = 1 Input Input enabled enabled Maintain Hi-Z / input previous enabled state Maintain Maintain previous previous state state GPIO selected Internal input fixed at 0 Hi-Z / Hi-Z / Internal Output Internal input input fixed maintains fixed at 0 at 0 previous state / Internal input fixed at 0 Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state Maintain Maintain previous previous state state Hi-Z / Input enabled Power supply stable INITX = 1 SPL = 0 SPL = 1 Input Input enabled enabled Maintain Hi-Z / input previous enabled state Maintain Maintain previous previous state state WKUP enabled Setting External disabled interrupt enabled R selected Resource other than above selected Deep Standby RTC mode Return from or Deep Standby Stop Deep Standby mode state mode state Maintain previous state Maintain previous state Power supply stable INITX = 1 Input enabled Maintain previous state Maintain previous state GPIO selected Maintain previous state Maintain previous state Hi-Z / WKUP input WKUP input enabled enabled GPIO selected Internal input fixed at 0 Hi-Z / Internal Output input fixed maintains at 0 previous state / Internal input fixed at 0 GPIO selected Hi-Z / Internal input fixed at 0 Maintain previous state Page 50 of 99 Pin status type CY9A1A0N Series Power-on Run Device mode reset or INITX or internal low-voltage input Sleep reset detection state mode state state state Function group Power Power supply Power supply stable supply unstable stable - Analog output selected External interrupt enabled selected Resource S other than above selected Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled Hi-Z GPIO selected Analog Setting output disabled selected Resource other than above T selected Hi-Z GPIO selected INITX = 0 INITX = 1 INITX = 1 - Hi-Z / Input enabled Hi-Z / Input enabled Setting disabled Setting disabled Hi-Z / Input enabled Hi-Z / Input enabled Timer mode, RTC mode, or Stop mode state Deep Standby RTC mode Return from or Deep Standby Stop Deep Standby mode state mode state Power supply stable Power supply stable Power supply stable INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 SPL = 1 INITX = 1 - *3 *4 Maintain previous state Maintain previous Maintain state previous state *3 Maintain previous Maintain state previous state GPIO selected Internal input fixed at 0 GPIO selected Hi-Z / Internal input fixed at 0 Hi-Z / Internal Output input fixed maintains at 0 previous state / Internal input fixed at 0 *4 GPIO selected Internal input fixed at 0 Maintain previous state GPIO selected Hi-Z / Internal input Hi-Z / fixed at 0 Internal Output input fixed maintains at 0 previous Maintain state / previous state Internal input fixed at 0 *1: Oscillation is stopped at Sub run mode, Low-speed CR Run mode, Sub Sleep mode, Low-speed CR Sleep mode, Sub Timer mode, Low-speed CR Timer mode, RTC mode, Stop mode, Deep Standby RTC mode, and Deep Standby Stop mode. *2: Oscillation is stopped at Stop mode and Deep Standby Stop mode. *3: Maintain previous state at Timer mode. GPIO selected Internal input fixed at 0 at RTC mode, Stop mode. *4: Maintain previous state at Timer mode. Hi-Z/Internal input fixed at 0 at RTC mode, Stop mode. Document Number: 002-05675 Rev. *E Page 51 of 99 CY9A1A0N Series 12. Electrical Characteristics 12.1 Absolute Maximum Ratings Parameter Symbol Power supply voltage*1,*2 Analog power supply voltage*1,*3 Analog reference voltage*1,*3 VCC AVCC AVRH Input voltage*1 VI Rating Min Max VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS + 6.5 VSS + 6.5 VSS + 6.5 VCC + 0.5 (≤ 6.5 V) VSS + 6.5 AVCC + 0.5 (≤ 6.5 V) VCC + 0.5 (≤ 6.5 V) 10 4 100 50 - 10 -4 - 100 - 50 400 + 150 VSS - 0.5 VSS - 0.5 Analog pin input voltage*1 VIA VSS - 0.5 Output voltage*1 VO VSS - 0.5 current*4 L level maximum output L level average output current*5 L level total maximum output current L level total average output current*6 H level maximum output current*4 H level average output current*5 H level total maximum output current H level total average output current*6 Power consumption Storage temperature IOL IOLAV ∑IOL ∑IOLAV IOH IOHAV ∑IOH ∑IOHAV PD TSTG - 55 Unit Remarks V V V V V 5V tolerant V V mA mA mA mA mA mA mA mA mW C *1: These parameters are based on the condition that VSS = AVSS = 0 V. *2: VCC must not drop below VSS - 0.5 V. *3: Be careful not to exceed VCC + 0.5 V, for example, when the power is turned on. *4: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *5: The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100 ms period. *6: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100 ms. WARNING: − Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. Document Number: 002-05675 Rev. *E Page 52 of 99 CY9A1A0N Series 12.2 Recommended Operating Conditions (VSS = AVSS = 0.0V) Parameter Symbol Conditions Value Unit Min Max 5.5 5.5 V V AVCC V 10 μF + 85 C Power supply voltage Analog power supply voltage VCC AVCC - Analog reference voltage AVRH - Smoothing capacitor LQD064, LQG064, Operating LQH080, Temperature LQJ080, LQI100, PQH100 CS - 1.8 1.8 2.7 AVCC 1 TA - - 40 Remarks AVCC = VCC AVCC ≥ 2.7 V AVCC < 2.7 V For built-in Regulator * *: See C Pin in Handling Devices for the smoothing capacitor. WARNING: − The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. Document Number: 002-05675 Rev. *E Page 53 of 99 CY9A1A0N Series 12.3 DC Characteristics 12.3.1 Current Rating (VCC = AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0 V, TA = - 40C to + 85C) Parameter Symbol Pin name Conditions PLL Run mode High-spee d CR Run mode ICC Sub Run mode Power supply current VCC ICCS Low-speed CR Run mode PLL Sleep mode High-spee d CR Sleep mode Sub Sleep mode Low-speed CR Sleep mode CPU: 20 MHz, Peripheral: 20 MHz, Flash memory 0 Wait, FRWTR.RWT = 00, FSYNDN.SD = 000 CPU: 20 MHz, Peripheral: clock stopped, NOP operation Value Typ*3 Max*4 Unit Remarks 19 24 mA *1, *5 9.5 12.5 mA *1, *5 4.5 5 mA *1 0.25 0.55 mA *1, *6 0.3 0.95 mA *1 Peripheral: 20 MHz 8 10.5 mA *1, *5 Peripheral: 4 MHz*2 2 2.5 mA *1 Peripheral: 32 kHz 0.2 0.45 mA *1, *6 Peripheral: 100 kHz 0.25 0.65 mA *1 CPU/Peripheral: 4 MHz*2 Flash memory 0 Wait FRWTR.RWT = 00 FSYNDN.SD = 000 CPU/Peripheral: 32 kHz, Flash memory 0 Wait, FRWTR.RWT = 00, FSYNDN.SD = 000 CPU/Peripheral: 100 kHz, Flash memory 0 Wait, FRWTR.RWT = 00, FSYNDN.SD = 000 *1: When all ports are fixed. *2: When setting it to 4 MHz by trimming. *3: TA=+25°C, VCC=3.3 V *4: TA=+85°C, VCC=5.5 V *5: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit) *6: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit) Document Number: 002-05675 Rev. *E Page 54 of 99 CY9A1A0N Series Parameter Pin name Symbol Conditions Main Timer mode ICCT Sub Timer mode ICCR Power supply current RTC mode VCC ICCH ICCRD ICCHD Stop mode Deep Standby RTC mode Deep Standby Stop mode TA = + 25°C, When LVD is off TA = + 85°C, When LVD is off TA = + 25°C, When LVD is off TA = + 85°C, When LVD is off TA = + 25C, When LVD is off TA = + 85C, When LVD is off TA = + 25C, When LVD is off TA = + 85C, When LVD is off TA = + 25C, When LVD is off TA = + 85C, When LVD is off TA = + 25C, When LVD is off TA = + 85C, When LVD is off Value Unit Remarks Typ*2 Max*3 0.9 3.3 mA *1, *4 1.5 3.5 mA *1, *4 7.5 60 μA *1, *5 16 150 μA *1, *5 1.5 6.5 μA *1, *5 6 79 μA *1, *5 0.6 5 μA *1 4.2 77 μA *1 1.3 4.5 μA *1, *5 3 22 μA *1, *5 0.4 3 μA *1 1.4 20 μA *1 *1: When all ports are fixed. *2: VCC=3.3 V *3: VCC=5.5 V *4: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit) *5: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit) Document Number: 002-05675 Rev. *E Page 55 of 99 CY9A1A0N Series Low Voltage Detection Current (VCC = AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0 V, TA = - 40C to + 85C) Parameter Low-voltage detection circuit (LVD) power supply current Symbol ICCLVD Pin name VCC Value Conditions For occurrence of reset or for occurrence of interrupt in normal mode operation For occurrence of reset and for occurrence of interrupt in normal mode operation For occurrence of interrupt in low-power mode operation Typ* Max 10 20 Unit Remarks μA When not detected 14 30 μA 0.3 2 μA When not detected *: When VCC = 3.3 V Flash Memory Current (VCC = 1.8 V to 5.5 V, VSS = 0 V, TA = - 40°C to + 85°C) Parameter Flash memory write/erase current Pin name Symbol ICCFLASH VCC Conditions At Write/Erase Value Typ Max 10.8 11.9 Unit Remarks mA A/D Converter Current Parameter Power supply current Reference power supply current Pin name Symbol ICCAD ICCAVRH AVCC AVRH Conditions (VCC = AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0 V, TA = - 40°C to + 85°C) Value Unit Remarks Typ Max At 1unit operation 1.4 2.5 mA At stop 0.1 0.35 μA At 1unit operation AVRH=5.5 V 0.5 1.5 mA At stop 0.1 0.3 μA D/A Converter Current Parameter Power supply current Pin name Symbol IDDA AVCC IDSA Conditions At D/A 1ch. operation AVCC=3.3 V At D/A 1ch. operation AVCC=5.0 V At D/A stop (VCC = AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0 V, TA = - 40°C to + 85°C) Value Unit Remarks Typ Max 314 440 μA *1, *2 476 670 μA *1, *2 - 1.0 μA *1 *1: No-load *2: Generates the max current by the CODE about 0x200 Document Number: 002-05675 Rev. *E Page 56 of 99 CY9A1A0N Series 12.3.2 Pin Characteristics (VCC = AVCC = 1.8V to 5.5V, VSS = AVSS = 0V, TA = - 40C to + 85C) Parameter H level input voltage (hysteresis input) L level input voltage (hysteresis input) H level output voltage L level output voltage Symbol VIHS VILS VOH VOL MD0, MD1, PE0, PE2, PE3, P46, P47, P3A, P3B, P3C, P3D, P3E, P3F, INITX P0A, P0B, P0C, P4C, P60, P80, P81, P82 CMOS hysteresis input pins other than the above MD0, MD1, PE0, PE2, PE3, P46, P47, INITX CMOS hysteresis input pins other than the above Pxx Pxx Max - VCC × 0.8 - VCC + 0.3 V - VCC × 0.7 - VSS + 5.5 V - VCC × 0.7 - VCC + 0.3 V - VSS - 0.3 - VCC × 0.2 V - VSS - 0.3 - VCC × 0.3 V VCC - 0.5 - VCC V VSS - 0.4 V -5 - +5 - - + 1.8 VCC ≥ 4.5 V 25 50 100 VCC  4.5 V 40 100 400 - 5 15 Conditions VCC ≥ 4.5 V, IOH = - 4 mA VCC < 4.5 V, IOH = - 1 mA VCC ≥ 4.5 V, IOL = 4 mA VCC < 4.5 V, IOL = 2 mA - VCC = AVCC = AVRH = VSS = AVSS = 0.0 V Input leak current IIL CEC0, CEC1 Pull-up resistor value RPU Pull-up pin CIN Other than VCC, VSS, AVCC, AVSS, AVRH Input capacitance Min Value Typ Pin name Document Number: 002-05675 Rev. *E - Unit Remarks 5V tolerant μA kΩ pF Page 57 of 99 CY9A1A0N Series 12.4 AC Characteristics 12.4.1 Main Clock Input Characteristics (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Pin name Symbol Conditions fCH Input clock cycle tCYLH Input clock pulse width - Input clock rising time and falling time Internal operating clock*1 frequency Internal operating clock*1 cycle time tCF, tCR fCM fCC fCP0 fCP1 fCP2 tCYCC tCYCP0 tCYCP1 tCYCP2 Max Unit Remarks 4 4 4 4 50 62.5 20 4 20 16 250 250 MHz MHz MHz MHz ns ns 45 55 % - - 5 ns - - - 20 20 20 20 20 MHz MHz MHz MHz MHz When using external clock When using external clock Master clock Base clock (HCLK/FCLK) APB0 bus clock*2 APB1 bus clock*2 APB2 bus clock*2 - - 50 - ns Base clock (HCLK/FCLK) - - 50 - ns APB0 bus clock*2 - - 50 - ns APB1 bus clock*2 - - 50 - ns APB2 bus clock*2 VCC ≥ 2.0 V Input frequency Value Min X0, X1 VCC  2.0 V VCC ≥ 4.5 V VCC  4.5 V VCC ≥ 4.5 V VCC  4.5 V PWH/tCYLH, PWL/tCYLH When crystal oscillator is connected When using external clock When using external clock *1: For more information about each internal operating clock, see Chapter 2-1: Clock in FM3 Family Peripheral Manual. *2: For about each APB bus which each peripheral is connected to, see Block Diagram in this data sheet. X0 Document Number: 002-05675 Rev. *E Page 58 of 99 CY9A1A0N Series 12.4.2 Sub Clock Input Characteristics (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Input frequency fCL Input clock cycle tCYLL Input clock pulse width - Pin name X0A, X1A Conditions Value Unit Remarks Min Typ Max - - 32.768 - kHz - 32 - 100 kHz When crystal oscillator is connected When using external clock - 10 - 31.25 μs When using external clock PWH/tCYLL, PWL/tCYLL 45 - 55 % When using external clock X0A 12.4.3 Built-in CR Oscillation Characteristics Built-in High-speed CR (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Conditions VCC ≥ 2.2 V Clock frequency fCRH VCC < 2.2 V Frequency stabilization time tCRWT - Value Min Typ Max TA = + 25C 3.92 4 4.08 TA = - 40C to + 85C 3.8 4 4.2 TA = - 40C to + 85C 2.3 - 7.03 TA = + 25C 3.4 4 4.6 TA = - 40C to + 85C 3.16 4 4.84 TA = - 40C to + 85C 2.3 - 7.03 - - 10 Unit Remarks When trimming*1 MHz When not trimming When trimming*1 MHz μs When not trimming *2 *1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming. *2: This is the time to stabilize the frequency of High-speed CR clock after setting trimming value. This period is able to use High-speed CR clock as source clock. Document Number: 002-05675 Rev. *E Page 59 of 99 CY9A1A0N Series Built-in Low-speed CR (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Clock frequency 12.4.4 fCRL Conditions - Value Min Typ Max 50 100 150 Unit Remarks kHz Operating Conditions of Main PLL (In the case of using main clock for input of PLL) (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter PLL oscillation stabilization wait time*1 (LOCK UP time) PLL input clock frequency PLL multiplication rate PLL macro oscillation clock frequency Main PLL clock frequency*2 Symbol Value Unit Remarks Min Typ Max tLOCK 200 - - μs fPLLI fPLLO fCLKPLL 4 1 10 - - 20 5 20 20 MHz multiplier MHz MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual. 12.4.5 Operating Conditions of Main PLL (In the case of using the built-in High-speed CR for the input clock of the Main PLL) (VCC = 2.2V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter PLL oscillation stabilization wait time*1 (LOCK UP time) PLL input clock frequency PLL multiplication rate PLL macro oscillation clock frequency Main PLL clock frequency*2 Symbol Value Unit Min Typ Max tLOCK 200 - - μs fPLLI fPLLO fCLKPLL 3.8 3 11.4 - 4 - 4.2 4 16.8 16.8 MHz multiplier MHz MHz Remarks *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual. Note: − Make sure to input to the Main PLL source clock, the High-speed CR clock (CLKHC) that the frequency has been trimmed. When setting PLL multiple rate, please take the accuracy of the built-in High-speed CR clock into account and prevent the master clock from exceeding the maximum frequency. Document Number: 002-05675 Rev. *E Page 60 of 99 CY9A1A0N Series Main PLL connection Main clock (CLKMO) PLL input clock K divider High-speed CR clock (CLKHC) PLL macro oscillation clock Main PLL M divider Main PLL clock (CLKPLL) N divider 12.4.6 Reset Input Characteristics (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Reset input time 12.4.7 Pin name Symbol tINITX INITX Conditions - Value Min Max 500 1.5 1.5 - Unit ns ms ms Remarks When RTC mode or Stop mode When Deep Standby mode Power-on Reset Timing (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Power supply rising time dV/dt Power supply shut down time tOFF Reset release voltage VDETH Pin name VCC Value Unit Remarks Min Typ Max 0.1 - - V/ms 1 - - ms 1.44 1.60 1.76 V When voltage rises 1.39 1.55 1.71 V When voltage drops Reset detection voltage VDETL Time until releasing Power-on reset tPRT 0.46 - 11.4 ms dV/dt ≥ 0.1mV/μs Reset detection delay time tOFFD - - 0.4 ms dV/dt ≥ -0.04mV/μs Document Number: 002-05675 Rev. *E Page 61 of 99 CY9A1A0N Series VDETH VDETL VCC dV 0.2V dt 0.2V tOFF tPRT Internal reset tOFFD Reset active Release CPU Operation 12.4.8 Reset active start Base Timer Input Timing Timer input timing (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Input pulse width Symbol tTIWH, tTIWL Pin name Conditions TIOAn/TIOBn (when using as ECK, TIN) - tTIWH Value Min Max 2tCYCP - Unit Remarks ns tTIWL ECK TIN Document Number: 002-05675 Rev. *E VIHS VIHS VILS VILS Page 62 of 99 CY9A1A0N Series Trigger input timing (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Input pulse width Symbol tTRGH, tTRGL Pin name Conditions TIOAn/TIOBn (when using as TGIN) - tTRGH TGIN VIHS Value Min Max 2tCYCP - Unit Remarks ns tTRGL VIHS VILS VILS Note: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which the Base Timer is connected to, see Block Diagram in this data sheet. Document Number: 002-05675 Rev. *E Page 63 of 99 CY9A1A0N Series 12.4.9 CSIO/UART Timing CSIO (SPI = 0, SCINV = 0) (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Pin name Conditions Baud rate Serial clock cycle time - - - tSCYC SCK   SOT delay time tSLOVI SIN  SCK  setup time tIVSHI SCK   SIN hold time Serial clock L pulse width Serial clock H pulse width tSHIXI SCKx, SOTx SCKx, SINx SCKx, SINx 2.7 V ≤ VCC 4.5 V Min Max 5 Min - Max 5 4tCYCP - 4tCYCP -40 +40 75 VCC ≥ 4.5 V Unit Min - Max 5 Mbps - 4tCYCP - ns -30 +30 -20 +20 ns - 50 - 30 - ns 0 - 0 - 0 - ns Master mode tSLSH SCKx 2tCYCP - 10 - 2tCYCP - 10 - 2tCYCP - 10 - ns tSHSL SCKx tCYCP + 10 - tCYCP + 10 - tCYCP + 10 - ns - 75 - 50 - 30 ns 10 - 10 - 10 - ns 20 - 20 - 20 - ns - 5 5 - 5 5 - 5 5 ns ns SCK   SOT delay time tSLOVE SIN  SCK  setup time tIVSHE SCK   SIN hold time SCK falling time SCK rising time SCKx VCC  2.7 V tSHIXE tF tR SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx Slave mode Notes: − The above characteristics apply to clock synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 50 pF. Document Number: 002-05675 Rev. *E Page 64 of 99 CY9A1A0N Series tSCYC VOH SCK VOH VOL tSHOVI VOH SOT VOL tIVSLI SIN tSLIXI VIH VIH VIL VIL Master mode tSHSL SCK tSLSH VIH VIH VIL tR tF VIL VIL tSHOVE SOT VOH VOL tIVSLE SIN VIH VIL tSLIXE VIH VIL Slave mode Document Number: 002-05675 Rev. *E Page 65 of 99 CY9A1A0N Series CSIO (SPI = 0, SCINV = 1) (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Baud rate Serial clock cycle time Symbol tSCYC tSHOVI SIN  SCK  setup time tIVSLI tSLIXI - - SCKx SCKx, SOTx SCKx, SINx SCKx, SINx VCC  2.7 V 2.7 V ≤ VCC  4.5 V Min Max 5 Min - Max 5 4tCYCP - 4tCYCP -40 +40 75 VCC ≥ 4.5 V Unit Min - Max 5 Mbps - 4tCYCP - ns -30 +30 -20 +20 ns - 50 - 30 - ns 0 - 0 - 0 - ns Master mode tSLSH SCKx 2tCYCP - 10 - 2tCYCP - 10 - 2tCYCP - 10 - ns tSHSL SCKx tCYCP + 10 - tCYCP + 10 - tCYCP + 10 - ns - 75 - 50 - 30 ns 10 - 10 - 10 - ns 20 - 20 - 20 - ns - 5 5 - 5 5 - 5 5 ns ns SCK   SOT delay time tSHOVE SIN  SCK  setup time tIVSLE SCK   SIN hold time SCK falling time SCK rising time Conditions - SCK   SOT delay time SCK   SIN hold time Serial clock L pulse width Serial clock H pulse width Pin name tSLIXE tF tR SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx Slave mode Notes: − The above characteristics apply to clock synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 50 pF. Document Number: 002-05675 Rev. *E Page 66 of 99 CY9A1A0N Series tSCYC VOH SCK VOH VOL tSHOVI VOH SOT VOL tIVSLI SIN tSLIXI VIH VIH VIL VIL Master mode tSHSL SCK tSLSH VIH VIH VIL tR tF VIL VIL tSHOVE SOT VOH VOL tIVSLE SIN VIH VIL tSLIXE VIH VIL Slave mode Document Number: 002-05675 Rev. *E Page 67 of 99 CY9A1A0N Series CSIO (SPI = 1, SCINV = 0) (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Baud rate Serial clock cycle time Symbol tSCYC SCK   SOT delay time tSHOVI SIN  SCK  setup time tIVSLI SCK   SIN hold time tSLIXI SOT  SCK  delay time Serial clock L pulse width Serial clock H pulse width tSOVLI Conditions - - SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx, SOTx Master mode VCC  2.7 V 2.7 V ≤ VCC  4.5 V Min Max 5 Min - Max 5 4tCYCP - 4tCYCP -40 +40 75 VCC ≥ 4.5 V Unit Min - Max 5 Mbps - 4tCYCP - ns -30 +30 -20 +20 ns - 50 - 30 - ns 0 - 0 - 0 - ns 2tCYCP - 30 - 2tCYCP - 30 - 2tCYCP - 30 - ns tSLSH SCKx 2tCYCP - 10 - 2tCYCP - 10 - 2tCYCP - 10 - ns tSHSL SCKx tCYCP + 10 - tCYCP + 10 - tCYCP + 10 - ns - 75 - 50 - 30 ns 10 - 10 - 10 - ns 20 - 20 - 20 - ns - 5 5 - 5 5 - 5 5 ns ns SCK   SOT delay time tSHOVE SIN  SCK  setup time tIVSLE SCK   SIN hold time SCK falling time SCK rising time Pin name tSLIXE tF tR SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx Slave mode Notes: − The above characteristics apply to clock synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 50 pF. Document Number: 002-05675 Rev. *E Page 68 of 99 CY9A1A0N Series tSCYC VOH SCK VOL SOT VOH VOL VOH VOL tIVSLI tSLIXI VIH VIL SIN VOL tSHOVI tSOVLI VIH VIL Master mode tSLSH SCK VIH tR VOH VOL tIVSLE SIN VIL tF * SOT VIL tSHSL VIH VIH tSHOVE VOH VOL tSLIXE VIH VIL VIH VIL Slave mode *: Changes when writing to TDR register Document Number: 002-05675 Rev. *E Page 69 of 99 CY9A1A0N Series CSIO (SPI = 1, SCINV = 1) (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Baud rate Serial clock cycle time Symbol Pin name Conditions - - - VCC  2.7 V Min - Max 5 2.7 V ≤ VCC  4.5 V Min Max 5 VCC ≥ 4.5 V Unit Min - Max 5 Mbps tSCYC SCKx 4tCYCP - 4tCYCP - 4tCYCP - ns SCK   SOT delay time tSLOVI SCKx, SOTx -40 +40 -30 +30 -20 +20 ns SIN  SCK  setup time tIVSHI 75 - 50 - 30 - ns SCK  SIN hold time tSHIXI 0 - 0 - 0 - ns 2tCYCP - 30 - 2tCYCP - 30 - 2tCYCP - 30 - ns SOT  SCK  delay time Serial clock L pulse width Serial clock H pulse width tSOVHI Master mode tSLSH SCKx 2tCYCP - 10 - 2tCYCP - 10 - 2tCYCP - 10 - ns tSHSL SCKx tCYCP + 10 - tCYCP + 10 - tCYCP + 10 - ns - 75 - 50 - 30 ns 10 - 10 - 10 - ns 20 - 20 - 20 - ns - 5 5 - 5 5 - 5 5 ns ns SCK   SOT delay time tSLOVE SIN  SCK  setup time tIVSHE SCK   SIN hold time SCK falling time SCK rising time SCKx, SINx SCKx, SINx SCKx, SOTx tSHIXE tF tR SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx Slave mode Notes: − The above characteristics apply to clock synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 50 pF. Document Number: 002-05675 Rev. *E Page 70 of 99 CY9A1A0N Series tSCYC VOH SCK tSOVHI tSLOVI VOH VOL SOT VOH VOL tSHIXI tIVSHI VIH VIL SIN VOH VOL VIH VIL Master mode tR tF tSHSL SCK VIH VIH VIL tSLSH VIL VIL tSLOVE VOH VOL SOT VOH VOL tIVSHE tSHIXE VIH VIL SIN VIH VIL Slave mode UART external clock input (EXT = 1) (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Serial clock L pulse width Serial clock H pulse width SCK falling time SCK rising time Symbol tSLSH tSHSL tF tR Conditions CL = 50 pF Min Max tCYCP + 10 tCYCP + 10 - 5 5 Unit Remarks ns ns ns ns tF tR tSHSL SCK V IL Document Number: 002-05675 Rev. *E Value V IH t SLSH V IH V IL V IL V IH Page 71 of 99 CY9A1A0N Series 12.4.10 External Input Timing (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Pin name Value Min Conditions Max Unit ADTG Input pulse width tINH, tINL FRCKx ICxx DTTIxX IGTRG INTxx, NMIX WKUPx Remarks A/D converter trigger input - *2 *3 *4 2tCYCP*1 - ns 2tCYCP*1 2tCYCP*1 2tCYCP + 100*1 500 500 - ns ns ns ns ns Free-run timer input clock Input capture Waveform generator PPG IGBT mode External interrupt, NMI Deep standby wake up *1: tCYCP indicates the APB bus clock cycle time. About the APB bus number which the A/D converter, Multi-function Timer, PPG, External interrupt, Deep Standby mode Controller are connected to, see Block Diagram in this data sheet. *2: When in Run mode, in Sleep mode. *3: When in Timer mode, in RTC mode, in Stop mode. *4: When in Deep Standby RTC mode, in Deep Standby Stop mode. Document Number: 002-05675 Rev. *E Page 72 of 99 CY9A1A0N Series 12.4.11 I2C Timing (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter SCL clock frequency (Repeated) START condition hold time SDA   SCL  SCL clock L width SCL clock H width (Repeated) START condition setup time SCL   SDA  Data hold time SCL   SDA   Data setup time SDA    SCL  STOP condition setup time SCL   SDA  Bus free time between STOP condition and START condition Noise filter Symbol Conditions fSCL Standard-mode Min Max 0 100 Fast-mode Min Max 0 400 Unit kHz tHDSTA 4.0 - 0.6 - μs tLOW tHIGH 4.7 4.0 - 1.3 0.6 - μs μs 4.7 - 0.6 - μs 0 3.45*2 0 0.9*3 μs tSUDAT 250 - 100 - ns tSUSTO 4.0 - 0.6 - μs tBUF 4.7 - 1.3 - μs 2 tCYCP*4 - 2 tCYCP*4 - ns tSUSTA tHDDAT tSP CL = 50 pF, R = (VP/IOL)*1 - Remarks *1: R and CL represent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively. VP indicates the power supply voltage of the pull-up resistor and IOL indicates VOL guaranteed current. *2: The maximum tHDDAT must satisfy that it does not extend at least L period (tLOW) of device's SCL signal. *3: A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of tSUDAT ≥ 250 ns. *4: tCYCP is the APB bus clock cycle time. About the APB bus number which I2C is connected to, see Block Diagram in this data sheet. To use Standard-mode, set the APB bus clock at 2 MHz or more. To use Fast-mode, set the APB bus clock at 8 MHz or more. SDA SCL Document Number: 002-05675 Rev. *E Page 73 of 99 CY9A1A0N Series 12.4.12 JTAG Timing (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Pin name TMS,TDI setup time tJTAGS TCK, TMS,TDI TMS,TDI hold time tJTAGH TCK, TMS,TDI TDO delay time tJTAGD TCK, TDO Conditions VCC ≥ 4.5 V Min Value Max Unit 15 - ns 15 - ns VCC ≥ 4.5 V - 30 2.7 V ≤VCC  4.5 V VCC  2.7 V - 45 - 60 VCC  4.5 V VCC ≥ 4.5 V VCC  4.5 V Remarks ns Note: − When the external load capacitance CL = 50 pF. TCK TMS/TDI TDO Document Number: 002-05675 Rev. *E Page 74 of 99 CY9A1A0N Series 12.5 12-bit A/D Converter Electrical Characteristics for the A/D Converter (VCC = AVCC = 1.8V to 5.5V, VSS = AVSS = 0V, TA = - 40C to + 85C) Parameter Pin name Symbol Min 1.0 4.0 0.3 1.2 50 Value Typ ± 2.5 ± 3.5 ± 1.8 ± 2.7 ±9 AVRH ± 9 Max 12 ± 3.0 ± 4.0 ± 1.9 ± 2.9 ± 20 AVRH ± 20 - - μs - 10 μs - 1000 ns Unit bit LSB LSB LSB LSB mV mV Resolution - - Integral Nonlinearity INL - Differential Nonlinearity DNL - Zero transition voltage Full-scale transition voltage VZT VFST ANxx ANxx Conversion time*1 - - Sampling time*2 tS - Compare clock cycle*3 tCCK - Period of operation enable state transitions Analog input capacity tSTT - - - 1 μs CAIN - - - pF LSB 200 Analog input resistor RAIN - - - Interchannel disparity Analog port input leak current Analog input voltage - - - - 15 0.9 1.6 4.0 4 - ANxx - - 0.3 μA - ANxx - AVRH V Reference voltage - AVRH AVSS 2.7 AVCC - AVCC V kΩ Remarks AVCC ≥ 2.7 V AVCC < 2.7 V AVCC ≥ 2.7 V AVCC < 2.7 V AVCC ≥ 2.7 V AVCC < 2.7 V AVCC ≥ 2.7 V AVCC < 2.7 V AVCC ≥ 2.7 V AVCC < 2.7 V AVCC ≥ 4.5 V 2.7 V ≤ AVCC < 4.5 V AVCC < 2.7 V AVCC ≥ 2.7 V AVCC < 2.7 V *1: The conversion time is the value of sampling time (tS) + compare time (tC). The condition of the minimum conversion time is the following. AVCC ≥ 2.7 V, HCLK=20 MHz sampling time: 0.3 μs, compare time: 0.7 μs AVCC < 2.7 V, HCLK=20 MHz sampling time: 1.2 μs, compare time: 2.8 μs Ensure that it satisfies the value of the sampling time (tS) and compare clock cycle (tCCK). For setting*4 of the sampling time and compare clock cycle, see Chapter 1-1: A/D Converter in FM3 Family Peripheral Manual Analog Macro Part. The register settings of the A/D Converter are reflected in the operation according to the APB bus clock timing. For the number of the APB bus to which the A/D Converter is connected, see Block Diagram. The Base clock (HCLK) is used to generate the sampling time and the compare clock cycle. *2: A necessary sampling time changes by external impedance. Ensure to set the sampling time to satisfy (Equation 1). *3: The compare time (tC) is the value of (Equation 2). Document Number: 002-05675 Rev. *E Page 75 of 99 CY9A1A0N Series ANxx Analog input pin Analog Signal source REXT Comparator RAIN CAIN (Equation 1) tS ≥ ( RAIN + REXT ) × CAIN × 9 tS: Sampling time RAIN: input resistor of A/D = 0.9 kΩ at 4.5 V ≤ AVCC ≤ 5.5 V input resistor of A/D = 1.6 kΩ at 2.7 V ≤ AVCC < 4.5 V input resistor of A/D = 4.0 kΩ at 1.8 V ≤ AVCC < 2.7 V CAIN: input capacity of A/D = 15 pF at 1.8 V ≤ AVCC ≤ 5.5 V REXT: Output impedance of external circuit (Equation 2) tC = tCCK × 14 tC: Compare time tCCK: Compare clock cycle Document Number: 002-05675 Rev. *E Page 76 of 99 CY9A1A0N Series Definition of 12-bit A/D Converter Terms • Resolution: • Integral Nonlinearity: • Differential Nonlinearity: Analog variation that is recognized by an A/D converter. Deviation of the line between the zero-transition point (0b000000000000←→0b000000000001) and the full-scale transition point (0b111111111110←→0b111111111111) from the actual conversion characteristics. Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB. Integral Nonlinearity 0xFFF Actual conversion characteristics 0xFFE 0x(N+1) {1 LSB(N-1) + VZT} VFST VNT 0x004 (Actuallymeasured value) (Actually-measured value) 0x003 Digital output Digital output 0xFFD Differential Nonlinearity Actual conversion characteristics Ideal characteristics 0x002 0x001 0xN Actual conversion characteristics Ideal characteristics VNT Actual conversion characteristics AVRH AVSS AVRH Analog input Integral Nonlinearity of digital output N = Differential Nonlinearity of digital output N = 1LSB = N: VZT: VFST: VNT: (Actually-measured value) (Actually-measured value) 0x(N-2) VZT (Actually-measured value) AVSS V(N+1)T 0x(N-1) Analog input VNT - {1LSB × (N - 1) + VZT} 1LSB V(N + 1) T - VNT 1LSB [LSB] - 1 [LSB] VFST - VZT 4094 A/D converter digital output value. Voltage at which the digital output changes from 0x000 to 0x001. Voltage at which the digital output changes from 0xFFE to 0xFFF. Voltage at which the digital output changes from 0x(N − 1) to 0xN. Document Number: 002-05675 Rev. *E Page 77 of 99 CY9A1A0N Series 12.6 10-bit D/A Converter Electrical Characteristics for the D/A Converter (VCC = AVCC = 1.8V to 5.5V, VSS = AVSS = 0V, TA = - 40C to + 85C) Parameter Resolution Symbol Integral Nonlinearity Differential Nonlinearity tC20 tC100 INL DNL Output Voltage offset VOFF Analog output impedance RO Output undefined period tR Conversion time Pin name DAx Min 0.37 1.87 -4.0 -0.9 -50.0 2.45 5.0 Value Typ 0.53 2.67 3.50 9.0 Max 10 0.69 3.47 +4.0 +0.9 10.0 +5.5 5.5 - - - 250 Unit bit μs μs LSB LSB mV mV kΩ MΩ Remarks Load 20 pF Load 100 pF * * Code is 0x000 Code is 0x3FF D/A operation D/A stop ns *: No-load Document Number: 002-05675 Rev. *E Page 78 of 99 CY9A1A0N Series 12.7 Low-Voltage Detection Characteristics 12.7.1 Low-Voltage Detection Reset (TA = - 40C to + 85C) Parameter Symbol Conditions Min 1.43 1.53 1.80 1.90 Value Typ 1.53 1.63 1.93 2.03 Max 1.63 1.73 2.06 2.16 Unit V V V V Detected voltage Released voltage Detected voltage Released voltage VDLR VDHR VDLR VDHR LVD stabilization wait time tLVDRW - - - 633 × tCYCP* μs Detection delay time tLVDRD dV/dt ≥ -4mV/μs - - 60 μs SVHR = 0001 SVHR = 0100 Remarks When voltage drops When voltage rises When voltage drops When voltage rises *: tCYCP indicates the APB2 bus clock cycle time. Document Number: 002-05675 Rev. *E Page 79 of 99 CY9A1A0N Series 12.7.2 Interrupt of Low-Voltage Detection Normal mode (TA = - 40C to + 85C) Parameter Symbol Conditions Min 1.87 1.97 1.96 2.06 2.05 2.15 2.15 2.25 2.24 2.34 2.33 2.43 2.43 2.53 2.61 2.71 2.80 2.90 2.99 3.09 3.36 3.46 3.45 3.55 3.73 3.83 3.83 3.93 3.92 4.02 Value Typ 2.00 2.10 2.10 2.20 2.20 2.30 2.30 2.40 2.40 2.50 2.50 2.60 2.60 2.70 2.80 2.90 3.00 3.10 3.20 3.30 3.60 3.70 3.70 3.80 4.00 4.10 4.10 4.20 4.20 4.30 Max 2.13 2.23 2.24 2.34 2.35 2.45 2.45 2.55 2.56 2.66 2.67 2.77 2.77 2.87 2.99 3.09 3.20 3.30 3.41 3.51 3.84 3.94 3.95 4.05 4.27 4.37 4.37 4.47 4.48 4.58 Unit V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI VDLI VDHI LVD stabilization wait time tLVDIW - - - 633 × tCYCP* μs Detection delay time tLVDID dV/dt ≥ - 4mV/μs - - 60 μs SVHI = 0000 SVHI = 0001 SVHI = 0010 SVHI = 0011 SVHI = 0100 SVHI = 0101 SVHI = 0110 SVHI = 0111 SVHI = 1000 SVHI = 1001 SVHI = 1010 SVHI = 1011 SVHI = 1100 SVHI = 1101 SVHI = 1110 Remarks When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises *: tCYCP indicates the APB2 bus clock cycle time. Document Number: 002-05675 Rev. *E Page 80 of 99 CY9A1A0N Series Low power mode (TA = - 40C to + 85C) Parameter Symbol Conditions Min 1.80 Value Typ 2.00 Max 2.20 V When voltage drops 1.90 2.10 2.30 V When voltage rises 1.89 2.10 2.31 V When voltage drops 1.99 2.20 2.41 V When voltage rises 1.98 2.20 2.42 V When voltage drops 2.08 2.30 2.52 V When voltage rises 2.07 2.30 2.53 V When voltage drops 2.17 2.40 2.63 V When voltage rises 2.16 2.40 2.64 V When voltage drops 2.26 2.50 2.74 V When voltage rises 2.25 2.50 2.75 V When voltage drops 2.35 2.60 2.85 V When voltage rises 2.34 2.60 2.86 V When voltage drops 2.44 2.70 2.96 V When voltage rises 2.52 2.80 3.08 V When voltage drops 2.62 2.90 3.18 V When voltage rises 2.70 3.00 3.30 V When voltage drops 2.80 3.10 3.40 V When voltage rises 2.88 3.20 3.52 V When voltage drops 2.98 3.30 3.62 V When voltage rises 3.24 3.60 3.96 V When voltage drops 3.34 3.70 4.06 V When voltage rises 3.33 3.70 4.07 V When voltage drops 3.43 3.80 4.17 V When voltage rises 3.60 4.00 4.40 V When voltage drops 3.70 4.10 4.50 V When voltage rises 3.69 4.10 4.51 V When voltage drops 3.79 4.20 4.61 V When voltage rises 3.78 4.20 4.62 V When voltage drops 3.88 4.30 4.72 V When voltage rises Unit Detected voltage VDLIL Released voltage VDHIL Detected voltage VDLIL Released voltage VDHIL Detected voltage VDLIL Released voltage VDHIL Detected voltage VDLIL Released voltage VDHIL Detected voltage VDLIL Released voltage VDHIL Detected voltage VDLIL Released voltage VDHIL Detected voltage VDLIL Released voltage VDHIL Detected voltage VDLIL Released voltage VDHIL Detected voltage VDLIL Released voltage VDHIL Detected voltage VDLIL Released voltage VDHIL Detected voltage VDLIL Released voltage VDHIL Detected voltage VDLIL Released voltage VDHIL Detected voltage VDLIL Released voltage VDHIL Detected voltage VDLIL Released voltage VDHIL Detected voltage VDLIL Released voltage VDHIL LVD stabilization wait time tLVDILW - - - 8039 × tCYCP* μs Detection delay time tLVDILD dV/dt ≥ - 0.4mV/μs - - 800 μs SVHI = 0000 SVHI = 0001 SVHI = 0010 SVHI = 0011 SVHI = 0100 SVHI = 0101 SVHI = 0110 SVHI = 0111 SVHI = 1000 SVHI = 1001 SVHI = 1010 SVHI = 1011 SVHI = 1100 SVHI = 1101 SVHI = 1110 Remarks *: tCYCP indicates the APB2 bus clock cycle time. Document Number: 002-05675 Rev. *E Page 81 of 99 CY9A1A0N Series 12.8 Flash Memory Write/Erase Characteristics Write / Erase time 12.8.1 (VCC = 2.0V to 5.5V, TA = - 40C to + 85C) Parameter Value Typ* 1.6 0.4 Max* 7.5 2.1 Half word (16-bit) write time 25 Chip erase time 4 Sector erase time Large Sector Small Sector Unit Remarks s Includes write time prior to internal erase 400 μs Not including system-level overhead time. 19.2 s Includes write time prior to internal erase *: The typical value is immediately after shipment, the maximam value is guarantee value under 100,000 cycle of erase/write. Write cycles and data hold time 12.8.2 Erase/write cycles (cycle) Data hold time (year) 1,000 20 * 10,000 100,000 10 * 5* Remarks *: At average + 85C Document Number: 002-05675 Rev. *E Page 82 of 99 CY9A1A0N Series 12.9 Return Time from Low-Power Consumption Mode 12.9.1 Return Factor: Interrupt/WKUP The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the program operation. Return Count Time (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Value Typ tCYCC Sleep mode High-speed CR Timer mode, Main Timer mode, PLL Timer mode Low-speed CR Timer mode Sub Timer mode Max* tICNT RTC mode, Stop mode Deep Standby RTC mode Deep Standby Stop mode Unit Remarks μs 40 80 μs 630 1260 μs 630 1260 μs 1083 2100 μs 1099 2127 μs *: The maximum value depends on the accuracy of built-in CR. Operation example of return from Low-Power consumption mode (by external interrupt*) External interrupt Interrupt factor accept Active tICNT CPU Operation Interrupt factor clear by CPU Start *: External interrupt is set to detecting fall edge. Document Number: 002-05675 Rev. *E Page 83 of 99 CY9A1A0N Series Operation example of return from Low-Power consumption mode (by internal resource interrupt*) Internal resource interrupt Interrupt factor accept Active tICNT CPU Operation Interrupt factor clear by CPU Start *: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode. Notes: − The return factor is different in each Low-Power consumption modes. See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family Peripheral Manual. − When interrupt recoveries, the operation mode that CPU recoveries depend on the state before the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM3 Family Peripheral Manual. Document Number: 002-05675 Rev. *E Page 84 of 99 CY9A1A0N Series 12.9.2 Return Factor: Reset The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program operation. Return Count Time (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Value Unit Typ Max* 359 647 μs 359 647 μs 929 1787 μs Sub Timer mode 929 1787 μs RTC/Stop mode 1099 2127 μs Deep Standby RTC mode Deep Standby Stop mode 1099 2127 μs Sleep mode High-speed CR Timer mode, Main Timer mode, PLL Timer mode Low-speed CR Timer mode tRCNT Remarks *: The maximum value depends on the accuracy of built-in CR. Operation example of return from Low-Power consumption mode (by INITX) INITX Internal reset Reset active Release tRCNT CPU Operation Document Number: 002-05675 Rev. *E Start Page 85 of 99 CY9A1A0N Series Operation example of return from low power consumption mode (by internal resource reset*) Internal resource reset Internal reset Reset active Release tRCNT CPU Operation Start *: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode. Notes: − The return factor is different in each Low-Power consumption modes. See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family Peripheral Manual. − When interrupt recoveries, the operation mode that CPU recoveries depend on the state before the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM3 Family Peripheral Manual. − The time during the power-on reset/low-voltage detection reset is excluded. See (12.4.7) Power-on Reset Timing in 12.4 AC Characteristics in Electrical Characteristics for the detail on the time during the power-on reset/low-voltage detection reset. − When in recovery from reset, CPU changes to the High-speed CR Run mode. When using the main clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or the Main PLL clock stabilization wait time. − The internal resource reset means the watchdog reset and the CSV reset. Document Number: 002-05675 Rev. *E Page 86 of 99 CY9A1A0N Series 13. Ordering Information Part number On-chip Flash memory On-chip SRAM CY9AF1A1LPMC1-G-SNE2 64 Kbyte 12 Kbyte CY9AF1A2LPMC1-G-SNE2 128 Kbyte 16 Kbyte CY9AF1A1LPMC-G-SNE2 64 Kbyte 12 Kbyte CY9AF1A2LPMC-G-UNE2 128 Kbyte 16 Kbyte CY9AF1A1MPMC-G-UNE2 64 Kbyte 12 Kbyte CY9AF1A2MPMC-G-UNE2 128 Kbyte 16 Kbyte CY9AF1A1MPMC1-G-SNE2 64 Kbyte 12 Kbyte CY9AF1A2MPMC1-G-UNE2 128 Kbyte 16 Kbyte CY9AF1A1NPMC-G-SNE2 64 Kbyte 12 Kbyte CY9AF1A2NPMC-G-UNE2 128 Kbyte 16 Kbyte CY9AF1A1NPF-G-SNE1 64 Kbyte 12 Kbyte CY9AF1A2NPF-G-SNE1 128 Kbyte 16 Kbyte Document Number: 002-05675 Rev. *E Package Packing Plastic  LQFP (0.5mm pitch), 64-pin (LQD064) Plastic  LQFP (0.65mm pitch), 64-pin (LQG064) Plastic  LQFP (0.5mm pitch), 80-pin (LQH080) Plastic  LQFP (0.65mm pitch), 80-pin (LQJ080) Tray Plastic  LQFP (0.5mm pitch), 100-pin (LQI100) Plastic  QFP (0.65mm pitch), 100-pin (PQH100) Page 87 of 99 CY9A1A0N Series 14. Package Dimensions Package Type Package Code LQFP 64 LQD064 4 D D1 48 5 7 33 33 32 49 48 32 49 17 64 5 7 E1 E 4 3 6 17 64 1 16 e 1 16 2 5 7 3 BOTTOM VIEW 0.1 0 C A-B D 0.2 0 C A-B D b 0.0 8 C A-B D 8 TOP VIEW A 2 9 A A' 0.0 8 C SEATING PLAN E L1 0.25 L A1 c b SECTION A-A' 10 SIDE VIEW SYM BOL DIM ENSIONS M IN. NOM . M AX. A A1 1. 70 0.00 0.20 b 0.15 0.2 c 0.09 0.20 D 12.00 BSC. D1 10.00 BSC. e 0.50 BSC E 12.00 BSC. E1 10.00 BSC. L 0.45 0.60 0.75 L1 0.30 0.50 0.70 002-11499 ** PACKAGE OUTLINE, 64 LEAD LQFP 10.0X10.0X1.7 M M LQD064 Rev** Document Number: 002-05675 Rev. *E Page 88 of 99 CY9A1A0N Series Package Type Package Code LQFP 64 LQG064 D D1 48 4 5 7 33 33 32 49 48 32 49 17 64 E1 E 5 7 4 3 17 64 1 16 e 0.20 1 16 2 5 7 3 BOTTOM VIEW 0.10 C A-B D C A-B D b 0.13 C A-B D 8 TOP VIEW 2 A θ A A' 0.10 C SEATI N G PLA N E 0.2 5 L1 L 9 A1 10 c b SECTION A -A' SIDE VIEW SYM BOL DIM ENSION M IN. NOM . M AX. 0.00 0.20 1.70 A A1 b 0.27 c 0.09 0.32 0.20 D 14.00 BSC D1 12.00 BSC e 0.65 BSC E 14.00 BSC E1 0.37 12.00 BSC L 0.45 0.60 0.75 L1 0.30 0.50 0.70 θ 0° 8° 002-13881 ** PACKAGE OUTLINE, 64 LEAD LQFP 12.0X12.0X1.7 M M LQG064 REV** Document Number: 002-05675 Rev. *E Page 89 of 99 CY9A1A0N Series Package Type Package Code LQFP 80 LQH080 4 D D1 60 5 7 41 41 40 61 60 40 61 21 80 5 7 E1 E 4 3 6 80 21 1 20 D e 20 2 5 7 0.10 C A-B D 3 b 0.08 C A-B 1 BOTTOM VIEW D 0.20 C A-B D 8 TOP VIEW 2 A A A' 0.08 C SIDE VIEW SEATIN G PLAN E 9 L1 L 0.25 A1 10 c b SECTION A-A' DIM ENSIONS SYMBOL M IN. NOM . M AX. A A1 1. 70 0.05 0.15 b 0.15 0.27 c 0.09 0.20 D 14.00 BSC. D1 12.00 BSC. e 0.50 BSC E 14.00 BSC. E1 12.00 BSC. L 0.45 0.60 0.75 L1 0.30 0.50 0.70 002-11501 ** PACKAGE OUTLINE, 80 LEAD LQFP 12.0X12.0X1.7 M M LQH080 Rev ** Document Number: 002-05675 Rev. *E Page 90 of 99 CY9A1A0N Series Package Type Package Code LQFP 80 LQJ080 D D1 60 4 5 7 41 41 61 40 E1 60 40 61 21 80 E 5 7 4 3 6 80 21 1 20 20 2 5 7 1 0.1 0 C A-B D 3 e 0.2 0 C A-B D b dd d C A-B D 8 2 A A A' 0.1 0 C SEATING PLAN E 9 θ c L1 0.2 5 A1 10 b SECTION A-A' L SYM BOL DIM ENSIONS M IN. NOM . M AX. 1.70 A A1 0.00 b 0.16 0.20 c 0.09 0.32 0.38 0.20 D 16.00 BSC D1 14.00 BSC e 0.65 BSC E 16.00 BSC E1 14.00 BSC L 0.45 0.60 0.75 L1 0.30 0.50 0.70 θ 0° 8° 002-14043 ** PACKAGE OUTLINE, 80 LEAD LQFP 14.0X14.0X1.7 M M LQJ080 REV** Document Number: 002-05675 Rev. *E Page 91 of 99 CY9A1A0N Series Package Type Package Code LQFP 100 LQI100 D D1 75 4 D 5 7 51 D1 51 50 76 4 5 7 75 50 76 E1 E 5 4 7 E1 E 5 4 7 3 6 26 100 1 26 25 1 25 2 5 7 e 100 BOTTOM VIEW 0.1 0 C A-B D 3 0.2 0 C A-B D b TOP VIEW 8 0.0 8 C A-B D 2 A 9 A SEATIN G PLA N E A' 0.25 L1 0.0 8 C c A1 b 10 SECTIO N A-A ' L SIDE VIEW SYM BOL DETAIL A DIM ENSIONS M IN. NOM . M AX. 1.70 A A1 0.05 b 0.15 0.27 c 0.09 0.20 0.15 D 16.00 BSC D1 14.00 BSC e 0.50 BSC E 16.00 BSC E1 14.00 BSC L 0.45 0.60 0.75 L1 0.30 0.50 0.70 NOTES : 1. ALL DIM ENSIONS ARE IN M ILLIM ETERS. 2. DATUM PLANE H IS LOCATED AT THE BOTTOM OF THE M OLD PARTING LINE COINCIDENT W ITH W HERE THE LEAD EXITS THE BODY. 3. DATUM S A-B AND D TO BE DETERM INED AT DATUM PLANE H. 4. TO BE DETERM INED AT SEATING PLANE C. 5. DIM ENSIONS D1 AND E1 DO NOT INCLUDE M OLD PROTRUSION. ALLOW ABLEPROTRUSION IS 0.25m m PRE SIDE. DIM ENSIONS D1 AND E1 INCLUDE M OLD M ISM ATCH AND ARE DETERM INED AT DATUM PLANE H. 6. DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL BUT M UST BE LOCATED W ITHIN THE ZONE INDICATED. 7. REGARDLESS OF THE RELATIVE SIZE OF THE UPPER AND LOW ER BODY SECTIONS. DIM ENSIONS D1 AND E1 ARE DETERM INED AT THE LARGEST FEATURE OF THE BODY EXCLUSIVE OF M OLD FLASH AND GATE BURRS. BUT INCLUDING ANY M ISM ATCH BETW EEN THE UPPER AND LOW ER SECTIONS OF THE M OLDER BODY. 8. DIM ENSION b DOES NOT INCLUDE DAM BAR PROTRUSION. THE DAM BAR PROTRUSION (S) SHALL NOT CAUSE THE LEAD W IDTH TO EXCEED b M AXIM UM BY M ORE THAN 0.08m m . DAM BAR CANNOT BE LOCATED ON THE LOW ER RADIUS OR THE LEAD FOOT. 9. THESE DIM ENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETW EEN 0.10m m AND 0.25m m FROM THE LEAD TIP. 10. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOW EST POINT OF THE PACKAGE BODY. 002-11500 *A PACKAGE OUTLINE, 100 LEAD LQFP 14.0X14.0X1.7 M M LQI100 REV*A Document Number: 002-05675 Rev. *E Page 92 of 99 CY9A1A0N Series Package Type Package Code QFP 100 PQH100 D D1 4 5 7 80 51 81 51 50 80 50 81 31 100 E1 E 5 7 6 3 4 31 100 1 30 e 3 0.40 C A-B D 30 2 5 7 1 0.20 C A-B D b 0.13 C A-B D BOTTOM VIEW 8 TOP VIEW 2 θ 9 A A' SEATING PLANE L2 c 10 b 0.10 C SECTION A-A' D ETAIL A SID E VIEW SYM BOL DIM ENSIONS M IN. NOM . M AX. A1 0.05 0.45 b 0.27 c 0.11 A 3.35 0.32 0.23 D 23.90 BSC D1 20.00 BSC e 0.65 BSC E 17.90 BSC E1 θ L 0.37 14.00 BSC 0° 0.73 8° 0.88 L1 1.95 REF L2 0.2 5 BSC 1.03 002-15156 ** PACKAGE OUTLINE, 100 LEAD QFP 20.00X14.00X3 .35 M M PQH100 REV** Document Number: 002-05675 Rev. *E Page 93 of 99 CY9A1A0N Series 15. Errata This chapter describes the errata for CY9A1A0N Series. Details include errata trigger conditions, scope of impact, available workaround, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions. 15.1 Part Numbers Affected Part Number Initial Revision CY9AF1A1LPMC1-G-SNE2, CY9AF1A2LPMC1-G-SNE2, CY9AF1A1LPMC-G-SNE2, CY9AF1A2LPMC-G-SNE2, CY9AF1A2LPMC-G-UNE2, CY9AF1A1MPMC-G-SNE2, CY9AF1A1MPMC-G-UNE2, CY9AF1A2MPMC-G-SNE2, CY9AF1A2MPMC-G-UNE2, CY9AF1A1MPMC1-G-SNE2, CY9AF1A2MPMC1-G-SNE2, CY9AF1A2MPMC1-G-UNE2, CY9AF1A1NPMC-G-SNE2, CY9AF1A2NPMC-G-SNE2, CY9AF1A2NPMC-G-UNE2, CY9AF1A1NPF-G-SNE1, CY9AF1A2NPF-G-SNE1 15.2 Qualification Status Product Status: In Production − Qual. 15.3 Errata Summary This table defines the errata applicability to available devices. Items Part Number Silicon Revision Fix Status [15.4.1] HDMI-CEC polling message issue Refer to 15.1 Initial Rev Next silicon is not planned [15.4.2] RTC delay issue Refer to 15.1 Initial Rev Next silicon is not planned 15.4 Errata Detail 15.4.1 HDMI-CEC polling message issue  PROBLEM DEFINITION Error#1) While MCU sends a Polling Message, it always returns a NACK to a message coming to the MCU from another node. Error#2) MCU always waits for 7-bit signal free on CEC line before it drives the line even when the last line initiator was another node.  PARAMETERS AFFECTED N/A  TRIGGER CONDITION(S) This error always happens.  SCOPE OF IMPACT MCU does not reply properly to another node.  WORKAROUND The software workaround is applied to Error #1. 1. Store 0x0 to SFREE register. 2. Monitor CEC line with GPIO and wait until 1 lasts for the signal free time. 3. Store frame data to TXDATA register and store 0x0F to RCADR1 or RCADR2 register. It sends a message after 3~4 clocks of 32.768 kHz clock when TXDATA is stored 0x0F. Document Number: 002-05675 Rev. *E Page 94 of 99 CY9A1A0N Series If the device receives a frame from another node within 2~3 clocks after storing TXDATA, the bus error occurs and if the device receives a frame from another node within 3~4 clocks after storing TXDATA, the arbitration lost occurs. In these cases: 4-A-1. Set RCADR1 or RCADR2 to former value from 0x0F to reply ACK 4-A-2. Return back to step 2 above If the device receives a frame from another node within 1~2 clocks after storing TXDATA, take these steps. 4-B-1. Monitor CEC line with GPIO after 50us from storing TXDATA 4-B-2. Set TXEN to 1 -> 0 -> 1 immediately when GPIO finds state low on the CEC line 4-B-3. Set RCADR1 or RCADR2 to former value from 0x0F to reply ACK 4-B-4. Return back to step 2 above For Error #2, there is no software workaround, but signal free time of fixed 7-bit does not violate HDMI-CEC specification. The specification says signal free time must be more than and equals to 5-bit.  FIX STATUS The user uses the workaround to avoid the issue. The next silicon fixing the issue is not planned. 15.4.2 RTC delay issue  PROBLEM DEFINITION RTC delays when software reset or APB2 reset occurs.  PARAMETERS AFFECTED N/A  TRIGGER CONDITION(S) This error happens when software reset or APB2 reset occurs.  SCOPE OF IMPACT RTC delays and does not time correctly.  WORKAROUND RTC block is supplied with sub-clock. Both software reset and APB2 reset disable two clocks of sub-clock to RTC block. The workaround is to count occurrence of software and APB2 reset and calculate how many clocks of sub-clock were disabled and add one second to RTC counter when accumulated disabled sub-clock period reaches one second.  FIX STATUS The user uses the workaround to avoid the issue. The next silicon fixing the issue is not planned. Document Number: 002-05675 Rev. *E Page 95 of 99 CY9A1A0N Series Major Changes Spansion Publication Number: DS706-00068 Page Section Revision 0.1 Revision 1.0 43 BLOCK DIAGRAM ELECTRICAL CHARACTERISTICS 58,59 3.DC Characteristics (1) Current Rating Revision 2.0 Features 2 · On-chip Memories Packages 7 - 31 Pin Assignment List of Pin Functions Change Results Initial release Changed from Preliminary to Full Producton Deleted a part of QFN Added note for MB9AF1AxL Revised the values of “TBD” Changed the description of on-chip SRAM Deleted QFN package 40 Handling Devices Crystal oscillator circuit Added the following description "Evaluate oscillation of your using crystal oscillator by your mount board." 44 Memory Map · Memory map(2) Added the summary of Flash memory sector 57 - 59 Electrical Characteristics 3. DC Characteristics (1) Current rating · Changed the table format · Added Main Timer mode current · Added Flash Memory Current · Moved A/D Converter Current · Moved D/A Converter Current 60 63 64 Electrical Characteristics 3. DC Characteristics (2) Pin Characteristics Electrical Characteristics 4. AC Characteristics (4-1) Operating Conditions of Main PLL (4-2) Operating Conditions of Main PLL Electrical Characteristics 4. AC Characteristics (6) Power-on Reset Timing 66 - 73 Electrical Characteristics 4. AC Characteristics (8) CSIO/UART Timing 77 Electrical Characteristics 5. 12bit A/D Converter 81 84 Electrical Characteristics 7. Low-voltage Detection Characteristics Electrical Characteristics 8. Flash Memory Write/Erase Characteristics Document Number: 002-05675 Rev. *E Added the input leak current of CEC port at power off · Added the figure of Main PLL connection · Changed the figure of timing · Changed from Reset release delay time(tOND) to Time until releasing Power-on reset(tPRT) · Modified from UART Timing to CSIO/UART Timing · Changed from Internal shift clock operation to Master mode · Changed from External shift clock operation to Slave mode · Added the typical value of Integral Nonlinearity, Differential Nonlinearity, Zero transition voltage and Full-scale transition voltage · Added Conversion time at AVCC < 2.7 V Deleted the figure Change to the erase time of include write time prior to internal erase Page 96 of 99 CY9A1A0N Series Page Section Change Results Electrical Characteristics 9. Return Time from Low-Power Added Return Time from Low-Power Consumption Mode Consumption Mode 89 Ordering Information Changed notation of part number NOTE: Please see “Document History” about later revised information. 85 - 88 Document Number: 002-05675 Rev. *E Page 97 of 99 CY9A1A0N Series Document History Document Title: CY9A1A0N Series 32-bit Arm® Cortex®-M3 FM3 Microcontroller Document Number: 002-05675 Revision ECN ** - Orig. of Submission Change Date AKIH 06/30/2015 Description of Change Migrated to Cypress and assigned document number 002-05675. No change to document contents or format. *A 5193131 AKIH 03/31/2016 Updated to Cypress template. *B 5513616 HTER 02/08/2017 Modified RTC description in “Features, Real-Time Clock(RTC)”. Changed starting count value from 01 to 00. Deleted “second, or day of the week” in the Interrupt function. (Page 2) Changed package code as the following table in following section. 2. Package (Page 7) 3. Pin Assignment (Page 8 -11) 12. Electrical Characteristics (Page 53) 13. Ordering Information (Page 87) 14. Package Dimensions (Page 88 - 93) Before After FPT-64P-M38 LQD064 FPT-64P-M39 LQG064 FPT-80P-M37 LQH080 FPT-80P-M40 LQJ080 FPT-100P-M23 LQI100 FPT-100P-M06 PQH100 Added the Baud rate spec in “12.4.9 CSIO/UART Timing” (Page 64 - 70) Changed Part numbers in 13. Ordering Information (Page 87) “MB9AF1A2LPMC-G-SNE2” to “MB9AF1A2LPMC-G-UNE2” “MB9AF1A2MPMC-G-SNE2” to “MB9AF1A2MPMC-G-UNE2” “MB9AF1A2NPMC-G-SNE2” to “MB9AF1A2NPMC-G-UNE2” “MB9AF1A1MPMC-G-SNE2” to “MB9AF1A1MPMC-G-UNE2” “MB9AF1A2MPMC1-G-SNE2” to “MB9AF1A2MPMC1-G-UNE2” Added 15. Errata (Page 94 - 95) *C 5768635 YSAT 06/12/2017 Updated to new template. *D 5929772 HTER 10/16/2017 Corrected the following Analog output impedance MAX value (D/A operation) 4.55kΩ  5.5kΩ in chapter 12.6 10-bit D/A Converter. *E 6575847 XITO Document Number: 002-05675 Rev. *E 05/17/2019 Updated Document Title to read as “CY9A1A0N Series 32-bit Arm® Cortex®-M3 FM3 Microcontroller”. Replaced “MB9A1A0N Series” with “CY9A1A0N Series” in all instances across the document. Updated Ordering Information: Updated part numbers. Updated to new template. Completing Sunset Review. Page 98 of 99 CY9A1A0N Series Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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