Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
PRELIMINARY
CYW43364
Single-Chip IEEE 802.11 b/g/n MAC/
Baseband/Radio
The Cypress CYW43364 is a highly integrated single-chip solution and offers the lowest RBOM in the industry for Internet of Things
(IoT) and a wide range of other portable devices. The chip includes a 2.4 GHz WLAN IEEE 802.11 b/g/n MAC/baseband/radio. In
addition, it integrates a power amplifier (PA) that meets the output power requirements of most handheld systems, a low-noise amplifier
(LNA) for best-in-class receiver sensitivity, and an internal transmit/receive (iTR) RF switch, further reducing the overall solution cost
and printed circuit board area.
The WLAN host interface supports SDIO v2.0 mode, providing a raw data transfer rate up to 200 Mbps when operating in 4-bit mode
at a 50 MHz bus frequency.
Using advanced design techniques and process technology to reduce active and idle power, the CYW43364 is designed to address
the needs of highly mobile devices that require minimal power consumption and compact size. It includes a power management unit
that simplifies the system power topology while maximizing battery life.
Cypress Part Numbering Scheme
Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion,
there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides
Cypress ordering part number that matches an existing IoT part number.
Table 1. Mapping Table for Part Number between Broadcom and Cypress
Broadcom Part Number
Cypress Part Number
BCM43364
CYW43364
BCM43364KUBG
CYW43364KUBG
Features
IEEE 802.11x Key Features
■
General Features
Single-band 2.4 GHz IEEE 802.11b/g/n.
TurboQAM®
Support diversity antenna.
■
Supports a battery voltage range from 3.0V to 4.8V with an
internal switching regulator.
■
Support for 2.4 GHz Cypress
QAM) and 20 MHz channel bandwidth.
■
Integrated iTR switch supports a single 2.4 GHz antenna.
■
Programmable dynamic power management.
■
Supports explicit IEEE 802.11n transmit beamforming.
■
■
Tx and Rx low-density parity check (LDPC) support for
improved range and power efficiency.
4 Kbit one-time programmable (OTP) memory for storing board
parameters.
■
Can be routed on low-cost 1-x-1 PCB stack-ups.
■
Supports standard SDIO v2.0 host interface.
■
74-ball WLBGA package (4.87 mm × 2.87 mm, 0.4 mm pitch).
■
Supports space-time block coding (STBC) in the receiver.
■
■
Integrated ARM Cortex-M3 processor and on-chip memory for
complete WLAN subsystem functionality, minimizing the need
to wake up the applications processor for standard WLAN
functions. This allows for further minimization of power
consumption, while maintaining the ability to field-upgrade with
future features. On-chip memory includes 512 KB SRAM and
640 KB ROM.
Security:
❐ WPA and WPA2 (Personal) support for powerful encryption
and authentication.
❐ AES in WLAN hardware for faster data encryption and IEEE
802.11i compatibility.
❐ Reference WLAN subsystem provides Cisco Compatible Extensions (CCX, CCX 2.0, CCX 3.0, CCX 4.0, CCX 5.0).
❐ Reference WLAN subsystem provides Wi-Fi protected setup
(WPS).
■
Worldwide regulatory support: Global products supported with
worldwide homologated design.
■
data rates (256-
■
OneDriver™ software architecture for easy migration from
existing embedded WLAN.
Cypress Semiconductor Corporation
Document Number: 002-14781 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised Thursday, April 5, 2018
PRELIMINARY
CYW43364
Figure 1. CYW43364 System Block Diagram
VDDIO
VBAT
WL_REG_ON
WLAN
Host I/F
WL_HOST_WAKE
SDIO
2.4 GHz WLAN TX/RX
BPF
CYW43364
CLK_REQ
REF_CLK
(19.2, 26, or 37.4 MHz)
Document Number: 002-14781 Rev. *E
Page 2 of 56
PRELIMINARY
CYW43364
Contents
1. Overview ........................................................................ 4
1.1 Overview ............................................................... 4
1.2 Features ................................................................ 5
1.3 Standards Compliance .......................................... 5
2. Power Supplies and Power Management ................... 6
2.1 Power Supply Topology ........................................ 6
2.2 CYW43364 PMU Features .................................... 6
2.3 WLAN Power Management ................................... 9
2.4 PMU Sequencing .................................................. 9
2.5 Power-Off Shutdown ........................................... 10
2.6 Power-Up/Power-Down/Reset Circuits ............... 10
3. Frequency References ............................................... 11
3.1 Crystal Interface and Clock Generation .............. 11
3.2 TCXO .................................................................. 12
3.3 External 32.768 kHz Low-Power Oscillator ......... 13
4. WLAN System Interfaces ........................................... 14
4.1 SDIO v2.0 ............................................................ 14
5. Wireless LAN MAC and PHY ..................................... 15
5.1 MAC Features ..................................................... 15
5.2 PHY Description .................................................. 17
6. WLAN Radio Subsystem ............................................ 19
6.1 Receive Path ....................................................... 19
6.2 Transmit Path ...................................................... 19
6.3 Calibration ........................................................... 19
7. CPU and Global Functions ........................................ 20
7.1 WLAN CPU and Memory Subsystem .................. 20
7.2 One-Time Programmable Memory ...................... 20
7.3 GPIO Interface .................................................... 20
7.4 External Coexistence Interface ........................... 21
7.5 JTAG Interface ................................................... 23
7.6 UART Interface ................................................... 23
8. Pinout and Signal Descriptions ................................ 24
8.1 Ball Map .............................................................. 24
8.2 WLBGA Ball List in Ball Number Order with X-Y
Coordinates ....................................................... 25
8.3 WLBGA Ball List Ordered By Ball Name ............. 27
8.4 Signal Descriptions .............................................. 28
8.5 WLAN GPIO Signals and Strapping Options ...... 30
Document Number: 002-14781 Rev. *E
8.6 Chip Debug Options ............................................ 30
8.7 I/O States ............................................................ 31
9. DC Characteristics ..................................................... 33
9.1 Absolute Maximum Ratings ................................. 33
9.2 Environmental Ratings ........................................ 33
9.3 Electrostatic Discharge Specifications ................ 34
9.4 Recommended Operating Conditions and DC
Characteristics ................................................... 34
10. WLAN RF Specifications .......................................... 36
10.1 2.4 GHz Band General RF Specifications ......... 36
10.2 WLAN 2.4 GHz Receiver Performance
Specifications ..................................................... 37
10.3 WLAN 2.4 GHz Transmitter Performance
Specifications ..................................................... 40
10.4 General Spurious Emissions Specifications ...... 41
11. Internal Regulator Electrical Specifications .......... 42
11.1 Core Buck Switching Regulator ......................... 42
11.2 3.3V LDO (LDO3P3) ......................................... 43
11.3 CLDO ................................................................ 44
11.4 LNLDO .............................................................. 45
12. System Power Consumption ................................... 46
12.1 WLAN Current Consumption ............................. 46
13. Interface Timing and AC Characteristics ............... 47
13.1 SDIO Default Mode Timing ............................... 47
13.2 SDIO High-Speed Mode Timing ........................ 48
13.3 JTAG Timing ..................................................... 49
14. Power-Up Sequence and Timing ............................. 50
14.1 Sequencing of Reset and Regulator Control
Signals ............................................................... 50
15. Package Information ................................................ 51
15.1 Package Thermal Characteristics ..................... 51
16. Mechanical Information ........................................... 52
17. Ordering Information ................................................ 54
18. Additional information ............................................. 54
18.1 Acronyms and Abbreviations ............................. 54
18.2 IoT Resources ................................................... 54
Document History .......................................................... 55
n Sales, Solutions, and Legal Information ................... 56
Page 3 of 56
PRELIMINARY
CYW43364
1. Overview
1.1 Overview
The Cypress CYW43364 provides the highest level of integration for IoT and wireless automation system, with integrated
IEEE 802.11 b/g/n. It provides a small form-factor solution with minimal external components to drive down cost for mass volumes
and allows for handheld device flexibility in size, form, and function. The CYW43364 is designed to address the needs of highly mobile
devices that require minimal power consumption and reliable operation.
Figure 2 on page 4 shows the interconnection of all the major physical blocks in the CYW43364 and their associated external
interfaces, which are described in greater detail in subsequent sections.
SDP
ETM
Cortex
M3
JTAG*
Figure 2. CYW43364 Block Diagram
Debug
AHB Bus Matrix
AHB
AHB to
APB Bridge
RAM
ROM
APB
Patch
WD Timer
InterCtrl
SW Timer
DMA
Bus Arb
ARM IP
GPIO
Ctrl
JTAG supported
over SDIO
SDIO
Power
Supply
Sleep CLK
XTAL
WL_REG_ON
Common and
Radio Digital
SWREG
LDOx2
PMU
Control
SDIO
LPO
XTAL OSC.
ARM
CM3
Supported over SDIO
Radio
2.4 GHz
JTAG*
MAC
BT-WLAN
ECI
GPIO
UART
UART
IEEE 802.11a/b/g/n
ROM
OTP
GPIO
Backplane
RAM
WDT
LNPPHY
JTAG*
POR
2.4 GHz
PA
LNA
BPF
WLAN
Document Number: 002-14781 Rev. *E
Page 4 of 56
PRELIMINARY
CYW43364
1.2 Features
The CYW43364 supports the following WLAN features:
■
IEEE 802.11b/g/n single-band radio with an internal power amplifier, LNA, and T/R switch
■
On-chip WLAN driver execution capable of supporting IEEE 802.11 functionality
■
WLAN host interface options:
SDIO v2.0, including default and high-speed timing.
❐
1.3 Standards Compliance
The CYW43364 supports the following standards:
■ IEEE 802.11n—Handheld Device Class (Section 11)
■ IEEE 802.11b
■ IEEE 802.11g
■ IEEE 802.11d
■ IEEE 802.11h
■ IEEE 802.11i
The CYW43364 will support the following future drafts/standards:
■ IEEE 802.11r — Fast Roaming (between APs)
■ IEEE 802.11k — Resource Management
■ IEEE 802.11w — Secure Management Frames
■ IEEE 802.11 Extensions:
■ IEEE 802.11e QoS Enhancements (as per the WMM specification is already supported)
■ IEEE 802.11i MAC Enhancements
■ IEEE 802.11r Fast Roaming Support
■ IEEE 802.11k Radio Resource Measurement
The CYW43364 supports the following security features and proprietary protocols:
■ Security:
❐ WEP
❐ WPA Personal
❐ WPA2 Personal
❐ WMM
❐ WMM-PS (U-APSD)
❐ WMM-SA
❐ WAPI
❐ AES (Hardware Accelerator)
❐ TKIP (host-computed)
❐ CKIP (SW Support)
■ Proprietary Protocols:
❐ CCXv2
❐ CCXv3
❐ CCXv4
❐ CCXv5
■ IEEE 802.15.2 Coexistence Compliance — on silicon solution compliant with IEEE 3-wire requirements.
Document Number: 002-14781 Rev. *E
Page 5 of 56
PRELIMINARY
CYW43364
2. Power Supplies and Power Management
2.1 Power Supply Topology
One Buck regulator, multiple LDO regulators, and a power management unit (PMU) are integrated into the CYW43364. All regulators
are programmable via the PMU to simplify the power supply.
A single VBAT (3.0V to 4.8V DC maximum) and VDDIO supply (1.8V to 3.3V) can be used, with all additional voltages being provided
by the regulators in the CYW43364.
The WL_REG_ON control signal is used to power up the regulators and take the respective circuit blocks out of reset. The CBUCK
CLDO and LNLDO power up when any of the reset signals are deasserted. All regulators are powered down only when WL_REG_ON
is deasserted. The CLDO and LNLDO can be turned on and off based on the dynamic demands of the digital baseband.
The CYW43364 allows for an extremely low power-consumption mode by completely shutting down the CBUCK, CLDO, and LNLDO
regulators. When in this state, LPLDO1 provides the CYW43364 with all required voltage, further reducing leakage currents.
Notes:
VBAT should be connected to the LDO_VDDBAT5V and SR_VDDBAT5V pins of the device.
VDDIO should be connected to the SYS_VDDIO and WCC_VDDIO pins of the device.
2.2 CYW43364 PMU Features
The PMU supports the following:
■
VBAT to 1.35Vout (170 mA nominal, 370 mA maximum) Core-Buck (CBUCK) switching regulator
■
VBAT to 3.3Vout (250 mA nominal, 450 mA maximum 800 mA peak maximum) LDO3P3
■
1.35V to 1.2Vout (100 mA nominal, 150 mA maximum) LNLDO
■
1.35V to 1.2Vout (80 mA nominal, 200 mA maximum) CLDO with bypass mode for deep sleep
■
Additional internal LDOs (not externally accessible)
■
PMU internal timer auto-calibration by the crystal clock for precise wake-up timing from extremely low power-consumption mode.
Figure 3 on page 7 and Figure 4 on page 8 show the typical power topology of the CYW43364.
Document Number: 002-14781 Rev. *E
Page 6 of 56
PRELIMINARY
CYW43364
Figure 3. Typical Power Topology (1 of 2)
SR_VDDBAT5V
VBAT
WL RF—TX Mixer and PA
Mini PMU
CYW43364
1.2V
VBAT:
Operational:
3.0V—4.8V
Performance:
3.0V—4.8V
Absolute Maximum: 5.5V
VDDIO
Operational:
1.8V—3.3V
Core Buck
Int_SR_VBAT
Regulator
Peak: 370 mA
Avg: 170 mA
(320 mA)
VDD1P35
WL RF—LOGEN
Internal RXLDO
10 mA (NMOS)
1.2V
WL RF—RX LNA
Internal ADCLDO
10 mA (NMOS)
1.2V
WL RF—ADC REF
Internal TXLDO
80 mA (PMOS)
1.2V
WL RF—TX
Internal AFELDO
80 mA (NMOS)
1.2V
LDO_VDD_1P5
VBAT
SR_PVSS
4.7 uF
0402
LNLDO
(100 mA)
1.2V
(40 mA)
600 @
100 MHz
VOUT_LNLDO
2.2 uF
0402
PMU_VSS
WCC_VDDIO
WL RF—AFE and TIA
Mini PMU is placed
in WL radio
2.2 uH
0603
SR_VBAT5V
WCC_VDDIO
1.2V
1.35V
SR_VLX
SW1
GND
Internal VCOLDO
80 mA (NMOS)
LPLDO1
(5 mA)
WLRF_XTAL_
VDD1P2
10 mA average,
> 10 mA at start‐up
WL RF—RFPLL PFD and MMD
WL RF—XTAL
0.1 uF
0201
1.1V
WLAN/CLB/Top, Always On
VDDC1
1.3V, 1.2V,
CL LDO
or 0.95V
Peak: 200 mA (AVS)
Avg: 80 mA
(Bypass in deep‐
VOUT_CLDO
sleep)
WL_REG_ON
WL OTP
VDDC2
2.2 uF
0402
WL Digital and PHY
o_wl_resetb
WL VDDM (SROMs & AOS)
Supply ball
Supply bump/pad
Power switch
Ground ball
Ground bump/pad
No power switch
WLAN reset balls
External to chip
No dedicated power switch, but internal power‐
down modes and block‐specific power switches
Document Number: 002-14781 Rev. *E
Page 7 of 56
PRELIMINARY
CYW43364
Figure 4. Typical Power Topology (2 of 2)
CYW43364
1.8V, 2.5V, and 3.3V
VBAT
LDO_
VDDBAT5V
VOUT_3P3
LDO3P3 with
Back‐Power
VOUT_3P3
Protection
4.7 uF
(Peak 450‐800 mA
200 mA Average) 3.3V
0402
6.4 mA
WL BBPLL/DFLL
WL OTP 3.3V
480 to 800 mA
WLRF_PA_VDD
1 uF
0201
WL RF—PA (2.4 GHz)
2.5V Cap‐less
LNLDO
(10 mA)
6.4 mA
WL RF—ADC, AFE, LOGEN,
LNA, NMOS Mini‐PMU LDOs
Power switch
External to chip
No power switch
Supply ball
No dedicated power switch, but internal power‐
down modes and block‐specific power switches
Document Number: 002-14781 Rev. *E
Page 8 of 56
PRELIMINARY
CYW43364
2.3 WLAN Power Management
The CYW43364 has been designed with the stringent power consumption requirements of mobile devices in mind. All areas of the
chip design are optimized to minimize power consumption. Silicon processes and cell libraries were chosen to reduce leakage current
and supply voltages. Additionally, the CYW43364 integrated RAM is a high volatile memory with dynamic clock control. The dominant
supply current consumed by the RAM is leakage current only. Additionally, the CYW43364 includes an advanced WLAN power
management unit (PMU) sequencer. The PMU sequencer provides significant power savings by putting the CYW43364 into various
power management states appropriate to the operating environment and the activities that are being performed. The power
management unit enables and disables internal regulators, switches, and other blocks based on a computation of the required
resources and a table that describes the relationship between resources and the time needed to enable and disable them. Power-up
sequences are fully programmable. Configurable, free-running counters (running at the 32.768 kHz LPO clock) in the PMU sequencer
are used to turn on/turn off individual regulators and power switches. Clock speeds are dynamically changed (or gated altogether) for
the current mode. Slower clock speeds are used wherever possible.
The CYW43364 WLAN power states are described as follows:
■
Active mode: All WLAN blocks in the CYW43364 are powered up and fully functional with active carrier sensing and frame
transmission and receiving. All required regulators are enabled and put in the most efficient mode based on the load current. Clock
speeds are dynamically adjusted by the PMU sequencer.
■
Doze mode: The radio, analog domains, and most of the linear regulators are powered down. The rest of the CYW43364 remains
powered up in an IDLE state. All main clocks (PLL, crystal oscillator) are shut down to reduce active power to the minimum. The
32.768 kHz LPO clock is available only for the PMU sequencer. This condition is necessary to allow the PMU sequencer to wake
up the chip and transition to Active mode. In Doze mode, the primary power consumed is due to leakage current.
■
Deep-sleep mode: Most of the chip, including analog and digital domains, and most of the regulators are powered off. Logic states
in the digital core are saved and preserved to retention memory in the always-on domain before the digital core is powered off. To
avoid lengthy hardware reinitialization, the logic states in the digital core are restored to their pre-deep-sleep settings when a wakeup event is triggered by an external interrupt, a host resume through the SDIO bus, or by the PMU timers.
■
Power-down mode: The CYW43364 is effectively powered off by shutting down all internal regulators. The chip is brought out of
this mode by external logic re-enabling the internal regulators.
2.4 PMU Sequencing
The PMU sequencer is used to minimize system power consumption. It enables and disables various system resources based on a
computation of required resources and a table that describes the relationship between resources and the time required to enable and
disable them.
Resource requests can derive from several sources: clock requests from cores, the minimum resources defined in the ResourceMin
register, and the resources requested by any active resource request timers. The PMU sequencer maps clock requests into a set of
resources required to produce the requested clocks.
Each resource is in one of the following four states:
■
enabled
■
disabled
■
transition_on
■
transition_off
The timer value is 0 when the resource is enabled or disabled and nonzero during state transition. The timer is loaded with the time_on
or time_off value of the resource when the PMU determines that the resource must be enabled or disabled. That timer decrements
on each 32.768 kHz PMU clock. When it reaches 0, the state changes from transition_off to disabled or transition_on to enabled. If
the time_on value is 0, the resource can transition immediately from disabled to enabled. Similarly, a time_off value of 0 indicates that
the resource can transition immediately from enabled to disabled. The terms enable sequence and disable sequence refer to either
the immediate transition or the timer load-decrement sequence.
During each clock cycle, the PMU sequencer performs the following actions:
■
Computes the required resource set based on requests and the resource dependency table.
■
Decrements all timers whose values are nonzero. If a timer reaches 0, the PMU clears the ResourcePending bit for the resource
and inverts the ResourceState bit.
■
Compares the request with the current resource status and determines which resources must be enabled or disabled.
■
Initiates a disable sequence for each resource that is enabled, no longer being requested, and has no powered-up dependents.
■
Initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled.
Document Number: 002-14781 Rev. *E
Page 9 of 56
PRELIMINARY
CYW43364
2.5 Power-Off Shutdown
The CYW43364 provides a low-power shutdown feature that allows the device to be turned off while the host, and any other devices
in the system, remain operational. When the CYW43364 is not needed in the system, VDDIO_RF and VDDC are shut down while
VDDIO remains powered. This allows the CYW43364 to be effectively off while keeping the I/O pins powered so that they do not draw
extra current from any other devices connected to the I/O.
During a low-power shutdown state, provided VDDIO remains applied to the CYW43364, all outputs are tristated, and most input
signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths
or create loading on any digital signals in the system, and enables the CYW43364 to be fully integrated in an embedded device and
to take full advantage of the lowest power-savings modes.
When the CYW43364 is powered on from this state, it is the same as a normal power-up, and the device does not retain any
information about its state from before it was powered down.
2.6 Power-Up/Power-Down/Reset Circuits
The CYW43364 has two signals (see Table 2) that enable or disable the WLAN circuits and the internal regulator blocks, allowing the
host to control power consumption. For timing diagrams of these signals and the required power-up sequences, see Section 14.: “Power‐
Up Sequence and Timing,” on page 50.
Table 2. Power-Up/Power-Down/Reset Control Signals
Signal
WL_REG_ON
Description
This signal is used by the PMU to power-up the WLAN section. When this pin is high, the regulators are enabled
and the WLAN section is out of reset. When this pin is low, the WLAN section is in reset. This pin has an
internal 200 kΩ pull-down resistor that is enabled by default. It can be disabled through programming.
Document Number: 002-14781 Rev. *E
Page 10 of 56
PRELIMINARY
CYW43364
3. Frequency References
An external crystal is used for generating all radio frequencies and normal operation clocking. As an alternative, an external frequency
reference driven by a temperature-compensated crystal oscillator (TCXO) signal may be used. No software settings are required to
differentiate between the two. In addition, a low-power oscillator (LPO) is provided for lower power mode timing.
3.1 Crystal Interface and Clock Generation
The CYW43364 can use an external crystal to provide a frequency reference. The recommended configuration for the crystal oscillator,
including all external components, is shown in Figure 5. Consult the reference schematics for the latest configuration.
Figure 5. Recommended Oscillator Configuration
C
WLRF_XTAL_XOP
12 – 27 pF
C
12 – 27 pF
R
WLRF_XTAL_XON
Note: Resistor value determined by crystal
drive level. See reference schematics for
details.
The CYW43364 uses a fractional-N synthesizer to generate the radio frequencies, clocks, and data/packet timing so that it can operate
using numerous frequency references. The frequency reference can be an external source such as a TCXO or a crystal interfaced
directly to the CYW43364.
The default frequency reference setting is a 37.4 MHz crystal or TCXO. The signal requirements and characteristics for the crystal
interface are shown in Table 3 on page 12.
Note: Although the fractional-N synthesizer can support many reference frequencies, frequencies other than the default require
support to be added in the driver, plus additional extensive system testing. Contact Cypress for further details.
Document Number: 002-14781 Rev. *E
Page 11 of 56
PRELIMINARY
CYW43364
3.2 TCXO
As an alternative to a crystal, an external precision TCXO can be used as the frequency reference, provided that it meets the phase
noise requirements listed in Table 3 on page 12.
If the TCXO is dedicated to driving the CYW43364, it should be connected to the WLRF_XTAL_XOP pin through an external capacitor
with value ranges from 200 pF to 1000 pF as shown in Figure 6.
Figure 6. Recommended Circuit to Use with an External Dedicated TCXO
200 pF – 1000 pF
TCXO
WLRF_XTAL_XOP
NC
WLRF_XTAL_XON
Table 3. Crystal Oscillator and External Clock Requirements and Performance
Parameter
External Frequency Reference
Crystal
Conditions/Notes
Units
Min.
Typ.
Max.
Min.
Typ.
Max.
Frequency
–
–
37.4a
–
–
–
–
MHz
Crystal load capacitance
–
–
12
–
–
–
–
pF
ESR
–
–
–
60
–
–
–
Ω
Input Impedance
(WLRF_XTAL_XOP)
Resistive
–
–
–
10k
100k
–
Ω
Capacitive
–
–
–
–
–
7
pF
WLRF_XTAL_XOP input
voltage
AC-coupled analog signal
–
–
–
400b
–
1260
mVp-p
WLRF_XTAL_XOP input
low level
DC-coupled digital signal
–
–
–
0
–
0.2
V
WLRF_XTAL_XOP input
high level
DC-coupled digital signal
–
–
–
1.0
–
1.26
V
Frequency tolerance
Initial + over temperature
–
–20
–
20
–20
–
20
ppm
Duty cycle
37.4 MHz clock
–
–
–
40
50
60
%
Phase Noisec, d, e
(IEEE 802.11 b/g)
37.4 MHz clock at 10 kHz offset
–
–
–
–
–
–129
dBc/Hz
37.4 MHz clock at 100 kHz offset
–
–
–
–
–
–136
dBc/Hz
c, d, e
Phase Noise
(IEEE 802.11n, 2.4 GHz)
37.4 MHz clock at 10 kHz offset
–
–
–
–
–
–134
dBc/Hz
37.4 MHz clock at 100 kHz offset
–
–
–
–
–
–141
dBc/Hz
Phase Noisec, d, e
(256-QAM)
37.4 MHz clock at 10 kHz offset
–
–
–
–
–
–140
dBc/Hz
37.4 MHz clock at 100 kHz offset
–
–
–
–
–
–147
dBc/Hz
a.
b.
c.
d.
e.
The frequency step size is approximately 80 Hz. The CYW43364 does not auto-detect the reference clock frequency; the frequency is specified in the software
and/or NVRAM file.
To use 256-QAM, a 800 mV minimum voltage is required.
For a clock reference other than 37.4 MHz, 20 × log10(f/37.4) dB should be added to the limits, where f = the reference clock frequency in MHz.
Phase noise is assumed flat above 100 kHz.
The CYW43364 supports a 26 MHz reference clock sharing option. See the phase noise requirement in the table.
Document Number: 002-14781 Rev. *E
Page 12 of 56
PRELIMINARY
CYW43364
3.3 External 32.768 kHz Low-Power Oscillator
The CYW43364 uses a secondary low-frequency sleep clock for low-power mode timing. Either the internal low-precision LPO or an
external 32.768 kHz precision oscillator is required. The internal LPO frequency range is approximately 33 kHz ± 30% over process,
voltage, and temperature, which is adequate for some applications. However, one trade-off caused by this wide LPO tolerance is a
small current consumption increase during power save mode that is incurred by the need to wake up earlier to avoid missing beacons.
Whenever possible, the preferred approach is to use a precision external 32.768 kHz clock that meets the requirements listed in Table
4 on page 13.
Note: The CYW43364 will auto-detect the LPO clock. If it senses a clock on the EXT_SLEEP_CLK pin, it will use that clock. If it
doesn't sense a clock, it will use its own internal LPO.
■
To use the internal LPO: Tie EXT_SLEEP_CLK to ground. Do not leave this pin floating.
■
To use an external LPO: Connect the external 32.768 kHz clock to EXT_SLEEP_CLK.
Table 4. External 32.768 kHz Sleep-Clock Specifications
Parameter
LPO Clock
Units
Nominal input frequency
32.768
kHz
Frequency accuracy
±200
ppm
Duty cycle
30–70
%
Input signal amplitude
200–3300
Signal type
Square wave or sine wave
Input impedancea
Clock jitter
>100
NoPull
SDIO MODE -> NoPull
SDIO MODE -> PU
SDIO MODE ->
NoPull
Input; PU
WCC_VDDIO
SDIO_DATA_1
I/O
N
SDIO MODE -> NoPull
SDIO MODE -> NoPull
SDIO MODE -> NoPull
SDIO MODE -> PU
SDIO MODE ->
NoPull
Input; PU
WCC_VDDIO
SDIO_DATA_2
I/O
N
SDIO MODE -> NoPull
SDIO MODE -> NoPull
SDIO MODE -> NoPull
SDIO MODE -> PU
SDIO MODE ->
NoPull
Input; PU
WCC_VDDIO
SDIO_DATA_3
I/O
N
SDIO MODE -> NoPull
SDIO MODE -> NoPull
SDIO MODE -> NoPull
SDIO MODE -> PU
SDIO MODE ->
NoPull
Input; PU
WCC_VDDIO
SDIO_CMD
I/O
N
SDIO MODE -> NoPull
SDIO MODE -> NoPull
SDIO MODE -> NoPull
SDIO MODE -> PU
SDIO MODE ->
NoPull
Input; PU
WCC_VDDIO
SDIO_CLK
I
N
SDIO MODE -> NoPull
SDIO MODE -> NoPull
SDIO MODE -> NoPull
SDIO MODE -> NoPull SDIO MODE ->
NoPull
Input
WCC_VDDIO
JTAG_SEL
I
Y
PD
PD
High-Z, NoPull
Input, PD
PD
Input, PD
WCC_VDDIO
Input, SDIO OOB Int,
NoPull
Active mode
Input, NoPull
WCC_VDDIO
Input, PD
Active mode
Input, Strap, PD
WCC_VDDIO
Input, GCI GPIO[7],
NoPull
Active mode
Input, Strap,
NoPull
WCC_VDDIO
a
GPIO_0
I/O
Y
TBD
Active mode
High-Z, NoPull
GPIO_1
I/O
Y
TBD
Active mode
High-Z, NoPulla
a
GPIO_2
I/O
Y
TBD
Active mode
High-Z, NoPull
GPIO_3
I/O
Y
TBD
Active mode
High-Z, NoPulla
Input, GCI GPIO[0], PU Active mode
Input, PU
WCC_VDDIO
Active mode
a
Input, GCI GPIO[1], PU Active mode
Input, PU
WCC_VDDIO
GPIO_4
I/O
Y
TBD
Document Number: 002-14781 Rev. *E
High-Z, NoPull
Page 31 of 56
PRELIMINARY
CYW43364
Table 11. I/O States (Cont.)
Name
I/O Keeper
Active Mode
Low Power State/
Sleep
(All Power Present)
Power-down
(WL_REG_ON=0
BT_REG_ON=don’t
care)
Out-of-Reset;
(WL_REG_ON=1;
BT_REG_ON=don’t
care)
(WL_REG_ON=0
and
(WL_REG_ON=1 and
BT_REG_ON=0) and BT_REG_ON=1)
VDDIOs are Present and VDDIOs are
Present
Power
Rail
Note:
1. Keeper column: N = pad has no keeper. Y = pad has a keeper. Keeper is always active except in the Power-down state.
2. If there is no keeper, and it is an input and there is Nopull, then the pad should be driven to prevent leakage due to a floating pad (e.g., SDIO_CLK).
3. In the Power-down state (xx_REG_ON = 0): High-Z; NoPull => The pad is disabled because power is not supplied.
4. Depending on whether the PCM interface is enabled and the configuration is master or slave mode, it can be either an output or input.
5. Depending on whether the I2S interface is enabled and the configuration is master or slave mode, it can be either an output or input.
6. The GPIO pull states for the Active and Low-Power states are hardware defaults. They can all be subsequently programmed as pull-ups or pull-downs.
7. Regarding GPIO pins, the following are the pull-up and pull-down values for both 3.3V and 1.8V VDDIO:
3.3V VDDIO pull-downs:
3.3V VDDIO pull-ups:
1.8V VDDIO pull-downs:
1.8V VDDIO pull-ups:
Minimum (kΩ)
51.5
37.4
64
65
Typical (kΩ)
44.5
39.5
83
86
Maximum (kΩ)
38
44.5
116
118
a. The GPIO pull states for the active and low-power states are hardware defaults. They can all be subsequently programmed as a pull-up or pull-down.
Document Number: 002-14781 Rev. *E
Page 32 of 56
PRELIMINARY
CYW43364
9. DC Characteristics
Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization.
9.1 Absolute Maximum Ratings
Caution: The absolute maximum ratings in Table 12 indicate levels where permanent damage to the device can occur, even if these
limits are exceeded for only a brief duration. Functional operation is not guaranteed under these conditions. Excluding VBAT,
operation at the absolute maximum conditions for extended periods can adversely affect long-term reliability of the device.
Table 12. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
a
V
DC supply for VBAT and PA driver supply
VBAT
–0.5 to +6.0
DC supply voltage for digital I/O
VDDIO
–0.5 to 3.9
V
DC supply voltage for RF switch I/Os
VDDIO_RF
–0.5 to 3.9
V
DC input supply voltage for CLDO and LNLDO
–
–0.5 to 1.575
V
DC supply voltage for RF analog
VDDRF
–0.5 to 1.32
V
DC supply voltage for core
VDDC
–0.5 to 1.32
V
Vundershoot
–0.5
V
Vovershoot
VDDIO + 0.5
V
Tj
125
°C
Maximum undershoot voltage for I/O
Maximum overshoot voltage for I/O
b
b
Maximum junction temperature
a.
b.
Continuous operation at 6.0V is supported.
Duration not to exceed 25% of the duty cycle.
9.2 Environmental Ratings
The environmental ratings are shown in Table 13.
Table 13. Environmental Ratings
Characteristic
Units
Conditions/Comments
Ambient temperature (TA)
–30 to +70°C
a
C
Operation
Storage temperature
–40 to +125°C
C
–
Relative humidity
a.
Value
Less than 60
%
Storage
Less than 85
%
Operation
Functionality is guaranteed, but specifications require derating at extreme temperatures (see the specification tables for details).
Document Number: 002-14781 Rev. *E
Page 33 of 56
PRELIMINARY
CYW43364
9.3 Electrostatic Discharge Specifications
Extreme caution must be exercised to prevent electrostatic discharge (ESD) damage. Proper use of wrist and heel grounding straps
to discharge static electricity is required when handling these devices. Always store unused material in its antistatic packaging.
Table 14. ESD Specifications
Pin Type
Symbol
ESD, Handling Reference:
NQY00083, Section 3.4, Group ESD_HAND_HBM
D9, Table B
Machine Model (MM)
CDM
Condition
ESD Rating
Unit
Human Body Model Contact Discharge
per JEDEC EID/JESD22-A114
1250
V
ESD_HAND_MM
Machine Model Contact
50
V
ESD_HAND_CDM
Charged Device Model Contact
Discharge per JEDEC EIA/JESD22C101
300
V
9.4 Recommended Operating Conditions and DC Characteristics
Functional operation is not guaranteed outside the limits shown in Table 15, and operation outside these limits for extended periods
can adversely affect long-term reliability of the device.
Table 15. Recommended Operating Conditions and DC Characteristics
Element
DC supply voltage for VBAT
DC supply voltage for core
DC supply voltage for RF blocks in chip
DC supply voltage for digital I/O
DC supply voltage for RF switch I/Os
External TSSI input
Internal POR threshold
SDIO Interface I/O Pins
For VDDIO_SD = 1.8V:
Input high voltage
Input low voltage
Output high voltage @ 2 mA
Output low voltage @ 2 mA
For VDDIO_SD = 3.3V:
Input high voltage
Input low voltage
Output high voltage @ 2 mA
Output low voltage @ 2 mA
Other Digital I/O Pins
For VDDIO = 1.8V:
Input high voltage
Input low voltage
Output high voltage @ 2 mA
Output low voltage @ 2 mA
For VDDIO = 3.3V:
Document Number: 002-14781 Rev. *E
Symbol
Value
Unit
Minimum
3.0a
1.14
1.14
Typical
–
1.2
1.2
Maximum
4.8b
1.26
1.26
1.71
–
3.63
V
3.13
0.15
0.4
3.3
–
–
3.46
0.95
0.7
V
V
V
VIH
VIL
VOH
VOL
1.27
–
1.40
–
–
–
–
–
–
0.58
–
0.45
V
V
V
V
VIH
VIL
VOH
VOL
0.625 × VDDIO
–
0.75 × VDDIO
–
–
–
–
–
–
0.25 × VDDIO
–
0.125 × VDDIO
V
V
V
V
VIH
VIL
VOH
VOL
0.65 × VDDIO
–
VDDIO – 0.45
–
–
–
–
–
–
0.35 × VDDIO
–
0.45
V
V
V
V
VBAT
VDD
VDDRF
VDDIO,
VDDIO_SD
VDDIO_RF
TSSI
Vth_POR
V
V
V
Page 34 of 56
PRELIMINARY
CYW43364
Table 15. Recommended Operating Conditions and DC Characteristics (Cont.)
Element
Input high voltage
Input low voltage
Output high voltage @ 2 mA
Output low Voltage @ 2 mA
RF Switch Control Output Pinsc
For VDDIO_RF = 3.3V:
Output high voltage @ 2 mA
Output low voltage @ 2 mA
Input capacitance
a.
b.
c.
Symbol
Value
VIH
VIL
VOH
VOL
Minimum
2.00
–
VDDIO – 0.4
–
Typical
–
–
–
–
Maximum
–
0.80
–
0.40
VOH
VOL
CIN
VDDIO – 0.4
–
–
–
–
–
–
0.40
5
Unit
V
V
V
V
V
V
pF
The CYW43364 is functional across this range of voltages. However, optimal RF performance specified in the data sheet is guaranteed only for 3.2V < VBAT <
4.8V.
The maximum continuous voltage is 4.8V. Voltages up to 6.0V for up to 10 seconds, cumulative duration over the lifetime of the device are allowed. Voltages as
high as 5.0V for up to 250 seconds, cumulative duration over the lifetime of the device are allowed.
Programmable 2 mA to 16 mA drive strength. Default is 10 mA.
Document Number: 002-14781 Rev. *E
Page 35 of 56
PRELIMINARY
CYW43364
10. WLAN RF Specifications
The CYW43364 includes an integrated direct conversion radio that supports the 2.4 GHz band. This section describes the RF
characteristics of the 2.4 GHz radio.
Note: Values in this data sheet are design goals and may change based on device characterization results.
Unless otherwise stated, the specifications in this section apply when the operating conditions are within the limits specified in Table
13 on page 33 and Table 15 on page 34. Functional operation outside these limits is not guaranteed.
Typical values apply for the following conditions:
■
VBAT = 3.6V.
■
Ambient temperature +25°C.
Figure 16. RF Port Location
Chip
Port
C2
TX
Filter
Antenna
Port
10 pF
CYW43364
C1
L1
RX
4.7 nH
10 pF
Note: All specifications apply at the chip port unless otherwise specified.
10.1 2.4 GHz Band General RF Specifications
Table 16. 2.4 GHz Band General RF Specifications
Item
Condition
Minimum
Typical
Maximum
Unit
TX/RX switch time
Including TX ramp down
–
–
5
µs
RX/TX switch time
Including TX ramp up
–
–
2
µs
Document Number: 002-14781 Rev. *E
Page 36 of 56
PRELIMINARY
CYW43364
10.2 WLAN 2.4 GHz Receiver Performance Specifications
Note: Unless otherwise specified, the specifications in Table 17 are measured at the chip port (for the location of the chip port, see
Figure 16 on page 36).
Table 17. WLAN 2.4 GHz Receiver Performance Specifications
Parameter
Frequency range
Condition/Notes
Minimum
Typical
Maximum
Unit
–
2400
–
2500
MHz
1 Mbps DSSS
–97.5
–99.5
–
dBm
RX sensitivity (8% PER for 1024 2 Mbps DSSS
octet PSDU) a
5.5 Mbps DSSS
–93.5
–95.5
–
dBm
–91.5
–93.5
–
dBm
11 Mbps DSSS
–88.5
–90.5
–
dBm
6 Mbps OFDM
–91.5
–93.5
–
dBm
9 Mbps OFDM
–90.5
–92.5
–
dBm
12 Mbps OFDM
–87.5
–89.5
–
dBm
RX sensitivity (10% PER for 1000 18 Mbps OFDM
octet PSDU) at WLAN RF port a 24 Mbps OFDM
–85.5
–87.5
–
dBm
–82.5
–84.5
–
dBm
36 Mbps OFDM
–80.5
–82.5
–
dBm
48 Mbps OFDM
–76.5
–78.5
–
dBm
54 Mbps OFDM
–75.5
–77.5
–
dBm
20 MHz channel spacing for all MCS rates (Mixed mode)
256-QAM, R = 5/6
–67.5
–69.5
–
dBm
256-QAM, R = 3/4
–69.5
–71.5
–
dBm
MCS7
–71.5
–73.5
–
dBm
RX sensitivity
MCS6
(10% PER for 4096 octet PSDU).
MCS5
Defined for default parameters:
GF, 800 ns GI.
MCS4
–73.5
–75.5
–
dBm
–74.5
–76.5
–
dBm
–79.5
–81.5
–
dBm
MCS3
–82.5
–84.5
–
dBm
MCS2
–84.5
–86.5
–
dBm
MCS1
–86.5
–88.5
–
dBm
MCS0
–90.5
–92.5
–
dBm
Document Number: 002-14781 Rev. *E
Page 37 of 56
PRELIMINARY
CYW43364
Table 17. WLAN 2.4 GHz Receiver Performance Specifications (Cont.)
Parameter
Condition/Notes
Typical
Maximum
Unit
704–716
LTE
–
–13
–
dBm
777–787
LTE
–
–13
–
dBm
776–794 MHz
CDMA2000
–
–13.5
–
dBm
815–830
LTE
–
–12.5
–
dBm
816–824
CDMA2000
–
–13.5
–
dBm
816–849
LTE
–
–11.5
–
dBm
824–849
WCDMA
–
–11.5
–
dBm
824–849
CDMA2000
–
–12.5
–
dBm
824–849
LTE
–
–11.5
–
dBm
824–849
GSM850
–
–8
–
dBm
830–845
LTE
–
–11.5
–
dBm
832–862
LTE
–
–11.5
–
dBm
880–915
WCDMA
–
–10
–
dBm
LTE
–
–12
–
dBm
E-GSM
–
–9
–
dBm
1710–1755
WCDMA
–
–13
–
dBm
1710–1755
LTE
–
–14.5
–
dBm
1710–1755
CDMA2000
–
–14.5
–
dBm
1710–1785
WCDMA
–
–13
–
dBm
1710–1785
LTE
–
–14.5
–
dBm
1710–1785
GSM1800
–
–12.5
–
dBm
1850–1910
GSM1900
–
–11.5
–
dBm
1850–1910
CDMA2000
–
–16
–
dBm
1850–1910
WCDMA
–
–13.5
–
dBm
1850–1910
LTE
–
–16
–
dBm
1850–1915
LTE
–
–17
–
dBm
1920–1980
WCDMA
–
–17.5
–
dBm
1920–1980
CDMA2000
–
–19.5
–
dBm
1920–1980
LTE
–
–19.5
–
dBm
LTE
–
–44
–
dBm
LTE
–
–43
–
dBm
Blocking level for 3 dB Rx sensitivity degradation (without
880–915
external filtering)
880–915
Blocking level for 3 dB Rx sensi2300–2400
tivity degradation (without
external filtering)
2500–2570
(cont.)
2570–2620
LTE
–
–34
–
dBm
WLAN
–
>–4
–
dBm
@ 1, 2 Mbps (8% PER, 1024 octets)
–6
–
–
dBm
@ 5.5, 11 Mbps (8% PER, 1024 octets)
–12
–
–
dBm
@ 6–54 Mbps (10% PER, 1000 octets)
–15.5
–
–
dBm
5G (WLAN)
Maximum receive level
@ 2.4 GHz
Minimum
Document Number: 002-14781 Rev. *E
Page 38 of 56
PRELIMINARY
CYW43364
Table 17. WLAN 2.4 GHz Receiver Performance Specifications (Cont.)
Parameter
Condition/Notes
Minimum
Typical
Maximum
Unit
Adjacent channel rejectionDSSS.
(Difference between interfering
and desired signal [25 MHz
11 Mbps DSSS
apart] at 8% PER for 1024 octet
PSDU with desired signal level
as specified in Condition/Notes.)
–70 dBm
35
–
–
dB
6 Mbps OFDM
–79 dBm
16
–
–
dB
9 Mbps OFDM
–78 dBm
15
–
–
dB
12 Mbps OFDM
–76 dBm
13
–
–
dB
18 Mbps OFDM
–74 dBm
11
–
–
dB
24 Mbps OFDM
–71 dBm
8
–
–
dB
36 Mbps OFDM
–67 dBm
4
–
–
dB
Adjacent channel rejectionOFDM.
(Difference between interfering
and desired signal (25 MHz
apart) at 10% PER for 1000b
octet PSDU with desired signal
level as specified in Condition/
Notes.)
RCPI accuracyc
Return loss
a.
b.
c.
48 Mbps OFDM
–63 dBm
0
–
–
dB
54 Mbps OFDM
–62 dBm
–1
–
–
dB
65 Mbps OFDM
–61 dBm
–2
–
–
dB
Range –98 dBm to –75 dBm
–3
–
3
dB
Range above –75 dBm
–5
–
5
dB
Zo = 50Ω across the dynamic range.
10
–
–
dB
Optimal RF performance, as specified in this data sheet, is guaranteed only for temperatures between –10°C and 55°C.
For 65 Mbps, the size is 4096.
The minimum and maximum values shown have a 95% confidence level.
Document Number: 002-14781 Rev. *E
Page 39 of 56
PRELIMINARY
CYW43364
10.3 WLAN 2.4 GHz Transmitter Performance Specifications
Note: Unless otherwise specified, the specifications in Table 17 are measured at the chip port (for the location of the chip port, see
Figure 16 on page 36).
Table 18. WLAN 2.4 GHz Transmitter Performance Specifications
Parameter
Frequency range
Condition/Notes
–
Minimum
Typical
Maximum
Unit
2400
–
2500
MHz
776–794 MHz
CDMA2000
–
–167.5
–
dBm/Hz
869–960 MHz
CDMAOne, GSM850
–
–163.5
–
dBm/Hz
1450–1495
DAB
–
–154.5
–
dBm/Hz
1570–1580 MHz
GPS
–
–152.5
–
dBm/Hz
1592–1610 MHz
GLONASS
–
–149.5
–
dBm/Hz
1710–1800
DSC-1800-Uplink
–
–145.5
–
dBm/Hz
1805–1880 MHz
GSM 1800
–
–143.5
–
dBm/Hz
1850–1910 MHz
GSM 1900
–
–140.5
–
dBm/Hz
1910–1930 MHz
TDSCDMA,LTE
–
–138.5
–
dBm/Hz
1930–1990 MHz
GSM1900, CDMAOne,
WCDMA
–
–139
–
dBm/Hz
2010–2075 MHz
TDSCDMA
–
–127.5
–
dBm/Hz
2110–2170 MHz
WCDMA
–
–124.5
–
dBm/Hz
2305–2370
LTE Band 40
–
–104.5
–
dBm/Hz
2370–2400
LTE Band 40
–
–81.5
–
dBm/Hz
2496–2530
LTE Band 41
–
–94.5
–
dBm/Hz
2530–2560
LTE Band 41
–
–120.5
–
dBm/Hz
2570–2690
LTE Band 41
–
–121.5
–
dBm/Hz
5000–5900
WLAN 5G
–
–109.5
–
dBm/Hz
4.8-5.0 GHz
2nd Harmonic
–
–26.5
–
dBm/
MHz
Harmonic level (at 21 dBm with
7.2-7.5 GHz
90% duty cycle, 1 Mbps CCK)
3rd Harmonic
–
–23.5
–
dBm/
MHz
9.6-10 GHz
4th Harmonic
–
–32.5
–
dBm/
MHz
Transmitted power in cellular
and WLAN 5G band (at 21
dBm, 90% duty cycle, 1 Mbps
CCK).
EVM Does Not Exceed
IEEE 802.11b
(DSSS/CCK)
–9 dB
21
–
–
dBm
OFDM, BPSK
–8 dB
20.5
–
–
dBm
–13 dB
20.5
–
–
dBm
–19 dB
20.5
–
–
dBm
–25 dB
18
–
–
dBm
–27 dB
17.5
–
–
dBm
15
–
–
dBm
TX power at the chip port for the OFDM, QPSK
highest power level setting at
OFDM, 16-QAM
25°C, VBA = 3.6V, and spectral
mask and EVM compliancea, b OFDM, 64-QAM
(R = 3/4)
OFDM, 64-QAM
(R = 5/6)
OFDM, 256-QAM (R
–32 dB
= 5/6)
Document Number: 002-14781 Rev. *E
Page 40 of 56
PRELIMINARY
CYW43364
Table 18. WLAN 2.4 GHz Transmitter Performance Specifications (Cont.)
Parameter
Condition/Notes
Minimum
Typical
Maximum
Unit
–
9
–
–
dB
Closed loop TX power variation Across full temperature and voltage range.
at highest power level setting
Applies across 5 to 21 dBm output power range.
–
–
±1.5
dB
Carrier suppression
–
15
–
–
dBc
–
–
0.25
–
dB
4
6
–
dB
EVM degradation
–
3.5
–
dB
Output power variation
–
±2
–
dB
ACPR-compliant power
level
–
15
–
dBm
EVM degradation
–
4
–
dB
Output power variation
–
±3
–
dB
ACPR-compliant power
level
–
15
–
dBm
TX power control
dynamic range
Gain control step
Return loss
Zo = 50
VSWR = 2:1.
Load pull variation for output
power, EVM, and Adjacent
Channel Power Ratio (ACPR)
VSWR = 3:1.
a.
b.
TX power for channel 1 and channel 11 is specified separately by nonvolatile memory parameters to ensure band-edge compliance.
Optimal RF performance, as specified in this data sheet, is guaranteed only for temperatures between –10°C and 55°C.
10.4 General Spurious Emissions Specifications
Table 19. General Spurious Emissions Specifications
Parameter
Condition/Notes
Minimum
Typical
Maximum
Unit
–
2400
–
2500
MHz
Frequency range
General Spurious Emissions
TX emissions
RX/standby
emissions
30 MHz < f < 1 GHz
RBW = 100 kHz
–
–99
–96
dBm
1 GHz < f < 12.75 GHz
RBW = 1 MHz
–
–44
–41
dBm
1.8 GHz < f < 1.9 GHz
RBW = 1 MHz
–
–68
–65
dBm
5.15 GHz < f < 5.3 GHz
RBW = 1 MHz
–
–88
–85
dBm
30 MHz < f < 1 GHz
RBW = 100 kHz
–
–99
–96
dBm
1 GHz < f < 12.75 GHz
RBW = 1 MHz
–
–54
–51
dBm
1.8 GHz < f < 1.9 GHz
RBW = 1 MHz
–
–88
–85
dBm
5.15 GHz < f < 5.3 GHz
RBW = 1 MHz
–
–88
–85
dBm
Note: The specifications in this table apply at the chip port.
Document Number: 002-14781 Rev. *E
Page 41 of 56
PRELIMINARY
CYW43364
11. Internal Regulator Electrical Specifications
Note: Values in this data sheet are design goals and are subject to change based on device characterization results.
Functional operation is not guaranteed outside of the specification limits provided in this section.
11.1 Core Buck Switching Regulator
Table 20. Core Buck Switching Regulator (CBUCK) Specifications
Specification
Notes
Input supply voltage (DC)
DC voltage range inclusive of disturbances.
PWM mode switching
frequency
CCM, load > 100 mA VBAT = 3.6V.
Min.
Typ.
Max.
2.4
3.6
a
Units
4.8
V
–
4
–
MHz
PWM output current
–
–
–
370
mA
Output current limit
–
–
1400
–
mA
Output voltage range
Programmable, 30 mV steps.
Default = 1.35V.
1.2
1.35
1.5
V
PWM output voltage
DC accuracy
Includes load and line regulation.
Forced PWM mode.
–4
–
4
%
PWM ripple voltage, static
Measure with 20 MHz bandwidth limit.
Static load, max. ripple based on VBAT = 3.6V,
Vout = 1.35V,
Fsw = 4 MHz, 2.2 μH inductor L > 1.05 μH, Cap +
Board total-ESR < 20 mΩ,
Cout > 1.9 μF, ESL
工商网监
湘ICP备2023018690号
