FM28V102A
1-Mbit (64 K × 16) F-RAM Memory
1-Mbit (64 K × 16) F-RAM Memory
Features
■
1-Mbit ferroelectric random access memory (F-RAM) logically
organized as 64 K × 16
❐ Configurable as 128 K × 8 using UB and LB
14
❐ High-endurance 100 trillion (10 ) read/writes
❐ 151-year data retention (see the Data Retention and
Endurance table)
❐ NoDelay™ writes
❐ Page mode operation to 30-ns cycle time
❐ Advanced high-reliability ferroelectric process
■
SRAM compatible
❐ Industry-standard 64 K × 16 SRAM pinout
❐ 60-ns access time, 90-ns cycle time
■
Superior to battery-backed SRAM modules
❐ No battery concerns
❐ Monolithic reliability
❐ True surface mount solution, no rework steps
❐ Superior for moisture, shock, and vibration
■
Low power consumption
❐ Active current 7 mA (typ)
❐ Standby current 120 A (typ)
❐ Sleep mode current 3 A (typ)
■
Low-voltage operation: VDD = 2.0 V to 3.6 V
■
Industrial temperature: –40 C to +85 C
■
44-pin thin small outline package (TSOP) Type II
■
Restriction of hazardous substances (RoHS) compliant
Functional Overview
The FM28V102A is a 64 K × 16 nonvolatile memory that reads
and writes similar to a standard SRAM. A ferroelectric random
access memory or F-RAM is nonvolatile, which means that data
is retained after power is removed. It provides data retention for
over 151 years while eliminating the reliability concerns,
functional disadvantages, and system design complexities of
battery-backed SRAM (BBSRAM). Fast write timing and high
write endurance make the F-RAM superior to other types of
memory.
The FM28V102A operation is similar to that of other RAM
devices and therefore, it can be used as a drop-in replacement
for a standard SRAM in a system. Read cycles may be triggered
by CE or simply by changing the address and write cycles may
be triggered by CE or WE. The F-RAM memory is nonvolatile
due to its unique ferroelectric memory process. These features
make the FM28V102A ideal for nonvolatile memory applications
requiring frequent or rapid writes.
The device is available in a 400-mil 44-pin TSOP-II
surface mount package. Device specifications are guaranteed
over the industrial temperature range –40 °C to +85 °C.
For a complete list of related documentation, click here.
A 1-0
64 K x 16
F-RAM Array
...
A 15-2
Address Latch
A 15-0
Row Decoder
Logic Block Diagram
...
CE
Column Decoder
UB, LB
WE
OE
I/O Latch & Bus Driver
Control
Logic
DQ 15-0
ZZ
Cypress Semiconductor Corporation
Document Number: 001-91080 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 12, 2015
FM28V102A
Contents
Pinout ................................................................................ 3
Pin Definitions .................................................................. 3
Device Operation .............................................................. 4
Memory Operation ....................................................... 4
Read Operation ........................................................... 4
Write Operation ........................................................... 4
Page Mode Operation ................................................. 4
Pre-charge Operation .................................................. 4
Sleep Mode ................................................................. 4
SRAM Drop-In Replacement ....................................... 5
Endurance ................................................................... 6
Maximum Ratings ............................................................. 7
Operating Range ............................................................... 7
DC Electrical Characteristics .......................................... 7
Data Retention and Endurance ....................................... 8
Capacitance ...................................................................... 8
Thermal Resistance .......................................................... 8
AC Test Conditions .......................................................... 8
Document Number: 001-91080 Rev. *E
AC Switching Characteristics ......................................... 9
SRAM Read Cycle ...................................................... 9
SRAM Write Cycle ..................................................... 10
Power Cycle and Sleep Mode Timing ........................... 14
Functional Truth Table ................................................... 15
Byte Select Truth Table .................................................. 15
Ordering Information ...................................................... 16
Ordering Code Definitions ......................................... 16
Package Diagram ............................................................ 17
Acronyms ........................................................................ 18
Document Conventions ................................................. 18
Units of Measure ....................................................... 18
Document History Page ................................................. 19
Sales, Solutions, and Legal Information ...................... 20
Worldwide Sales and Design Support ....................... 20
Products .................................................................... 20
PSoC® Solutions ...................................................... 20
Cypress Developer Community ................................. 20
Technical Support ..................................................... 20
Page 2 of 20
FM28V102A
Pinout
Figure 1. 44-pin TSOP II pinout
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
VDD
VSS
DQ4
DQ5
DQ6
DQ7
WE
VSS
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44-pin TSOP II
(× 16)
Top View
(not to scale)
A5
A6
A7
OE
UB
44
43
42
41
40
39
38
37
36
35
34
33
32
31
LB
DQ15
DQ14
DQ13
DQ12
VSS
VDD
DQ11
DQ10
30
29
28
27
26
25
24
23
DQ9
DQ8
ZZ
A8
A9
A10
A11
NC
Pin Definitions
Pin Name
I/O Type
Description
A15–A0
Input
Address inputs: The 16 address lines select one of 64K words in the F-RAM array. The lowest two
address lines A1–A0 may be used for page mode read and write operations.
DQ15–DQ0 Input/Output Data I/O Lines: 16-bit bidirectional data bus for accessing the F-RAM array.
WE
Input
Write Enable: A write cycle begins when WE is asserted. The rising edge causes the FM28V102A to
write the data on the DQ bus to the F-RAM array. The falling edge of WE latches a new column address
for page mode write cycles.
CE
Input
Chip Enable: The device is selected and a new memory access begins on the falling edge of CE. The
entire address is latched internally at this point. Subsequent changes to the A1–A0 address inputs allow
page mode operation.
OE
Input
Output Enable: When OE is LOW, the FM28V102A drives the data bus when the valid read data is
available. Deasserting OE HIGH tristates the DQ pins.
UB
Input
Upper Byte Select: Enables DQ15–DQ8 pins during reads and writes. These pins are HI-Z if UB is HIGH.
If the user does not perform byte writes and the device is not configured as a 128 K × 8, the UB and LB
pins may be tied to ground.
LB
Input
Lower Byte Select: Enables DQ7–DQ0 pins during reads and writes. These pins are HI-Z if LB is HIGH.
If the user does not perform byte writes and the device is not configured as a 128 K × 8, the UB and LB
pins may be tied to ground.
ZZ
Input
Sleep: When ZZ is LOW, the device enters a low-power sleep mode for the lowest supply current
condition. ZZ must be HIGH for a normal read/write operation. This pin must be tied to VDD if not used.
VSS
Ground
VDD
NC
Ground for the device. Must be connected to the ground of the system.
Power supply Power supply input to the device.
No connect
No connect. This pin is not connected to the die.
Document Number: 001-91080 Rev. *E
Page 3 of 20
FM28V102A
Device Operation
The FM28V102A is a word wide F-RAM memory logically
organized as 65,536 × 16 and accessed using an
industry-standard parallel interface. All data written to the part is
immediately nonvolatile with no delay. The device offers page
mode operation, which provides high-speed access to
addresses within a page (row). Access to a different page
requires that either CE transitions LOW or the upper address
(A15–A2) changes. See the Functional Truth Table on page 15
for a complete description of read and write modes.
Memory Operation
Users access 65,536 memory locations, each with 16 data bits
through a parallel interface. The F-RAM array is organized as
16,384 rows each having 64 bits. Each row has four column
locations, which allow fast access in page mode operation.
When an initial address is latched by the falling edge of CE,
subsequent column locations may be accessed without the need
to toggle CE. When CE is deasserted HIGH, a pre-charge
operation begins. Writes occur immediately at the end of the
access with no delay. The WE pin must be toggled for each write
operation. The write data is stored in the nonvolatile memory
array immediately, which is a feature unique to F-RAM called
NoDelay writes.
Read Operation
A read operation begins on the falling edge of CE. The falling
edge of CE causes the address to be latched and starts a
memory read cycle if WE is HIGH. Data becomes available on
the bus after the access time is met. When the address is latched
and the access completed, a new access to a random location
(different row) may begin while CE is still LOW. The minimum
cycle time for random addresses is tRC. Note that unlike SRAMs,
the FM28V102A's CE-initiated access time is faster than the
address access time.
The FM28V102A will drive the data bus when OE and at least
one of the byte enables (UB, LB) is asserted LOW. The upper
data byte is driven when UB is LOW, and the lower data byte is
driven when LB is LOW. If OE is asserted after the memory
access time is met, the data bus will be driven with valid data. If
OE is asserted before completing the memory access, the data
bus will not be driven until valid data is available. This feature
minimizes supply current in the system by eliminating transients
caused by invalid data being driven to the bus. When OE is
deasserted HIGH, the data bus will remain in a HI-Z state.
Write Operation
In the FM28V102A, writes occur in the same interval as reads.
The FM28V102A supports both CE and WE controlled write
cycles. In both cases, the address A15–A2 is latched on the
falling edge of CE.
In a CE-controlled write, the WE signal is asserted before
beginning the memory cycle. That is, WE is LOW when CE falls.
In this case, the device begins the memory cycle as a write. The
FM28V102A will not drive the data bus regardless of the state of
OE as long as WE is LOW. Input data must be valid when CE is
Document Number: 001-91080 Rev. *E
deasserted HIGH. In a WE-controlled write, the memory cycle
begins on the falling edge of CE. The WE signal falls some time
later. Therefore, the memory cycle begins as a read. The data
bus will be driven if OE is LOW; however, it will be HI-Z when WE
is asserted LOW. The CE- and WE-controlled write timing cases
are shown in the Switching Waveforms on page 13.
Write access to the array begins on the falling edge of WE after
the memory cycle is initiated. The write access terminates on the
rising edge of WE or CE, whichever comes first. A valid write
operation requires the user to meet the access time specification
before deasserting WE or CE. The data setup time indicates the
interval during which data cannot change before the end of the
write access (rising edge of WE or CE).
Unlike other nonvolatile memory technologies, there is no write
delay with F-RAM. Because the read and write access times of
the underlying memory are the same, the user experiences no
delay through the bus. The entire memory operation occurs in a
single bus cycle. Data polling, a technique used with EEPROMs
to determine if a write is complete, is unnecessary.
Page Mode Operation
The F-RAM array is organized as 16,384 rows each having 64
bits. Each row has four column-address locations. Address
inputs A1–A0 define the column address to be accessed. An
access can start on any column address, and other column
locations may be accessed without the need to toggle the CE pin.
For fast access reads, after the first data byte is driven to the bus,
the column address inputs A1–A0 may be changed to a new
value. A new data byte is then driven to the DQ pins no later than
tAAP, which is less than half the initial read access time. For fast
access writes, the first write pulse defines the first write access.
While CE is LOW, a subsequent write pulse along with a new
column address provides a page mode write access.
Pre-charge Operation
The pre-charge operation is an internal condition in which the
memory state is prepared for a new access. Pre-charge is
user-initiated by driving the CE signal HIGH. It must remain
HIGH for at least the minimum pre-charge time, tPC.
Pre-charge is also activated by changing the upper addresses,
A15–A2. The current row is first closed before accessing the new
row. The device automatically detects an upper order address
change, which starts a pre-charge operation. The new address
is latched and the new read data is valid within the tAA address
access time; see Figure 6 on page 11. A similar sequence occurs
for write cycles; see Figure 11 on page 12. The rate at which
random addresses can be issued is tRC and tWC, respectively.
Sleep Mode
The device incorporates a sleep mode of operation, which allows
the user to achieve the lowest power supply current condition. It
enters a low-power sleep mode by asserting the ZZ pin LOW.
Read and write operations must complete before the ZZ pin
going LOW. When ZZ is LOW, all pins are ignored except the ZZ
pin. When ZZ is deasserted HIGH, there is some time delay
(tZZEX) before the user can access the device. If sleep mode is
not used, the ZZ pin must be tied to VDD
Page 4 of 20
FM28V102A
Note that if CE is tied to ground, the user must be sure WE is not
LOW at power-up or power-down events. If CE and WE are both
LOW during power cycles, data will be corrupted. Figure 4 shows
a pull-up resistor on WE, which will keep the pin HIGH during
power cycles, assuming the MCU/MPU pin tristates during the
reset condition.The pull-up resistor value should be chosen to
ensure the WE pin tracks VDD to a high enough value, so that
the current drawn when WE is LOW is not an issue. A 10-k
resistor draws 330 µA when WE is LOW and VDD = 3.3 V.
Figure 2. Sleep/Standby State Diagram
Power
Applied
CE HIGH,
ZZ HIGH
Standby
ZZ LOW
Initialize
CE LOW,
ZZ HIGH
CE HIGH,
ZZ HIGH
CE LOW,
ZZ HIGH
Normal
Operation
Figure 4. Use of Pull-up Resistor on WE
ZZ LOW
VDD
ZZ HIGH
Sleep
FM28V102A
CE
WE
SRAM Drop-In Replacement
The FM28V102A is designed to be a drop-in replacement for
standard asynchronous SRAMs. The device does not require CE
to toggle for each new address. CE may remain LOW indefinitely.
While CE is LOW, the device automatically detects address
changes and a new access begins. This functionality allows CE
to be grounded, similar to an SRAM. It also allows page mode
operation at speeds up to 33 MHz.
Figure 3 shows a pull-up resistor on CE, which will keep the pin
HIGH during power cycles, assuming the MCU / MPU pin
tristates during the reset condition. The pull-up resistor value
should be chosen to ensure the CE pin tracks VDD to a high
enough value, so that the current drawn when CE is LOW is not
an issue. A 10-k resistor draws 330 µA when CE is LOW and
VDD = 3.3 V
Figure 3. Use of Pull-up Resistor on CE
VDD
FM28V102A
OE
MCU / MPU
A 15-0
DQ15-0
For applications that require the lowest power consumption, the
CE signal should be active (LOW) only during memory accesses.
The FM28V102A draws supply current while CE is LOW, even if
addresses and control signals are static. While CE is HIGH, the
device draws no more than the maximum standby current, ISB.
The UB and LB byte select pins are active for both read and write
cycles. They may be used to allow the device to be wired as a
128 K × 8 memory. The upper and lower data bytes can be tied
together and controlled with the byte selects. Individual byte
enables or the next higher address line A16 may be available
from the system processor.
Figure 5. FM28V102A Wired as 128 K x 8
CE
MCU / MPU
WE
OE
OE
A 15-0
DQ 15-0
A
16
A
15-0
Document Number: 001-91080 Rev. *E
ZZ
CE
WE
UB
LB
A
15-0
1-Mbit F-RAM
FM28V102A
DQ
15-8
D
DQ
7-0
7-0
Page 5 of 20
FM28V102A
Endurance
14
The FM28V102A is capable of being accessed at least 10
times – reads or writes. An F-RAM memory operates with a read
and restore mechanism. Therefore, an endurance cycle is
applied on a row basis. The F-RAM architecture is based on an
array of rows and columns. Rows are defined by A15-2 and
column addresses by A1-0. The array is organized as 16K rows
of four words each. The entire row is internally accessed once
whether a single 16-bit word or all four words are read or written.
Each word in the row is counted only once in an endurance
calculation.
The user may choose to write CPU instructions and run them
from a certain address space. Table 1 shows endurance
calculations for a 256-byte repeating loop, which includes a
starting address, three-page mode accesses, and a CE
pre-charge. The number of bus clock cycles needed to complete
a four-word transaction is 4 + 1 at lower bus speeds, but 5 + 2 at
33 MHz due to initial read latency and an extra clock cycle to
Document Number: 001-91080 Rev. *E
satisfy the device's pre-charge timing constraint tPC. The entire
loop causes each byte to experience only one endurance cycle.
The F-RAM read and write endurance is virtually unlimited even
at a 33-MHz system bus clock rate.
Table 1. Time to Reach 100 Trillion Cycles for Repeating
256-byte Loop
Bus
Freq
(MHz)
Bus
256-byte
Cycle
Endurance Endurance
Transaction
Time
Cycles/sec Cycles/year
Time (s)
(ns)
Years to
Reach
1014
Cycles
33
30
10.56
94,690
2.98 x 1012
33.5
25
40
12.8
78,125
2.46 x 1012
40.6
10
100
28.8
34,720
1.09 x 1012
91.7
5
200
57.6
17,360
5.47 x 1011
182.8
Page 6 of 20
FM28V102A
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –55 C to +125 C
Maximum accumulated storage time
At 125 °C ambient temperature ................................. 1000 h
At 85 °C ambient temperature ................................ 10 Years
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Supply voltage on VDD relative to VSS ........–1.0 V to + 4.5 V
Voltage applied to outputs
in High Z state .................................... –0.5 V to VDD + 0.5 V
Input voltage .......... –1.0 V to + 4.5 V and VIN < VDD + 1.0 V
Transient voltage (< 20 ns) on
any pin to ground potential ................. –2.0 V to VCC + 2.0 V
Package power dissipation
capability (TA = 25 °C) ................................................. 1.0 W
Surface mount Pb soldering
temperature (3 seconds) ......................................... +260 C
DC output current (1 output at a time, 1s duration) .... 15 mA
Static discharge voltage
Human Body Model (AEC-Q100-002 Rev. E) ............... 2 kV
Charged Device Model (AEC-Q100-011 Rev. B) ......... 500 V
Latch-up current ................................................... > 140 mA
Operating Range
Range
Industrial
Ambient Temperature (TA)
VDD
–40 C to +85 C
2.0 V to 3.6 V
DC Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
Min
Typ [1]
Max
Unit
2.0
3.3
3.6
V
VDD
Power supply voltage
IDD
VDD supply current
VDD = 3.6 V, CE cycling at min. cycle time. All
inputs toggling at CMOS levels
(0.2 V or VDD – 0.2 V), all DQ pins unloaded.
–
7
12
mA
ISB
Standby current
VDD = 3.6 V, CE at VDD,
All other pins are static and at
CMOS levels
(0.2 V or VDD – 0.2 V), ZZ is HIGH
TA = 25 C
–
120
150
µA
TA = 85 C
–
–
250
µA
TA = 25 C
–
3
5
µA
TA = 85 C
–
–
8
µA
IZZ
Sleep mode current
VDD = 3.6 V, ZZ is LOW,
All other inputs VSS or VDD.
ILI
Input leakage current
VIN between VDD and VSS
–
–
+1
µA
ILO
Output leakage current
VOUT between VDD and VSS
–
–
+1
µA
VIH1
Input HIGH voltage
VDD = 2.7 V to 3.6 V
2.2
–
VDD + 0.3
V
VIH2
Input HIGH voltage
VDD = 2.0 V to 2.7 V
0.7 × VDD
–
–
V
VIL1
Input LOW voltage
VDD = 2.7 V to 3.6 V
– 0.3
–
0.8
V
VIL2
Input LOW voltage
VDD = 2.0 V to 2.7 V
– 0.3
–
0.3 × VDD
V
VOH1
Output HIGH voltage
IOH = –1 mA, VDD > 2.7 V
2.4
–
–
V
VOH2
Output HIGH voltage
IOH = –100 µA
VDD – 0.2
–
–
V
VOL1
Output LOW voltage
IOL = 2 mA, VDD > 2.7 V
–
–
0.4
V
VOL2
Output LOW voltage
IOL = 150 µA
–
–
0.2
V
Note
1. Typical values are at 25 °C, VDD = VDD (typ). Not 100% tested.
Document Number: 001-91080 Rev. *E
Page 7 of 20
FM28V102A
Data Retention and Endurance
Parameter
TDR
NVC
Description
Data retention
Endurance
Test condition
TA = 85 C
Min
Max
Unit
10
–
Years
TA = 75 C
38
–
TA = 65 C
151
–
Over operating temperature
1014
–
Cycles
Max
Unit
8
pF
Capacitance
Parameter
Description
Test Conditions
TA = 25 C, f = 1 MHz, VDD = VDD(Typ)
CI/O
Input/Output capacitance (DQ)
CIN
Input capacitance
6
pF
CZZ
Input capacitance of ZZ pin
8
pF
Thermal Resistance
Parameter
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
44-pin TSOP II Unit
107
C/W
25
C/W
AC Test Conditions
Input pulse levels ...................................................0 V to 3 V
Input rise and fall times (10%–90%) ........................... < 3 ns
Input and output timing reference levels ....................... 1.5 V
Output load capacitance ............................................... 30 pF
Document Number: 001-91080 Rev. *E
Page 8 of 20
FM28V102A
AC Switching Characteristics
Over the Operating Range
Parameters [2]
Cypress
Parameter
VDD = 2.0 V to 2.7 V
Description
Alt
Parameter
VDD = 2.7 V to 3.6 V
Min
Max
Min
Max
–
70
–
60
105
–
90
Unit
SRAM Read Cycle
tCE
tACE
Chip enable access time
ns
tRC
–
Read cycle time
tAA
–
Address access time, A15-2
–
105
–
90
ns
tOH
tOHA
Output hold time, A15-2
20
–
20
–
ns
tAAP
–
Page mode access time, A1-0
–
40
–
30
ns
tOHP
–
Page mode output hold time, A1-0
3
–
3
–
ns
tCA
–
Chip enable active time
70
–
60
–
ns
tPC
–
Pre-charge time
35
–
30
–
ns
tBA
tBW
UB, LB access time
–
25
–
15
ns
tAS
tSA
Address setup time (to CE LOW)
0
–
0
–
ns
tAH
tHA
Address hold time (CE Controlled)
70
–
60
–
ns
tOE
tDOE
Output enable access time
–
25
–
15
ns
tHZ[3, 4]
tHZCE
Chip Enable to output HI-Z
–
15
–
10
ns
tOHZ[3, 4]
tHZOE
Output enable HIGH to output HI-Z
–
15
–
10
ns
tBHZ[3, 4]
tHZBE
UB, LB HIGHHIGH to output HI-Z
–
15
–
10
ns
ns
Notes
2. Test conditions assume a signal transition time of 3 ns or less, timing reference levels of 0.5 × VDD, input pulse levels of 0 to 3 V, output loading of the specified
IOL/IOH and load capacitance shown in AC Test Conditions on page 8.
3. tHZ, tOHZ and tBHZ are specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state.
4. This parameter is characterized but not 100% tested.
Document Number: 001-91080 Rev. *E
Page 9 of 20
FM28V102A
AC Switching Characteristics (continued)
Over the Operating Range
Parameters [2]
Cypress
Parameter
VDD = 2.0 V to 2.7 V
Description
Alt
Parameter
VDD = 2.7 V to 3.6 V
Min
Max
Min
Max
Unit
SRAM Write Cycle
tWC
tWC
Write cycle time
105
–
90
–
ns
tCA
–
Chip enable active time
70
–
60
–
ns
tCW
tSCE
Chip enable to write enable HIGH
70
–
60
–
ns
tPC
–
Pre-charge time
35
–
30
–
ns
tPWC
–
Page mode write enable cycle time
40
–
30
–
ns
tWP
tPWE
Write enable pulse width
22
–
18
–
ns
tWP2
tBW
UB, LB pulse width
22
–
18
–
ns
tWP3
tPWE
WE LOW to UB, LB HIGH
22
–
18
–
ns
tAS
tSA
Address setup time (to CE LOW)
0
–
0
–
ns
tAH
tHA
Address hold time (CE Controlled)
70
–
60
–
ns
tASP
–
Page mode address setup time (to WE LOW)
8
–
5
–
ns
tAHP
–
Page mode address hold time (to WE LOW)
20
–
15
–
ns
tWLC
tPWE
Write enable LOW to chip disabled
30
–
25
–
ns
tBLC
tBW
UB, LB LOW to chip disabled
30
–
25
–
ns
tWLA
–
Write enable LOW to address change, A15-2
30
–
25
–
ns
tAWH
–
Address change to write enable HIGH, A15-2
105
–
90
–
ns
tDS
tSD
Data input setup time
20
–
15
–
ns
tHD
Data input hold time
0
–
0
–
ns
tHZWE
Write enable LOW to output HI-Z
–
10
–
10
ns
tWX[6]
–
Write enable HIGH to output driven
8
–
5
–
ns
tBDS
–
Byte disable setup time (to WE LOW)
8
–
5
–
ns
tBDH
–
Byte disable hold time (to WE HIGH)
8
–
5
–
ns
tDH
tWZ
[5, 6]
Notes
5. tWZ is specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state.
6. This parameter is characterized but not 100% tested.
Document Number: 001-91080 Rev. *E
Page 10 of 20
FM28V102A
Figure 6. Read Cycle Timing 1 (CE LOW, OE LOW)
tRC
tRC
A15-2
tOH
tAA
tAA
tOH
Previous Data
DQ
15-0
Valid Data
Valid Data
Figure 7. Read Cycle Timing 2 (CE Controlled)
tCA
tPC
CE
tAH
tAS
A 15-0
tOE
OE
tHZ
tCE
tOHZ
tOH
DQ 15-0
tBA
tBHZ
UB / LB
Figure 8. Page Mode Read Cycle Timing [7]
tPC
tCA
CE
tAS
A 15-2
Col 0
A1-0
Col 1
tAAP
tOE
OE
tHZ
tOHZ
tOHP
tCE
DQ15-0
Col 2
Data 0
Data 1
Data 2
Note
7. Although sequential column addressing is shown, it is not required.
Document Number: 001-91080 Rev. *E
Page 11 of 20
FM28V102A
Figure 9. Write Cycle Timing 1 (WE Controlled) [8]
tCA
tPC
tCW
CE
tAS
tWLC
A15-0
tWP
tWX
WE
DQ15-0
tWZ
tDH
tDS
D out
D in
tHZ
D out
Figure 10. Write Cycle Timing 2 (CE Controlled)
tCA
tPC
CE
tBLC
tAS
A15-0
WE
tDH
tDS
DQ
15-0
D in
UB/LB
Figure 11. Write Cycle Timing 3 (CE LOW) [8]
tWC
tAWH
A15-0
tWLA
tWX
WE
tWZ
tDS
DQ15-0
D out
D in
tDH
D out
D in
Note
8. OE (not shown) is LOW only to show the effect of WE on DQ pins.
Document Number: 001-91080 Rev. *E
Page 12 of 20
FM28V102A
Figure 12. Write Cycle Timing 4 (CE LOW) [9]
A15-0
tWP3
WE
tBDH
tBDS
tWP2
UB/LB
tDS
DQ15-0
tDH
tDS
D in
tDH
D in
Figure 13. Page Mode Write Cycle Timing
tCA
tPC
tCW
CE
tWLC
tAS
A15-2
tAHP
A 1-0
Col 0
tASP
Col 1
Col 2
tPWC
tWP
WE
OE
tDH
tDS
DQ15-0
Data 0
Data 1
Data 2
Note
9. UB and LB to show byte enable and byte masking cases.
Document Number: 001-91080 Rev. *E
Page 13 of 20
FM28V102A
Power Cycle and Sleep Mode Timing
Over the Operating Range
Parameter
tPU
tPD
tVR
[10]
Description
Min
Max
Unit
Power-up (after VDD min. is reached) to first access time
1
–
ms
Last write (WE HIGH) to power down time
0
–
µs
VDD power-up ramp rate
50
–
µs/V
tVF[10]
VDD power-down ramp rate
100
–
µs/V
tZZH
ZZ active to DQ HI-Z time
–
20
ns
tWEZZ
Last write to sleep mode entry time
0
–
µs
tZZL
ZZ active LOW time
1
–
µs
tZZEN
Sleep mode entry time (ZZ LOW to CE don’t care)
–
0
µs
–
450
µs
tZZEX
Sleep mode exit time (ZZ HIGH to
1st
access after wakeup)
Figure 14. Power Cycle and Sleep Mode Timing
VDD
t VR
t PU
CE
VDD min.
VDD min.
t ZZEN
t ZZEX
R/W
Allowed
t ZZEX
R/W
Allowed
t VF
R/W
Allowed
t ZZL
ZZ
t PD
t WEZZ
WE
t ZZH
DQ
D out
D in
Note
10. Slope measured at any point on the VDD waveform.
Document Number: 001-91080 Rev. *E
Page 14 of 20
FM28V102A
Functional Truth Table
Operation [11, 12]
CE
WE
A15-2
A1-0
ZZ
X
X
X
X
L
Sleep Mode
H
X
X
X
H
Standby/Idle
↓
H
H
V
V
V
V
H
H
Read
L
L
H
No Change
Change
H
Page Mode Read
L
H
Change
V
H
Random Read
↓
V
V
V
V
H
H
CE-Controlled Write[12]
L
L
L
L
↓
V
V
H
WE-Controlled Write [12, 13]
L
↓
No Change
V
H
Page Mode Write [14]
↑
X
X
X
X
X
X
H
H
Starts pre-charge
L
Byte Select Truth Table
Operation [15]
WE
OE
LB
UB
H
H
X
X
X
H
H
L
H
L
Read upper byte; HI-Z lower byte
L
H
Read lower byte; HI-Z upper byte
L
L
Read both bytes
H
L
Write upper byte; Mask lower byte
L
H
Write lower byte; Mask upper byte
L
L
Write both bytes
H
L
X
Read; Outputs disabled
Notes
11. H = Logic HIGH, L = Logic LOW, V = Valid Data, X = Don't Care, ↓ = toggle LOW, ↑ = toggle HIGH.
12. For write cycles, data-in is latched on the rising edge of CE or WE, whichever comes first.
13. WE-controlled write cycle begins as a Read cycle and then A15-2 is latched.
14. Addresses A1-0 must remain stable for at least 15 ns during page mode operation.
15. The UB and LB pins may be grounded if 1) the system does not perform byte writes and 2) the device is not configured as a 128 K x 8.
Document Number: 001-91080 Rev. *E
Page 15 of 20
FM28V102A
Ordering Information
Access
time
(ns)
60
Ordering Code
FM28V102A-TG
Package
Diagram
Package Type
51-85087 44-pin TSOP II
Operating
Range
Industrial
FM28V102A-TGTR
All the above parts are Pb-free.
Ordering Code Definitions
FM 28
V
102 A - TG TR
Option:
blank = Standard; TR = Tape and Reel
Package Type:
TG = 44-pin TSOP II
Die Revision: A
Density: 102 = 1-Mbit
Voltage: V = 2.0 V to 3.6 V
Parallel F-RAM
Cypress
Document Number: 001-91080 Rev. *E
Page 16 of 20
FM28V102A
Package Diagram
Figure 15. 44-pin TSOP Package Outline, 51-85087
51-85087 *E
Document Number: 001-91080 Rev. *E
Page 17 of 20
FM28V102A
Acronyms
Acronym
UB
Document Conventions
Description
Units of Measure
Upper Byte
Symbol
Unit of Measure
LB
Lower Byte
°C
CE
CMOS
Chip Enable
Hz
hertz
Complementary Metal Oxide Semiconductor
kHz
kilohertz
EIA
Electronic Industries Alliance
k
kilohm
F-RAM
Ferroelectric Random Access Memory
MHz
megahertz
I/O
Input/Output
A
microampere
OE
RoHS
Output Enable
F
microfarad
s
microsecond
RW
Read and Write
mA
milliampere
ms
millisecond
SRAM
Static Random Access Memory
M
megaohm
TSOP
Thin Small Outline Package
ns
nanosecond
WE
Write Enable
ohm
%
percent
pF
picofarad
V
volt
W
watt
Restriction of Hazardous Substances
Document Number: 001-91080 Rev. *E
degree Celsius
Page 18 of 20
FM28V102A
Document History Page
Document Title: FM28V102A, 1-Mbit (64 K × 16) F-RAM Memory
Document Number: 001-91080
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
**
4272603
GVCH
03/11/2014
New data sheet.
*A
4372700
GVCH
05/07/2014
Changed datasheet status from “Preliminary to Final”
Maximum Ratings: Static discharge voltage
Removed Machine Model
DC Electrical Characteristics:
Updated IZZ test condition
Updated Figure 6 for more clarity
Removed FM28V102A-TGES part
*B
4375244
GVCH
06/30/2014
Pin Definitions: ZZ pin
Added sentence: This pin must be tied to VDD if not used
Removed sentence: The ZZ pin is internally pulled up
DC Electrical Characteristics:Removed RIN spec
*C
4562106
GVCH
11/5/2014
Added related documentation hyperlink in page 1.
*D
4683470
GVCH
03/11/2015
Typo fixed (Features): Removed “Software-programmable block write-protect
feature”
*E
4881722
ZSK / PSR
08/12/2015
Updated Maximum Ratings:
Removed “Maximum junction temperature”.
Added “Maximum accumulated storage time”.
Added “Ambient temperature with power applied”.
Updated to new template.
Document Number: 001-91080 Rev. *E
Page 19 of 20
FM28V102A
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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Community | Forums | Blogs | Video | Training
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© Cypress Semiconductor Corporation, 2014-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-91080 Rev. *E
Revised August 12, 2015
All products and company names mentioned in this document may be the trademarks of their respective holders.
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