MB39A135
1ch DC/DC Converter IC with
PFM/PWM Synchronous Rectification
Description
MB39A135 is 1ch step-down DC/DC converter IC of the current mode N-ch/N-ch synchronous rectification method.
It contains the enhanced protection features, and supports the ceramic capacitor. MB39A135 realizes rapid response, high efficiency,
and low ripple voltage, and its high-frequency operation enables the miniaturization of inductor and I/O capacitors.
Features
High efficiency
For frequency setting by external resistor
: 100 kHz to 1 MHz
Error Amp threshold voltage
: 0.7 V 1.0 %
Minimum output voltage value
: 0.7 V
Wide range of power-supply voltage
: 4.5 V to 25 V
PFM/PWM auto switching mode and fixed PWM mode selectable
With built-in over voltage protection function
With built-in under voltage protection function
With built-in over current protection function
With built-in over-temperature protection function
With built-in soft start/stop circuit without load dependence
With built-in synchronous rectification type output steps for N-ch MOS FET
Standby current
: 0 A (Typ)
Small package
: TSSOP-16
Applications
Digital TV
Photocopiers
Surveillance cameras
Set-top boxes (STB)
DVD players, DVD recorders
Projectors
IP phones
Vending machines
Consoles and other non-portable devices
Cypress Semiconductor Corporation
Document Number: 002-08410 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 9, 2017
MB39A135
Contents
Description ............................................................................. 1
Features .................................................................................. 1
Applications ........................................................................... 1
1. Pin Assignment ................................................................ 3
2. Pin Descriptions ............................................................... 3
3. Block Diagram .................................................................. 4
4. Absolute Maximum Ratings ............................................ 5
5. Recommended Operating Conditions ............................ 6
6. Electrical Characteristics ................................................. 7
7. Typical Characteristics .................................................. 10
8. Function Description ...................................................... 12
8.1 Current Mode .......................................................... 12
9. Protection Function Table ............................................. 16
10. I/O Pin Equivalent Circuit Diagram ............................. 17
11. Example Application Circuit ........................................ 19
12. Parts List ....................................................................... 20
13. Application Note ........................................................... 21
13.1 Setting Method for PFM/PWM and Fixed
PWM Modes .............................................................. 21
13.2 Cautions at PFM/PWM Mode ................................ 21
13.3 Setting Method of Output Voltage ......................... 21
13.4 Oscillation Frequency Setting Method ................... 22
13.5 Setting Method of Soft-start time ........................... 23
Document Number: 002-08410 Rev. *C
13.6 Setting Method of Over Current Detection Value .. 24
13.7 Selection of Smoothing Inductor ........................... 25
13.8 Selection of SWFET .............................................. 26
13.9 Selection of Fly-back Diode ................................... 28
13.10 Selection of Output Capacitor ............................. 29
13.11 Selection of Input Capacitor ................................ 30
13.12 Selection of Boot Strap Diode ............................. 31
13.13 Selection of Boot Strap Capacitor ....................... 31
13.14 Design of Phase Compensation Circuit ............... 31
13.15 1pole-1zero Phase Compensation Circuit ........... 32
13.16 VB pin Capacitor ................................................. 33
13.17 VB Regulator ....................................................... 33
13.18 Power Dissipation and the Thermal Design ........ 34
13.19 Board Layout ....................................................... 35
14. Reference Data ............................................................. 36
15. Usage Precaution ......................................................... 38
16. Ordering Information .................................................... 38
17. RoHS Compliance Information .................................... 38
18. Package Dimensions .................................................... 39
19. Major Changes .............................................................. 40
Document History ................................................................ 41
Sales, Solutions, and Legal Information ........................... 42
Page 2 of 42
MB39A135
1. Pin Assignment
(TOP VIEW)
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2. Pin Descriptions
Pin No.
Pin Name
I/O
Description
PFM/PWM switch pin.
It becomes fixed PWM operation with the VREF connection, and it
becomes PFM/PWM operation with the GND connection.
1
MODE
I
2
RT
—
3
VREF
O
Reference voltage output pin.
4
CTL
I
Control pin.
5
PGND
—
Ground pin.
6
DRVL
O
Output pin for external low-side FET gate drive.
7
VB
O
Bias voltage output pin.
8
VCC
—
Power supply pin for reference voltage and control circuit.
9
LX
—
Inductor and external high-side FET source connection pin.
10
DRVH
O
Output pin for external high-side FET gate drive.
Resistor connection pin for oscillation frequency setting.
11
CB
—
The connection pin for boot strap capacitor.
12
GND
—
Ground pin.
13
CS
I
Soft-start time setting capacitor connection pin.
14
FB
I
Error amplifier inverted input pin.
15
COMP
O
Error amplifier (Error Amp) output pin.
16
ILIM
I
Over current detection level setting voltage input pin.
Document Number: 002-08410 Rev. *C
Page 3 of 42
MB39A135
3. Block Diagram
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Document Number: 002-08410 Rev. *C
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Page 4 of 42
MB39A135
4. Absolute Maximum Ratings
Parameter
Symbol
Condition
Rating
Min
Max
Unit
Power supply voltage
VVCC
VCC pin
—
27
V
CB pin input voltage
VCB
CB pin
—
32
V
LX pin input voltage
VLX
LX pin
—
27
V
Voltage between CB and LX
VCBLX
—
7
V
VI
CTL pin
—
27
V
VFB
FB pin
—
VVREF 0.3
V
V
ILIM pin
—
VVREF 0.3
V
VCS
CS pin
—
VVREF 0.3
V
VMODE
MODE pin
—
VVB 0.3
V
Output current
IOUT
DC,
DRVL pin,
DRVH pin
—
60
mA
Power dissipation
PD
Ta
—
1237
mW
55
150
°C
Control input voltage
Input voltage
Storage temperature
ILIM
TSTG
—
25°C
—
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in
excess of absolute maximum ratings. Do not exceed these ratings .
Document Number: 002-08410 Rev. *C
Page 5 of 42
MB39A135
5. Recommended Operating Conditions
Parameter
Symbol
Condition
Value
Min
Typ
Max
Unit
Power supply voltage
VVCC
—
4.5
—
25.0
V
CB pin input voltage
VCB
—
—
—
30
V
Reference voltage output
current
IVREF
—
100
—
—
A
IVB
—
1
—
—
mA
Bias output current
CTL pin input voltage
Input voltage
VI
CTL pin
0
—
25
V
VFB
FB pin
0
—
VVREF
V
VILIM
ILIM pin
0.3
—
1.94
V
VCS
CS pin
0
—
VVREF
V
MODE pin
0
—
VVREF
V
1200
—
1200
mA
kHz
VMODE
DRVH pin, DRVL pin
Duty 5%
(t ! 1 fOSC × Duty)
Peak output current
IOUT
Operation frequency range
fOSC
—
100
500
1000
Timing resistor
RRT
—
—
47
—
Soft start capacitor
CCS
—
0.0075
0.0180
—
F
CB pin capacitor
CCB
—
—
0.1
1.0
F
CVREF
—
—
0.1
1.0
F
Bias voltage output
capacitor
CVB
—
—
1.0
10
F
Operating ambient
temperature
Ta
—
30
25
85
°C
Reference voltage output
capacitor
WARNING:
k
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor
device. All of the device's electrical characteristics are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.
Users considering application outside the listed conditions are advised to contact their representatives beforehand.
Document Number: 002-08410 Rev. *C
Page 6 of 42
MB39A135
6. Electrical Characteristics
(Ta ! +25°C, VCC pin ! 15 V, CTL pin ! 5 V, VREF pin ! 0 A, VB pin ! 0 A)
Symbol
Pin
No.
Condition
Output voltage
VVREF
3
—
Input stability
VREF
LINE
3
Load stability
VREF
LOAD
Short-circuit
output current
Output voltage
Parameter
Reference
Voltage Block
[REF]
Input stability
Bias Voltage Block
[VB Reg.]
Load stability
Short-circuit
output current
Threshold voltage
Under voltage
Lockout Protection Hysteresis width
Circuit Block
Threshold voltage
[UVLO]
Hysteresis width
Soft-start /
Soft-stop Block
[Soft-Start,
Soft-Stop]
Clock
Generator Block
[OSC]
Value
Unit
Min
Typ
Max
3.24
3.30
3.36
V
VCC pin ! 4.5 V to 25 V
—
1
10
mV
3
VREF pin ! 0 A to
n100 A
—
1
10
mV
VREF
IOS
3
VREF pin ! 0 V
n14.5
n10.0
n7.5
mA
VVB
7
4.85
5.00
5.15
V
VB
LINE
7
VCC pin ! 6 V to 25 V
—
10
100
mV
VB
LOAD
7
VB pin ! 0 A to n1 mA
—
10
100
mV
VB
IOS
7
VB pin ! 0 V
n130
n90
n65
mA
VTLH1
7
VB pin
4.0
4.2
4.4
V
VTHL1
7
VB pin
3.4
3.6
3.8
V
—
VH1
7
VB pin
—
0.6*
—
V
VTLH2
3
VREF pin
2.7
2.9
3.1
V
VTHL2
3
VREF pin
2.5
2.7
2.9
V
VH2
3
VREF pin
—
0.2*
—
V
n7.9
n5.5
n4.2
A
Charge current
ICS
13
CTL pin ! 5 V,
CS pin ! 0 V
Soft-start
end voltage
VCS
13
CTL pin ! 5 V
2.2
2.4
2.6
V
Electrical discharge
resistance at
soft-stop
RDISCG
13
CTL pin ! 0 V,
CS pin ! 0.5 V
49
70
91
k
Soft-stop
end voltage
VDISCG
13
CTL pin ! 0 V
—
0.1*
—
V
Oscillation
frequency
fOSC
2
RT pin ! 47 k
450
500
550
kHz
Oscillation
frequency when
under voltage is
detected
fSHORT
2
RT pin ! 47 k
—
62.5
—
kHz
Frequency
Temperature
variation
df/dT
2
Ta ! n30°C to
—
3*
—
%
Document Number: 002-08410 Rev. *C
85°C
Page 7 of 42
MB39A135
(Ta ! +25°C, VCC pin ! 15 V, CTL pin ! 5 V, VREF pin ! 0 A, VB pin ! 0 A)
Parameter
Under-voltage
Protection
Circuit Block
[UVP Comp.]
Unit
Min
Typ
Max
—
0.693
0.700
0.707
V
n30°C to 85°C
FB pin ! 0 V
FB pin ! 0 V,
COMP pin ! 1 V
FB pin ! VREF pin, COMP
pin ! 1 V
FB pin ! 0 V,
ILIM pin ! 1.5 V
FB pin ! 0 V,
ILIM pin ! 1.5 V
0.689*
0.700*
0.711*
V
n0.1
0
+0.1
A
n390
n300
n210
A
8.4
12.0
16.8
mA
1.35
1.50
1.65
V
n1
0
+1
FB pin
0.776
0.805
0.835
49
70
91
0.450
0.490
0.531
V
—
512/
fOSC
—
s
EVTHT
14
IFB
14
ISOURCE
15
ISINK
15
Output clamp
voltage
VILIM
15
ILIM pin
input current
IILIM
16
Over-voltage
detecting voltage
VOVP
14
Over-voltage
detection time
tOVP
14
Under-voltage
detecting voltage
VUVP
14
Under-voltage
detection time
tUVP
14
TOTPH
—
Junction temperature
—
+160*
—
°C
TOTPL
—
Junction temperature
—
+135*
—
°C
Synchronous
rectification stop
voltage
VTHLX
9
LX pin
—
0*
—
mV
PFM/PWM mode
condition
VPFM
1
MODE pin
0
—
1.4
V
Fixed PWM mode
condition
VPWM
1
MODE pin
2.2
—
VVREF
V
MODE pin input
current
IMODE
1
MODE pin ! 0 V
n1
0
+1
A
Output current
Over-temperature
Protection
Detection
Circuit Block
temperature
[OTP]
PFM Control
Circuit Block
[MODE]
Value
14
Input current
Over-voltage
Protection
Circuit Block
[OVP Comp.]
Condition
EVTH
Threshold
voltage
Error Amp Block
[Error Amp]
Symbol Pin No.
Document Number: 002-08410 Rev. *C
Ta !
—
FB pin
—
A
V
s
Page 8 of 42
MB39A135
(Ta ! +25°C, VCC pin ! 15 V, CTL pin ! 5 V, VREF pin ! 0 A, VB pin ! 0 A)
Parameter
Symbol Pin No.
Typ
Max
Unit
10
DRVH pin ! n100 mA
—
4
7
RON_ML
10
DRVH pin ! 100 mA
—
1.0
3.5
Low-side
output on-resistance
RON_SH
6
DRVL pin ! n100 mA
—
4
7
RON_SL
6
DRVL pin ! 100 mA
—
0.75
1.70
LX pin ! 0 V,
CB pin ! 5 V
DRVH, DRVL pins ! 2.5 V
Duty 5%
—
n0.5*
—
A
10
LX pin ! 0 V,
CB pin ! 5 V
DRVH pin ! 2.5 V
Duty 5%
—
0.9*
—
A
6
LX pin ! 0 V,
CB pin ! 5 V
DRVL pin ! 2.5 V
Duty 5%
—
1.2*
—
A
COMP pin ! 1 V
—
250*
—
ns
75
80
—
%
LX pin ! 0 V,
CB pin ! 5 V
—
60
—
ns
VCC pin LX pin
—
220*
—
mV
Output sink current
ISOURCE
10,6
ISINK
Minimum on time
tON
10
Maximum on-duty
DMAX
10
tD
10, 6
Maximum current sense
voltage
VRANGE
9
Voltage conversion gain
ALV
9
—
5.4
6.8
8.2
V/V
Offset voltage at
voltage conversion
VIO
9
—
—
300
—
mV
Slope compensation
inclination
SLOPE
9
—
—
2*
—
V/V
LX pin input current
ILX
9
LX pin ! VCC pin
320
420
600
A
ON condition
VON
4
CTL pin
2
—
25
V
OFF condition
VOFF
4
CTL pin
0
—
0.8
V
VH
4
CTL pin
—
0.4*
—
V
ICTLH
4
CTL pin ! 5 V
—
25
40
A
ICTLL
4
CTL pin ! 0 V
—
0
1
A
Standby current
ICCS
8
CTL pin ! 0 V
—
0
10
A
Power-supply
current
ICC
8
LX pin ! 0 V,
FB pin ! 1.0 V
MODE pin ! VREF pin
—
1.9
2.7
mA
Dead time
Hysteresis width
Input current
General
Min
RON_MH
Output Block
[DRV]
Control Block
[CTL]
Value
High-side output
on-resistance
Output source
current
Level
Converter Block
[LVCNV]
Condition
—
* : This value isn't be specified. This should be used as a reference to support designing the circuits.
Document Number: 002-08410 Rev. *C
Page 9 of 42
MB39A135
7. Typical Characteristics
Power dissipation
Power dissipation vs. Operating ambient temperature
Operating ambient temperature Ta (°C)
VREF bias voltage vs.
Operating ambient temperature
Error Amp threshold voltage vs.
Operating ambient temperature
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Operating ambient temperature Ta (°C)
Document Number: 002-08410 Rev. *C
Operating ambient temperature Ta (°C)
Page 10 of 42
MB39A135
Oscillation frequency vs.
Operating ambient temperature
Dead time vs.
Operating ambient temperature
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Operating ambient temperature Ta(°C)
Oscillation frequency vs. Timing resistor value
Operating ambient temperature Ta(°C)
tD1 : period from DRVL off to DRVH on
tD2 : period from DRVH off to DRVL on
VB bias voltage vs. VB bias output current
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Timing resistor value RRT (k )
VB bias output current IVB (A)
Maximum duty cycle vs. Power supply voltage
Maximum duty cycle vs.
Operating ambient temperature
Power supply voltage VVCC (V)
Document Number: 002-08410 Rev. *C
Operating ambient temperature Ta (°C)
Page 11 of 42
MB39A135
8. Function Description
8.1 Current Mode
It uses the current waveform from the switching (Q1) as a control waveform to control the output voltage, as described below:
1. The clock (CK) from the internal clock generator (OSC) sets RS-FF and turns on the high-side FET.
2. Turning on the high-side FET causes the inductor current (IL) rise. Generate Vs that converts this current into the voltage.
3. The current comparator (I Comp.) compares this Vs with the output (COMP) from the error amplifier (Error Amp) that is negativefeedback from the output voltage (Vo).
4. When I Comp. detects that Vs exceeds COMP, it resets RS-FF and turns off high side FET.
5. The clock (CK) from the clock generator (OSC) turns on the high-side FET again.
Thus, switching is repeated.
Operate so that the FB electrical potential may become INTREF electrical potential, and stabilize the output voltage as a feedback
control.
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Document Number: 002-08410 Rev. *C
Page 12 of 42
MB39A135
8.1.1 Reference Voltage Block (REF)
The reference voltage circuit (REF) generates a temperature-compensated reference voltage (3.3[V] Typ) using the voltage supplied
from the VCC pin. The voltage is used as the reference voltage for the IC's internal circuit. The reference voltage can be used to
supply a load current of up to 100 A to an external device through the VREF pin.
8.1.2 Bias Voltage Block (VB Reg.)
Bias Voltage Block (VB Reg.) generates the reference voltage used for IC's internal circuit, using the voltage supplied from the VCC
pin. The reference voltage is a temperature-compensated stable voltage (5[V] Typ) to supply a current of up to 100 mA through the
VB pin.
8.1.3 Under Voltage Lockout Protection Circuit Block (UVLO)
The circuit protects against IC malfunction and system destruction/deterioration in a transitional state or a momentary drop when a
bias voltage (VB) or an internal reference voltage (VREF) starts. It detects a voltage drop at the VB pin or the VREF pin and stops
IC operation. When voltages at the VB pin and the VREF pin exceed the threshold voltage of the under voltage lockout protection
circuit, the system is restored.
8.1.4 Soft-start/Soft-stop Block (Soft-Start, Soft-Stop)
Soft-start
It protects a rush current or an output voltage (VO) from overshooting at the output start. Since the lamp voltage generated by charging
the capacitor connecting to the CS pin is used for the reference voltage of the error amplifier (Error Amp), it can set the soft-start time
independent of a load of the output (VO). When the IC starts with “H” level of the CTL pin, the capacitor at the CS pin (CS) starts to
be charged at 5.5 A. The output voltage (VO) during the soft-start period rises in proportion to the voltage at the CS pin generated
by charging the capacitor at the CS pin.
During the soft-start with, 0.8 V > voltage at CS pin, operations are as follows:
Fixed PWM operation only (fixed PWM even if MODE pin is set to “L”)
Over-voltage protection function and under-voltage protection function are invalid.
Soft-stop
It discharges electrical charges stored in a smoothing capacitor at output stop. Setting the CTL pin to “L” level starts the soft-stop
function independent of a load of output (Vo). Since the capacitor connecting to the CS pin starts to discharge through the IC-built-in
soft-stop discharging resistance (70[k ] Typ) when the CTL pin sets at “L” level enters its lamp voltage into the error amplifier (Error
Amp), the soft-stop time can be set independent of a load of output (VO). When discharging causes the voltage at the CS pin to drop
below 100 mV (Typ), the IC shuts down and changes to the stand-by state. In addition, the soft-stop function operates after the under
voltage protection circuit block (UVP Comp.) is latched or after the over-temperature protection circuit block (OTP) detects overtemperature.
During the soft-stop with, 0.8 V > voltage at CS pin, operations are as follows:
Fixed PWM operation only (fixed PWM even if MODE pin is set to “L”)
Over-voltage protection function and under-voltage protection function are invalid.
8.1.5 Clock Generator Block (OSC)
The clock generator has the built-in oscillation frequency setting capacitor and generates a clock by connecting the oscillation
frequency setting resistor to the RT pin.
8.1.6 Error Amp Block (Error Amp)
The error amplifiers (Error Amp) detect the output voltage from the DC/DC converter and output to the current comparators (I Comp.).
The output voltage setting resistor externally connected to FB pin allows an arbitrary output voltage to be set.
In addition, since an external resistor and an external capacitor serially connected between COMP and FB pins allow an arbitrary loop
gain to be set, it is possible for the system to compensate a phase stably.
Document Number: 002-08410 Rev. *C
Page 13 of 42
MB39A135
8.1.7 Over Current Detection (Protection) Block (ILIM)
It is the current detection circuit to restrict an output current (IO). The over current detection block (ILIM) compares an output waveform
of the level converter (see “(12) Level Converter Block (LVCNV)”) with the ILIM pin voltage in every cycle. As a load resistance (RO)
drops, a load current (IO) increases. Therefore, the output waveform of the level converter exceeds the ILIM pin voltage At this time,
the output current can be restricted by turning off FET on the high-side and suppressing a peak value of the inductor current.
As a result, the output voltage (VO) should drop.
Furthermore, if the output voltage drops and the electrical potential at the FB pin drops below 0.3 V, the oscillation frequency (f OSC)
drops to 1/8.
8.1.8 Over-voltage Protection Circuit Block (OVP Comp.)
The circuit protects a device connecting to the output when the output voltage (V O) rises.
It compares 1.15 times (Typ) of the internal reference voltage (INTREF) (0.7 V) that is non-inverting-entered into the error amplifier
with the feed-back voltage that is inverting-entered into the error amplifier and if it detects the state where the latter is higher than the
former by 50 s (Typ). It stops the voltage output by setting the RS latch, setting the DRVH pin to “L” level, setting the DRVL pin to
“H” level, turning off the high side FET and turning on the low-side FET.
The conditions below cancel the protection function:
Setting CTL to “L”.
Setting the power supply voltage below the UVLO threshold voltage (V THL1 and VTHL2).
8.1.9 Under-voltage Protection Circuit Block (UVP Comp.)
It protects a device connecting to the output by stopping the output when the output voltage (VO) drops.
It compares 0.7 times (Typ) of the internal reference voltage (INTREF) (0.7 V) that is non-inverting-entered into the error amplifier with
the feed-back voltage that is inverting-entered into the error amplifier and if it detects the state where the latter is lower than the former
by 512/fosc [s](Typ), it stops the voltage output by setting the RS latch.
The conditions below cancel the protection function:
Setting CTL to “L”.
Setting the power supply voltage below the UVLO threshold voltage (V THL1 and VTHL2).
8.1.10 Over Temperature Protection Circuit Block (OTP)
The circuit protects an IC from heat-destruction. If the temperature at the joint part reaches +160°C, the circuit stops the voltage output
by discharging the capacitor connecting to the CS pin through the soft-stop discharging resistance (70[k ] Typ) in the IC.
In addition, if the temperature at the joint part drops to +135°C, the output restarts again through the
soft-start function.
Therefore, make sure to design the DC/DC power supply system so that the over temperature protection does not start frequently.
8.1.11 PFM Control Circuit Block (MODE)
It sets the control mode of the IC and makes control at automatic PFM/PWM switching.
MODE Pin
Connection
Control Mode
“L” (GND)
Automatic PFM/PWM
switching
“H” (VREF)
Fixed PWM
Features
Highly-efficient at light load
Stable oscillation frequency
Stable switching ripple voltage
Excellent in rapid load change characteristic at heavy load to light load
Automatic PFM/PWM switching mode operation
It compares the LX pin voltage with GND electrical potential at Di Comp. In the comparison, the negative voltage at the LX pin causes
low-side FET to set on, positive voltage causes it to set off (Di Comp. method). As a result, the method restricts the back flow of the
inductor current at a light load and makes the switching of the inductor current discontinuous (DCM). Such an operation allows the
oscillation frequency to drop, resulting in high efficiency at a light load.
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Page 14 of 42
MB39A135
8.1.12 Output Block (DRV)
The output circuit is configured in CMOS type for both of the high-side and the low-side, allowing the external N-ch MOS FET to drive.
8.1.13 Level Converter Block (LVCNV)
The circuit detects and converts the current when the high-side FET turns on. It converts the voltage waveform between drain side
(VCC pin voltage) and the source side (LX pin voltage) on the high-side FET into the voltage waveform for GND reference.
8.1.14 Control Block (CTL)
The circuit controls on/off of the output from the IC.
Control function table
CTL
DC/DC Converter
Remarks
L
OFF
Standby
H
ON
—
Document Number: 002-08410 Rev. *C
Page 15 of 42
MB39A135
9. Protection Function Table
The following table shows the state of each pins when each protection function operates.
Protection
Function
Detection
Condition
Output of Each Pin After Detection
DC/DC Output
Dropping Operation
VREF
VB
DRVH
DRVL
< 2.7 V
< 3.6V
L
L
Self-discharge by load
Under Voltage Lock Out
(UVLO)
VB< 3.6 V
VREF< 2.7 V
Under Voltage Protection
(UVP)
FB< 0.49V
3.3 V
5V
L
L
Electrical discharge by
soft-stop function
Over Voltage Protection
(OVP)
FB " 0.805V
3.3 V
5V
L
H
0 V clamping
Over current protection
(ILIM)
COMP " ILIM
3.3 V
5V
switching
switching
160°C
3.3 V
5V
L
L
CTL : H L
(CS " 0.1 V)
3.3 V
5V
L
L
Over Temperature Protection
Tj "
(OTP)
CONTROL
(CTL)
Document Number: 002-08410 Rev. *C
The output voltage is
dropping to keep constant
output current.
Electrical discharge by
soft-stop function
Page 16 of 42
MB39A135
10. I/O Pin Equivalent Circuit Diagram
VREF pin
CTL pin
:&
:''
'80
:6)*
ESD protection element
+2(
+2(
VB pin
CS pin
:''
:6)*
:&
+2(
FB pin
:6)*
'7
+2(
COMP pin
:6)*
*&
'314
+2(
Document Number: 002-08410 Rev. *C
+2(
Page 17 of 42
MB39A135
ILIM pin
RT pin
:6)*
:6)*
:6)*
:&
-0-1
-0-1
68
+2(
+2(
+2(
MODE pin
CB, DRVH, LX pins
:6)*
'&
:6)*
:6)*
(6:,
(6:,
13()
0<
0<
+2(
DRVL pin
+2(
+2(
:&
(6:0
4+2(
+2(
Document Number: 002-08410 Rev. *C
Page 18 of 42
MB39A135
11. Example Application Circuit
6
:6)*
:-2
:
XS
:
13()
'7
'
%
6 '314
6
6
68
7SJX7XEVX"
GXP
YZTCSYX
SXTCSYX
:''
'PSGO
KIRIVEXSV
&MEW
6IK
'
:6)*
YZPS
SZTCSYX
4*1'SQT"
%
:
,MWMHI
(VMZI
*&
)VVSV%QT"
6
-'SQT"
MRXVIJ
'0/
67**
65
(VMZI
0SKMG
-0-1
7
0
:S
5
'
'
'
'
(6:,
0<
(6:0
4+2(
'
'
'
0IZIP
'SRZIVXIV
:W
'&
5
:&
0SWMHI
(VMZI
6
%
(
O
'
:&
(MGSQT"
6
3:4'SQT"
W
HIPE]
75
SZTCSYX
6
9:03"
MRXVIJ
\:
YZPS
9:4'SQT"
:&
9:03
J37'
HIPE]
75
6
YZTCSYX
:6)*
9:03
, 9:03
VIPIEWI
SXTCSYX
MRXVIJ
\:
:&
6)*"
MRXVIJ
1& %
384
GXP
'80"
323**
'80
:
:6)*
+2(
'
Document Number: 002-08410 Rev. *C
Page 19 of 42
MB39A135
12. Parts List
Component
Item
Specification
Vendor
Package
Parts Name
RENESAS
SO-8
Onsemi
SOD-523
1.5 H
(6.2 m , 8.9 A)
TDK
—
VLF10040T-1R5N
Remark
Q1
N-ch FET
VDS ! 30 V,
ID ! 8 A,
Ron ! 21 m
D2
Diode
VF ! 0.35 V
at IF ! 0.2 A
L1
Inductor
C1-1
C1-2
Ceramic capacitor
Ceramic capacitor
22 F (25 V)
22 F (25 V)
TDK
TDK
3225
3225
C3225JB1E226M
C3225JB1E226M
2 capacitors in
parallel
C2-1
C2-2
C2-3
Ceramic capacitor
Ceramic capacitor
Ceramic capacitor
22 F (10 V)
22 F (10 V)
22 F (10 V)
TDK
TDK
TDK
3216
3216
3216
C3216JB1A226M
C3216JB1A226M
C3216JB1A226M
3 capacitors in
parallel
C5
Ceramic capacitor
0.1 F (50 V)
TDK
1608
C1608JB1H104K
C7
Ceramic capacitor
0.022 F (50 V)
TDK
1608
C1608JB1H223K
C9
Ceramic capacitor
820 pF (50 V)
TDK
1608
C1608CH1H821J
C13
Ceramic capacitor
0.01 F (50 V)
TDK
1608
C1608JB1H103K
PA2755
BAT54XV2T1G
C14
Ceramic capacitor
1.0 F (16 V)
TDK
1608
C1608JB1C105K
C15
Ceramic capacitor
0.1 F (50 V)
TDK
1608
C1608JB1H104K
R8-1
R8-2
Resistor
Resistor
1.6 k
9.1 k
SSM
SSM
1608
1608
RR0816P162D
RR0816P912D
R9
Resistor
15 k
SSM
1608
RR0816P153D
R11
Resistor
56 k
SSM
1608
RR0816P563D
R12
Resistor
56 k
SSM
1608
RR0816P463D
R21
Resistor
82 k
SSM
1608
RR0816P823D
R23
Resistor
22 k
SSM
1608
RR0816P223D
RENESAS
Onsemi
TDK
SSM
Dual type
(2 elements)
2 resistors in
serial
: Renesas Electronics Corporation
: ON Semiconductor
: TDK Corporation
: SUSUMU Co.,Ltd.
Document Number: 002-08410 Rev. *C
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MB39A135
13. Application Note
13.1 Setting Method for PFM/PWM and Fixed PWM Modes
For the setting method for each mode, see “PFM Control Circuit Block (MODE)”.
13.2 Cautions at PFM/PWM Mode
If a load current drops rapidly because of rapid load change and others, it tends to take a lot of time to restore overshooting of an
output voltage.
As a result, the over-voltage protection may operate.
In this case, solution are possible by the addition of the load resistance of value to be able to restore the output voltage in the overvoltage detection time.
13.3 Setting Method of Output Voltage
Set it by adjusting the output voltage setting zero-power resistance ratio.
VO !
R1 R2
R2
VO
R1, R2
× 0.7
: Output setting voltage [V]
: Output setting resistor value [ ]
:3
6
*&
6
Make sure that the setting does not exceed the maximum on-duty.
Calculate the on-duty by the following formula.
DMAX_Min !
DMAX_Min
VIN
VO
RON_Main
RON_Sync
IOMAX
VIN
VO RON_Sync × IOMAX
RON_Main × IOMAX RON_Sync × IOMAX
: Minimum value of the maximum on-duty cycle
: Power supply voltage of switching system [V]
: Output setting voltage [V]
: High-side FET ON resistance [ ]
: Low-side FET ON resistance [ ]
: Maximum load current [A]
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MB39A135
13.4 Oscillation Frequency Setting Method
Set it by adjusting the RT pin resistor value.
1.09
RRT × 40 × 10 12 300 × 10
fOSC !
RRT
fOSC
9
: RT resistor value [ ]
: Oscillation frequency [Hz]
The oscillation frequency must set for on-time (tON) to become 300 ns or more.
Calculate the on-time by the following formula.
tON !
VO
VIN × fOSC
tON
VIN
VO
fOSC
: On-time [s]
: Power supply voltage of switching system [V]
: Output setting voltage [V]
: Oscillation frequency [Hz]
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MB39A135
13.5 Setting Method of Soft-start Time
Calculate the soft-start time by the following formula.
tS ! 1.4 × 105 × CCS
ts
CCS
: Soft-start time [s] (Time to becoming output 100%)
: CS pin capacitor value [F]
Calculate delay time until the soft-start beginning by the following formula:
td1 ! 30 × CVB 290 × CVREF 1.455 × 104 × CCS
td1
CCS
CVB
CVREF
: Delay time including VB voltage and VREF voltage starts [s]
: CS pin capacitor value [F]
: VB pin capacitor value [F]
: VREF pin capacitor value [F] (0.1 F Typ)
Calculate the discharge time at the soft-stop by the following formula:
tdis ! 1.44 × 105 × CCS
tdis
CCS
: Discharge time [s]
: CS pin capacitor value [F]
In addition, calculate the delay time to the discharge starting by the following formula:
td3 ! 7.87 × 104 × CCS
td3
CCS
: Delay time until discharge start [s]
: CS pin capacitor value [F]
XW
XHMW
'80
:3
XH
Document Number: 002-08410 Rev. *C
XH
Page 23 of 42
MB39A135
13.6 Setting Method of Over Current Detection Value
It is possible to set it by adjusting the over current detection setting zero-power resistance ratio when over current detection (I LIM) is
used.
Calculate the over current detection setting resistor value by the following formula.
3.3 × R2
0.3
R1 R2
VIN VO
ILIM !
6.8 × RON
L
200 × 103 R1 R2 30 × 103
ILIM
R1, R2
L
VIN
VO
fOSC
RON
*:
× (200 × 10
9
VO
2 × fOSC × VIN
)
: Over current detection value [A]
: ILIM setting resistor value [ ]*
: Inductor value [H]
: Power supply voltage of switching system [V]
: Output setting voltage [V]
: Oscillation frequency [Hz]
: High-side FET ON resistance [ ]
Since the over current detection value depends on the on-resistance of FET, the over current detection setting resistor value ratio should be adjusted in consideration
of the temperature characteristics of the on-resistance.
When the temperature at the FET joint part rises by +100°C, the on-resistance of FET increases to about 1.5 times.
Inductor current
:6)*
Over current
detection value
-0-1
6
-3
-0-1
6
*:
Time
If the over current detection function is not used, connect the ILIM pin to the VREF pin.
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MB39A135
13.7 Selection of Smoothing Inductor
The inductor value selects the value that the ripple current peak-to-peak value of the inductor becomes 50% or less of the maximum
load current as a rough standard. Calculate the inductor value in this case by the following formula.
L
VIN VO
LOR × IOMAX
L
IOMAX
LOR
VIN
VO
fOSC
×
VO
VIN × fOSC
: Inductor value [H]
: Maximum load current [A]
: Ripple current peak-to-peak value of Maximum load current ratio (=0.5)
: Power supply voltage of switching system [V]
: Output setting voltage [V]
: Oscillation frequency [Hz]
An inductor ripple current value limited on the principle of operation is necessary for this device. However, when it uses the high-side
FET of the low Ron resistance, the switching ripple voltage become small, and the ripple current value be insufficient. This should be
solved by the oscillation frequency or reducing the inductor value.
Select the one of the inductor value that meets a requirement listed below.
L
VIN VO
VRON
L
VIN
VO
fOSC
VRON
RON
×
VO
VIN × fOSC
× RON
: Inductor value [H]
: Power supply voltage of switching system [V]
: Output setting voltage [V]
: Oscillation frequency [Hz]
: Ripple voltage [V] (20 mV or more is recommended)
: High-side FET ON resistance [ ]
It is necessary to calculate the maximum current value that flows to the inductor to judge whether the electric current that flows to the
inductor is a rated value or less. Calculate the maximum current value of the inductor by the following formula.
ILMAX
IoMAX
ILMAX
IoMAX
IL
L
VIN
VO
fOSC
IL
2
, IL !
VIN VO
L
×
VO
VIN × fOSC
: Maximum current value of inductor [A]
: Maximum load current [A]
: Ripple current peak-to-peak value of inductor [A]
: Inductor value [H]
: Power supply voltage of switching system [V]
: Output setting voltage [V]
: Oscillation frequency [Hz]
Inductor current
-01%<
-S1%<
-0
t
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MB39A135
13.8 Selection of SWFET
The switching ripple voltage generated between drain and sources on high-side FET is necessary for this device operation. Select
the one of the SWFET of on-resistance that satisfies the following formula.
RON_Main
VRON_Main
IL
RON_Main
IL
VRON_Main
ILIM
VRONMAX
, RON_Main
VRONMAX
ILIM
IL
2
: High-side FET ON resistance [ ]
: Ripple current peak-to-peak value of inductor [A]
: High-side FET ripple voltage [V] (20 mV or more is recommended)
: Over current detection value [A]
: Maximum current sense voltage [V] (240 mV or less is recommended)
Select FET ratings with a margin enough for the input voltage and the load current. Ratings with the
over-current detection setting value or more are recommended.
Calculate a necessary rated value of high side FET and low-side FET by the following formula.
ID " IoMAX
ID
IoMAX
IL
IL
2
: Rated drain current [A]
: Maximum load current [A]
: Ripple current peak-to-peak value of inductor [A]
VDS " VIN
VDS
VIN
: Rated voltage between drain and source [V]
: Power supply voltage of switching system [V]
VGS " VB
VGS
VB
: Rated voltage between gate and source [V]
: VB voltage [V]
Moreover, it is necessary to calculate the loss of SWFET to judge whether a permissible loss of SWFET is a rated value or less.
Calculate the loss on high-side FET by the following formula.
PMainFET ! PRON_Main PSW_Main
PMainFET
PRON_Main
PSW_Main
: High-side FET loss [W]
: High-side FET conduction loss [W]
: High-side FET SW loss [W]
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MB39A135
High-side FET conduction loss
VO
VIN
PRON_Main ! IoMAX2 ×
PRON_Main
IOMAX
VIN
VO
RON_Main
× RON_Main
: High-side FET conduction loss [W]
: Maximum load current [A]
: Power supply voltage of switching system [V]
: Output voltage [V]
: High-side FET ON resistance [ ]
High-side FET SW loss
PSW_Main !
VIN × fOSC × (Ibtm × tr Itop × tf)
2
PSW_Main
VIN
fOSC
Ibtm
Itop
tr
tf
: High-side FET SW loss [W]
: Power supply voltage of switching system [V]
: Oscillation frequency [Hz]
: Ripple current bottom value of inductor [A]
: Ripple current top value of inductor [A]
: Turn-on time on high-side FET [s]
: Turn-off time on high-side FET [s]
Calculate the Ibtm, Itop, tr and the tf simply by the following formula.
Ibtm ! IoMAX
Itop ! IoMAX
tr !
IL
2
IL
2
Qgd × 4
5 Vgs (on)
IOMAX
IL
Qgd
Vgs (on)
tf !
Qgd × 1
Vgs (on)
: Maximum load current [A]
: Ripple current peak-to-peak value of inductor [A]
: Quantity of charge between gate and drain on high-side FET [C]
: Voltage between gate and sources in Qgd on high-side FET [V]
Document Number: 002-08410 Rev. *C
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MB39A135
Calculate the loss on low-side FET by the following formula.
PSyncFET ! PRon_Sync* ! IoMAX2 × (1
PSyncFET
PRon_Sync
IOMAX
VIN
VO
Ron_Sync
*:
VO
) × Ron_Sync
VIN
: Low-side FET loss [W]
: Low-side FET conduction loss [W]
: Maximum load current [A]
: Power supply voltage of switching system [V]
: Output voltage [V]
: Low-side FET on-resistance [ ]
The transition voltage of the voltage between drain and source on low-side FET is generally small, and the switching loss is omitted here for the small one as it is
possible to disregard it.
The gate drive power of SWFET is supplied by LDO in IC, therefore all of SWFET allowable maximum total charge (QgTotalMax) is
determined by the following formula.
0.095
fOSC
QgTotalMax
QgTotalMax
fOSC
: SWFET allowable maximum total charge [C]
: Oscillation frequency [Hz]
13.9 Selection of Fly-back Diode
When the conversion efficiency is valued, the improved property of the conversion efficiency is possible by the addition of the fly-back
diode. thought it is usually unnecessary. The effect is achieved in the condition where the oscillation frequency is high or output voltage
is lower. Select schottky barrier diode (SBD) that the forward current is as small as possible. In this DC/DC control IC, the period for
the electric current flows to fly-back diode is limited to synchronous rectification period (60 ns × 2) because of using the synchronous
rectification method. Therefore, select the one that the electric current of fly-back diode doesn't exceed ratings of forward current
surge peak (IFSM).Calculate the forward current surge peak ratings of fly-back diode by the following formula.
IFSM
IoMAX
IFSM
IoMAX
IL
IL
2
: Forward current surge peak ratings of fly-back diode [A]
: Maximum load current [A]
: Ripple current peak-to-peak value of inductor [A]
Calculate ratings of the fly-back diode by the following formula:
VR_Fly " VIN
VR_Fly
VIN
: Reverse voltage of fly-back diode direct current [V]
: Power supply voltage of switching system [V]
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MB39A135
13.10 Selection of Output Capacitor
This device supports a small ceramic capacitor of the ESR. The ceramic capacitor that is low ESR is an ideal to reduce the ripple
voltage compared with other capacitor. Use the tantalum capacitor and the polymer capacitor of the low ESR when a mass capacitor
is needed as the ceramic capacitor can not support. To the output voltage, the ripple voltage by the switching operation of DC/DC is
generated. Discuss the lower bound of output capacitor value according to an allowable ripple voltage. Calculate the output ripple
voltage from the following formula.
VO ! (
1
2
VO
ESR
IL
CO
fOSC
× fOSC × CO
ESR)
× IL
: Switching ripple voltage [V]
: Series resistance component of output capacitor [ ]
: Ripple current peak-to-peak value of inductor [A]
: Output capacitor value [F]
: Oscillation frequency [Hz]
Notes:
The ripple voltage can be reduced by raising the oscillation frequency and the inductor value besides capacitor.
Capacitor has frequency characteristic, the temperature characteristic, and the electrode bias characteristic, etc. The effective
capacitor value might become extremely small depending on the condition. Note the effective capacitor value in the condition.
Calculate ratings of the output capacitor by the following formula:
VCO " VO
: Withstand voltage of the output capacitor [V]
: Output voltage [V]
VCO
VO
Note:
Select the capacitor rating with withstand voltage allowing a margin enough for the output voltage.
In addition, use the allowable ripple current with an enough margin, if it has a rating. Calculate an allowable ripple current of the output
capacitor by the following formula.
IL
Irms
2 3
Irms
IL
: Allowable ripple current (effective value) [A]
: Ripple current peak-to-peak value of inductor [A]
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MB39A135
13.11 Selection of Input Capacitor
Select the input capacitor whose ESR is as small as possible. The ceramic capacitor is an ideal. Use the tantalum capacitor and the
polymer capacitor of the low ESR when a mass capacitor is needed as the ceramic capacitor can not support. To the power supply
voltage, the ripple voltage by the switching operation of DC/DC is generated. Discuss the lower bound of input capacitor according to
an allowable ripple voltage. Calculate the ripple voltage of the power supply from the following formula.
IOMAX
CIN
VIN !
VIN
IOMAX
CIN
VIN
VO
fOSC
ESR
IL
×
VO
VIN × fOSC
ESR ×
(IOMAX
IL
2
)
: Switching system power supply ripple voltage peak-to-peak value [V]
: Maximum load current value [A]
: Input capacitor value [F]
: Power supply voltage of switching system [V]
: Output setting voltage [V]
: Oscillation frequency [Hz]
: Series resistance component of input capacitor [ ]
: Ripple current peak-to-peak value of inductor [A]
Notes:
The ripple voltage can be reduced by raising the oscillation frequency besides capacitor.
Capacitor has frequency characteristic, the temperature characteristic, and the electrode bias characteristic, etc. The effective
capacitor value might become extremely small depending on the condition. Note the effective capacitor value in the condition.
Calculate ratings of the input capacitor by the following formula:
VCIN " VIN
VCIN
VIN
: Withstand voltage of the input capacitor [V]
: Power supply voltage of switching system [V]
Note:
Select the capacitor rating with withstand voltage with margin enough for the input voltage.
In addition, use the allowable ripple current with an enough margin, if it has a rating. Calculate an allowable ripple current by the
following formula.
Irms
IOMAX ×
Irms
IOMAX
VIN
VO
VO × (VIN VO)
VIN
: Allowable ripple current (effective value) [A]
: Maximum load current value [A]
: Power supply voltage of switching system [V]
: Output voltage [V]
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MB39A135
13.12 Selection of Boot Strap Diode
Select Schottky barrier diode (SBD), that forward current is as small as possible. The electric current that drives the gate of high-side
FET flows to SBD of the bootstrap circuit. Calculate the mean current by the following formula. Select it so as not to exceed the electric
current ratings.
ID
Qg × fOSC
ID
Qg
fOSC
: Forward current [A]
: Total quantity of charge of gate on high-side FET [C]
: Oscillation frequency [Hz]
Calculate ratings of the boot strap diode by the following formula:
VR_BOOT " VIN
VR_BOOT
VIN
: Reverse voltage of boot strap diode direct current [V]
: Power supply voltage of switching system [V]
13.13 Selection of Boot Strap Capacitor
To drive the gate of high-side FET, the bootstrap capacitor must have enough stored charge. Therefore, a minimum value as a target
is assumed the capacitor which can store electric charge 10 times that of the Qg on high-side FET. And select the boot strap capacitor.
CBOOT
10 ×
CBOOT
Qg
VB
Qg
VB
: Boot strap capacitor value [F]
: Amount of gate charge on high-side FET [C]
: VB voltage [V]
Calculate ratings of the boot strap capacitor by the following formula:
VCBOOT " VB
VCBOOT
VB
: Withstand voltage of the boot strap capacitor [V]
: VB voltage [V]
13.14 Design of Phase Compensation Circuit
Assume the phase compensation circuit of 1pole-1zero to be a standard in this device.
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MB39A135
13.15 1pole-1zero Phase Compensation Circuit
:3
6G
6
*&
6
-286)*
'G
To I Comp.
'314
)VVSV
%QT
As for crossover frequency (fCO) that shows the band width of the control loop of DC/DC. The higher it is, the more excellent the rapid
response becomes, however, the possibility of causing the oscillation due to phase margin shortage increases. Though this crossover
frequency (fCO) can be arbitrarily set, make 1/10 of the oscillation frequencies (fosc) a standard, and set it to the upper limit. Moreover,
set the phase margin at least to 30°, and 45° or more if possible as a reference.
Set the constants of Rc and Cc of the phase compensation circuit using the following formula as a target:
(VIN VO) ALVCNV × RON_Main × fCO × 2 × CO × VO
VIN × fOSC × L × IOMAX
RC !
CC !
× R1
CO × VO
RC × IOMAX
RC
CC
VIN
VO
fOSC
IOMAX
L
CO
RON_Main
R1
ALVCNV
: Phase compensation resistor value [ ]
: Phase compensation capacitor value [F]
: Power supply voltage of switching system [V]
: Output setting voltage [V]
: Oscillation frequency [Hz]
: Maximum load current value [A]
: Inductor value [H]
: Output capacitor value [F]
: High-side FET ON resistance [ ]
: Output setting resistor value [ ]
fCO
: Cross-over frequency (arbitrary setting) [Hz]
: Level converter voltage gain [V/V]
On-duty 50% : ALVCNV ! 6.8
On-duty > 50% : ALVCNV ! 13.6
Document Number: 002-08410 Rev. *C
Page 32 of 42
MB39A135
13.16 VB Pin Capacitor
1 F is assumed to be a standard, and when Qg of SWFET used is large, it is necessary to adjust it. To drive the gate of high-side
FET, the bootstrap capacitor must have enough stored charge. Therefore, a minimum value as a target is assumed the capacitor
which can store electric charge 100 times that of the Qg on high-side FET. And select it.
CVB
Qg
VB
100 ×
CVB
Qg
VB
: VB pin capacitor value [F]
: Total amount of gate charge of high-side FET and low-side FET [C]
: VB voltage [V]
Calculate ratings of the VB pin capacitor by the following formula:
VCVB " VB
: Withstand voltage of the VB pin capacitor [V]
: VB voltage [V]
VCVB
VB
13.17 VB Regulator
In the condition for which the potential difference between VCC and VB is insufficient, the decrease in the voltage of VB happens
because of power output on-resistance and load current (mean current of all external FET gate driving current and load current of
internal IC) of the VB regulator. Stop the switching operation when the voltage of VB decreases and it reaches threshold voltage (V THL1)
of the under voltage lockout protection circuit. Therefore, set oscillation frequency or external FET or I/O potential difference of the
VB regulator using the following formula as a target when you use this IC.
VCC
VB (VTHL1)
VCC
VB (VTHL1)
Qg
fOSC
ICC
RVB
(Qg × fOSC ICC) × RVB
: Power supply voltage [V] (VIN)
: Threshold voltage of VB under-voltage lockout protection circuit [V](3.8 [V] Max)
: Total amount of gate charge of high-side FET and low-side FET [C]
: Oscillation frequency [Hz]
: Power supply current [A] (2.7 × 10 - 3 [A] Load current of VB (LDO))
: VB output on-resistance [ ] (100 (The reference value at VCC = 4.5 V))
If the I/O potential difference is small, the problem can be solved by connecting the VB pin and the VCC pin.
The conditions of the input voltage range are as follows:
VIN input voltage ranges:
:
:
:
(1) For 4.5 V < VIN < 6.0 V
Connect VB pin to VCC.
(2) When the input voltage range steps over 6.0 V
Normal use (VCC to VB not connected)
(3) For 6.0 V VIN
Normal use (VCC to VB not connected)
Note that if the I/O potential difference is not enough when used, use the actual machine to check carefully the operations at the
normal operation, start operation, and stop operation. In particular, care is needed when the input voltage range over 6 V.
Document Number: 002-08410 Rev. *C
Page 33 of 42
MB39A135
13.18 Power Dissipation and the Thermal Design
As for this IC, considerations of the power dissipation and thermal design are not necessary in most cases because of its high
efficiency. However, they are necessary for the use at the conditions of a high power supply voltage, a high oscillation frequency, high
load, and the high temperature.
Calculate IC internal loss (PIC) by the following formula.
PIC ! VCC × (ICC Qg × fOSC)
PIC
VCC
ICC
Qg
fOSC
: IC internal loss [W]
: Power supply voltage (VIN) [V]
: Power supply current [A] (2.7[mA] Max)
: All SWFET total quantity of charge [C] (Total with Vgs
: Oscillation frequency [Hz]
! 5 V)
Calculate junction temperature (Tj) by the following formula.
Tj ! Ta ja × PIC
Tj
Ta
ja
PIC
: Junction temperature [°C] (+150[°C] Max)
: Ambient temperature [°C]
: TSSOP-16 Package thermal resistance (101°C/W)
: IC internal loss [W]
Document Number: 002-08410 Rev. *C
Page 34 of 42
MB39A135
13.19 Board Layout
Consider the points listed below and do the layout design.
Provide the ground plane as much as possible on the IC mounted face. Connect bypass capacitor connected with the VCC and VB
pins, and GND pin of the switching system parts with switching system GND (PGND). Connect other GND connection pins with
control system GND (AGND), and separate each GND, and try not to pass the heavy current path through the control system GND
(AGND) as much as possible. In that case, connect control system GND (AGND) and switching system GND (PGND) right under IC.
Connect the switching system parts as much as possible on the surface. Avoid the connection through the through-hole as much
as possible.
As for GND pins of the switching system parts, provide the through hole at the proximal place, and connect it with GND of internal layer.
Pay the most attention to the loop composed of input capacitor (CIN), SWFET, and fly-back diode (SBD). Consider making the current
loop as small as possible.
Place the boot strap capacitor (C BOOT) proximal to CB and LX pins of IC as much as possible.
This device monitors the voltage between drain and source on high-side FET as voltage between VCC and LX pins.
Place the input capacitor (CIN) and the high-side FET proximally as much as possible. Draw out the wiring to VCC pin from the
proximal place to the input capacitor. As for the net of the LX pin, draw it out from the proximal place to the source pin on high-side
FET. Moreover, a large electric current flows momentary in the net of the LX pin. Wire the linewidth of about 0.8 mm to be a standard,
as short as possible.
Large electric current flows momentary in the net of DRVH and DRVL pins connected with the gate of SWFET. Wire the linewidth
of about 0.8mm to be a standard, as short as possible.
By-pass capacitor (CVCC, CVREF, CVB) connected with VREF, VCC, and VB, and the resistor (RRT) connected with the RT pin should
be placed close to the pin as much as possible. Also connect the GND pin of
the by-pass capacitor with GND of internal layer in the proximal through-hole.
Consider the net connected with RT, FB, and the COMP pins to keep away from a switching system parts as much as possible
because it is sensitive to the noise. Moreover, place the output voltage setting resistor and the phase compensation circuit element
connected with this net close to the IC as much as possible, and try to make the net as short as possible. In addition, for the internal
layer right under the installing part, provide the control system GND (AGND) of few ripple and few spike noises, or provide the ground
plane of the power supply voltage as much as possible.
Switching system parts :
Input capacitor (CIN), SWFET, Fly-back diode (SBD), Inductor (L), Output capacitor (CO)
Layout example of IC
Layout example of switching components
To the VCC pin
Through-hole
High-side FET
%+2(
Through-hole
TMR
%+2(
668
:-2
To the LX pin
'-2
Low-side FET
':6)*
':&
'&338
':''
4+2(
7&( STXMSR
'3
0
4+2(
Surface
Internal
layer
Document Number: 002-08410 Rev. *C
4+2(
:S
Output voltage
Vo feedback
Page 35 of 42
MB39A135
14. Reference Data
Conversion Efficiency
Conversion Efficiency vs. Load Current
Load Regulation
Output Voltage vs. Load Current
:-2!:
:3!:
JSWG!O,^
8E!'
:-2!:
:3!:
13()!:6)*
JSWG!O,^
8E!'
4*14;1
Fixed PWM
Load Current IO (A)
Load Current IO (A)
Load Sudden Change Waveform
-3 %HMZ
%
VIN ! 12 V
VO ! 1.2 V
2A
IO ! 0
fOSC ! 300 kHz,
Ta ! 25°C
%
WHMZ
:3 Q:HMZ :SJJWIX
CTL Start-up Waveform
CTL Stop Waveform
'80 :HMZ
'80 :HMZ
:3 :HMZ
:3 :HMZ
QWHMZ
QWHMZ
VIN = 12 V, VO = 1.2 V, Io = 5 A (0.24 )
fosc ! 300 kHz, Ta ! 25°C,Soft start setting time ! 3.0 ms
Document Number: 002-08410 Rev. *C
Page 36 of 42
MB39A135
Normal operation
Over current protection
Under voltage protection operation waveform
:3 :HMZ
VIN ! 12 V
VO ! 1.2 V
fOSC ! 300 kHz
Ta ! 25°C
'7 :HMZ
0
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