S71VS/XS-R Memory Subsystem
Solutions
MirrorBit® 1.8 Volt-Only Simultaneous Read/Write,
Burst Mode Multiplexed Flash Memory and Burst Mode
pSRAM
256/128/64 Mb (16/8/4 Mb x 16-bit) Flash,
128/64/32 Mb (8/4/2 Mb x 16-bit) pSRAM
S71VS/XS-R Memory Subsystem Solutions Cover Sheet
Data Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S71VS_XS-R_00
Revision 17
Issue Date October 2, 2012
D at a
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Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
2
S71VS/XS-R Memory Subsystem Solutions
S71VS_XS-R_00_17 October 2, 2012
S71VS/XS-R Memory Subsystem
Solutions
MirrorBit® 1.8 Volt-Only Simultaneous Read/Write,
Burst Mode Multiplexed Flash Memory and Burst Mode
pSRAM
256/128/64 Mb (16/8/4 Mb x 16-bit) Flash,
128/64/32 Mb (8/4/2 Mb x 16-bit) pSRAM
Data Sheet
Features
Power supply voltage of 1.7V to 1.95V
Flash / pSRAM Burst Speed: 108 MHz, 104 MHz, 83 MHz
MCP BGA Packages
– 52 ball, 6.0 x 5.0 mm, 0.5 mm ball pitch
– 56 ball, 7.7 x 6.2 mm, 0.5 mm ball pitch
– 56 ball, 9.2 x 8.0 mm, 0.5 mm ball pitch
Operating Temperature
– Wireless, –25°C to +85°C
– Industrial, –40°C to +85°C
General Description
The S71VS-R Series is a product line of stacked Multi-Chip Package (MCP) memory solutions and consists of the following
items:
One or more S29VS-R Flash memory die
One or more pSRAM
The products covered by this document are listed in the table below. For details about their specifications, please refer to their
individual data sheet for further details.
Flash Density
pSRAM Density
Product
64 Mb
32 Mb
S71VS064RB0
128 Mb
32 Mb
S71VS128RB0
128 Mb
64 Mb
S71VS128RC0
256 Mb
64 Mb
S71VS256RC0
256 Mb
128 Mb
S71VS256RD0
Publication Number S71VS_XS-R_00
Revision 17
Issue Date October 2, 2012
D at a
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For detailed specifications, please refer to the individual data sheets:
Document
4
Publication Identification Number
S29VS/XS-R
S29VS_XS-R_00
S29VS/XS-R Supplement
S29VS_XS-R_SP
S29VS064R/XS064R
S29VS_XS064R_00
S29VS064R/XS064R Supplement
S29VS064R_XS064R_SP
128 Mb MUX pSRAM Type 5
pSRAM_39
32 Mb CellularRAM Address/Data multiplexed
SWM032D108M1R
32 Mb CellularRAM Address/Data multiplexed
SWM032D108M3R
64 Mb CellularRAM Address/Data multiplexed
SWM064D108M1R
128 Mb CellularRAM Address/Data multiplexed
SWM128D108M1R
128 Mb CellularRAM Address/Data multiplexed
SWM128D108M3R
S71VS/XS-R Memory Subsystem Solutions
S71VS_XS-R_00_17 October 2, 2012
Data
1.
She et
Ordering Information
The order number is formed by a valid combinations of the following:
S71VS
256
R
C
0
AH
K
4L
0
Packing Type
0 = Tray
3 = 13-inch Tape and Reel
Model Number
See Valid Combinations table below
Package Modifier
T = 6.0 x 5.0, 52-ball BGA, 0.5 mm ball pitch (0.3 mm ball diameter)
K = 7.7 x 6.2, 56-ball BGA, 0.5 mm ball pitch (0.3 mm ball diameter)
Package Type
AH = Very Thin Fine-Pitch Ball Grid Array (VFRBGA) — 1.0 mm max height with
0.5 mm pitch; Lead (Pb)-free Package; Low-Halogen
Chip Contents
0 = No content (default)
pSRAM Density
B = 32 Mb
C = 64 Mb
D = 128 Mb
Process Technology
R = 65 nm MirrorBit Technology
Flash Density
256 = 256 Mb
128 = 128 Mb
64 = 64 Mb
Product Family
S71VS = Multi-Chip Product 1.8 Volt-only Simultaneous Read/Write Burst Mode
Address and Data Multiplexed (ADM) Flash Memory + pSRAM
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Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local
sales office to confirm availability of specific valid combinations and to check on newly released
combinations.
Base Ordering
Part Number
Package
Model Number
Packing
Type
pSRAM Type
Flash Boot
Top
Bottom
Package: RSE052
3L
Top
Pinout: S71VS-R 52-ball
Wireless
Package: RLG052
4L
Top
CL
Bottom
Pinout: S71VS-R 52-ball
0M
Top
Package: RSE052
108 MHz
AHT
Bottom
SWM032D108M3R
Industrial
3M
Top
Pinout: S71VS-R 52-ball
BM
Bottom
Package: RLG052
0L
Top
8L
Bottom
3L
Top
AHK
Pinout: S71VS-R 56-ball
Package: RLA056
SWM032D108M1R
BL
0, 3
108 MHz
Bottom
4L
Top
Pinout: S71VS-R 56-ball
CL
Bottom
Package: RSD056
4L
S71VS256RC0
Pinout: S71VS-R 52-ball
Bottom
8M
S71VS128RC0
Pinout and Package
Notes
8L
SWM032D108M1R
S71VS128RB0
Flash /
pSRAM Speed
0L
BL
S71VS064RB0
Temperature
Range
AHK
Top
Wireless
SWM064D108M1R
108 MHz
Pinout: S71VS-R 56-ball
CL
Bottom
Package: RSD056
4L
Top
Pinout: S71VS-R 56-ball
AHK
SWM064D108M1R
CL
108 MHz
Bottom
3L
Top
BL
Bottom
Package: RLA056
108 MHz
SWM128D108M1R
3C
Top
BC
Bottom
83 MHz
S71VS256RD0
AHK
3M
SWM128D108M3R
40
Top
Package: RSD056
Industrial
108 MHz
Wireless
108/104 MHz
Top
MUX pSRAM Type 5
C0
Pinout: S71VS-R 56-ball
Bottom
Note:
If a choice exists, Spansion recommends Top Boot.
6
S71VS/XS-R Memory Subsystem Solutions
S71VS_XS-R_00_17 October 2, 2012
Data
2.
She et
Input/Output Descriptions
Table 2.1 identifies the input and output package connections provided on the device.
Table 2.1 Input/Output Descriptions
Flash
RAM
AMAX – A16
Symbol
Address inputs.
Description
X
X
A/DQ15-A/DQ0
Multiplexed Address/Data.
X
X
X
X
X
X
X
Address Valid input. Indicates to device that the valid address is present on the address
inputs.
AVD#
Low = for asynchronous mode, indicates valid address; for burst mode, causes starting
address to be latched.
High = device ignores address inputs
CLK
Clock input. In burst mode, after the initial word is output, subsequent active edges of CLK
increment the internal address counter. Should be at VIL or VIH while in asynchronous mode.
DNU
Do Not Use. A device internal signal may be connected to the package connector. The
connection may be used by Spansion for test or other purposes and is not intended for
connection to any host system signal. Any DNU signal related function will be inactive when
the signal is at VIL. The signal has an internal pull-down resistor and may be left
unconnected in the host system or may be tied to VSS. Do not use these connections for
PCB signal routing channels. Do not connect any host system signal to these connections.
OE#
Output Enable input. Asynchronous relative to CLK for the Burst mode.
X
F-CE#
Chip-enable input for Flash. Asynchronous relative to CLK for Burst Mode.
X
Ready output; indicates the status of the Burst read.
Flash Memory RDY (using default “Active HIGH” configuration)
VOL = data invalid
VOH = data valid
F-RDY/R-WAIT
Note: The default polarity for the pSRAM WAIT signal is opposite the default polarity of the
Flash RDY signal.
X
X
pSRAM WAIT (using default “Active HIGH” configuration)
VOL = data valid
VOH = data invalid
To match polarities, change bit 10 of the pSRAM Bus Configuration Register to 0 (Active
LOW WAIT). Alternately, change bit 10 of the Flash Configuration Register to 0 (Active LOW
RDY).
F-RST#
Hardware reset input. Low = device resets and returns to reading array data
X
F-VPP
Accelerated input. At VHH, accelerates programming; automatically places device in unlock
bypass mode. At VIL, disables all program and erase functions. Should be at VIH for all other
conditions.
X
NC
Not Connected. No device internal signal is connected to the package connector nor is there
any future plan to use the connector for a signal. The connection may safely be used for
routing space for a signal on a Printed Circuit Board (PCB).
R-CE#
Chip-enable input for pSRAM.
X
R-CRE
Control Register Enable (pSRAM).
X
R-LB#
Lower Byte Control (pSRAM).
X
R-UB#
Upper Byte Control (pSRAM).
X
RFU
Reserved For Future Use. No device internal signal is currently connected to the package
connector but there is potential future use for the connector for a signal. It is recommended
to not use RFU connectors for PCB routing channels so that the PCB may take advantage of
future enhanced features in compatible footprint devices.
VCC
Flash and pSRAM 1.8 Volt-only single power supply.
X
X
VCCQ
Flash and pSRAM Input/Output Power Supply.
X
X
VSS
Ground.
X
X
VSSQ
Input/Output Ground.
X
X
WE#
Write Enable input.
X
X
October 2, 2012 S71VS_XS-R_00_17
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3. MCP Block Diagram
Figure 3.1 S71VS-R MCP Block Diagram
8
F-RST#
RST#
F-VPP
F-RDY/R-WAIT
F-CE#
OE#
WE#
AVD#
VPP
RDY
CE#
OE#
WE#
AVD#
VSS, VSSQ
VSS
VSSQ
R-UB#
UB#
R-LB#
LB#
R-CE#
CE#
OE#
WE#
ADV#
VSS
VSSQ
WAIT
A/DQ15-A/DQ0
MUX
FLASH
MEMORY
VS-R
v
CLK
Amax-A16
VCC
VCCQ
ADQ15-ADQ0
CLK
v
Amax-A16
VCC
VCCQ
A/DQ15-A/DQ0
MUX
pSRAM
MEMORY
CLK
Amax-A16
VCC
VCCQ
S71VS/XS-R Memory Subsystem Solutions
CRE
R-CRE
S71VS_XS-R_00_17 October 2, 2012
Data
4.
She et
Connection Diagrams/Physical Dimensions
This section contains the I/O designations and package specifications for the S71VS-R.
4.1
Special Handling Instructions for FBGA Packages
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The
package and/or data integrity may be compromised if the package body is exposed to temperatures above
150°C for prolonged periods of time.
4.2
Connection Diagrams
Figure 4.1 S71VS-R 56-ball Fine-Pitch Ball Grid Array
(Top View, Balls Facing Down)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Legend
A
NC
NC
Not Connected
B
C
Do Not Use
NC
RFU
F-RDY/
R-WAIT
A21
VSS
VCCQ
A16
A20
VSS
A/DQ7
R-LB#
R-UB#
RFU
NC
CLK
VCC
WE#
F-VPP
A19
A17
A22
AVD#
A23
F-RST#
RFU
A18
F-CE#
VSS
A/DQ2
A/DQ9
A/DQ8
OE#
Flash Only
A/DQ4 A/DQ11 A/DQ10 VCCQ
A/DQ1
A/DQ0
RAM Only
RFU
NC
D
Reserved for Future Use
E
Flash/RAM Shared
F
A/DQ6 A/DQ13 A/DQ12 A/DQ3
G
A/DQ15 A/DQ14 VSSQ
A/DQ5
H
NC
RFU
R-CE# R-CRE
J
K
NC
October 2, 2012 S71VS_XS-R_00_17
NC
S71VS/XS-R Memory Subsystem Solutions
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Figure 4.2 S71VS-R 52-ball Fine-Pitch Ball Grid Array
(Top View, Balls Facing Down)
1
2
3
NC
RFU
F-RDY/
R-WAIT
A21
VSS
VCCQ
A16
A20
4
5
6
7
R-LB#
R-UB#
CLK
VCC
WE#
F-VPP
AVD#
RFU
F-RST#
RFU
8
9
10
RFU
NC
A19
A17
RFU
A18
F-CE#
VSS
Legend
A
Not Connected
B
Do Not Use
C
Reserved for Future Use
D
VSS
ADQ7
ADQ6
ADQ13
ADQ12
ADQ3
ADQ2
ADQ9
ADQ8
OE#
Flash/RAM Shared
E
ADQ15
ADQ14
VSS
ADQ5
ADQ4
ADQ11
ADQ10
VCCQ
ADQ1
ADQ0
Flash Only
F
NC
RFU
R-CE#
R-CRE
RFU
NC
RAM Only
Notes:
1. Addresses are shared between Flash and RAM depending on the density of the pSRAM.
2. VSS and VSSQ must be connected together.
10
MCP
Flash-Only Addresses
Shared Addresses
S71VS064RB0
A21
A20-A16
S71VS128RB0
A22-A21
A20-A16
S71VS128RC0
A22
A21-A16
S71VS256RC0
A23-A22
A21-A16
S71VS256RD0
A23
A22-A16
S71VS/XS-R Memory Subsystem Solutions
Shared ADQ Pins
A/DQ15-A/DQ0
S71VS_XS-R_00_17 October 2, 2012
Data
4.3
She et
Physical Dimensions
Figure 4.3 RLG052 - 52-ball VFRBGA 6.0 x 5.0 mm
NOTES:
PACKAGE
RLG 052
JEDEC
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
N/A
2. ALL DIMENSIONS ARE IN MILLIMETERS.
6.00 mm x 5.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JEP 95, SECTION 4.3, SPP-010.
SYMBOL
MIN
NOM
MAX
A
---
---
1.00
A1
0.18
---
---
NOTE
PROFILE
6.00 BSC.
BODY SIZE
E
5.00 BSC.
BODY SIZE
D1
4.50 BSC.
MATRIX FOOTPRINT
E1
2.50 BSC.
MD
10
MATRIX SIZE D DIRECTION
ME
6
MATRIX SIZE E DIRECTION
n
52
BALL COUNT
0.25
0.30
MATRIX FOOTPRINT
0.35
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW SD OR SE = 0.000.
BALL DIAMETER
e
0.50 BSC.
BALL PITCH
SE / SD
0.25 BSC.
SOLDER BALL PLACEMENT
e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE
"D" DIRECTION.
BALL HEIGHT
D
Ib
4.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
8. “+” INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
3A,3F,4A,4F,7A,7F,8A,8F
DEPOPULATED SOLDER BALLS
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
g1002-1 \ f16-038.63 \ 08.25.10
October 2, 2012 S71VS_XS-R_00_17
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Figure 4.4 RLA056 - 56-ball VFRBGA 7.7 x 6.2 mm
NOTES:
PACKAGE
RLA 056
JEDEC
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
N/A
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D XE
7.70 mm x 6.20 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JEP 95, SECTION 4.3, SPP-010.
SYMBOL
MIN
NOM
MAX
A
---
---
1.00
A1
0.18
---
---
A2
0.62
---
0.74
NOTE
PROFILE
BALL HEIGHT
7.70 BSC.
BODY SIZE
E
6.20 BSC.
BODY SIZE
6.50 BSC.
E1
4.50 BSC.
MD
14
MATRIX FOOTPRINT
MATRIX FOOTPRINT
10
MATRIX SIZE E DIRECTION
n
56
BALL COUNT
b
0.25
0.30
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X E
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
MATRIX SIZE D DIRECTION
ME
0.35
e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE
"D" DIRECTION.
BODY THICKNESS
D
D1
4.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW SD OR SE = 0.000.
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
eE
0.50 BSC.
BALL PITCH
eD
0.50 BSC.
BALL PITCH
8. “+” INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
SE SD
0.25 BSC.
SOLDER BALL PLACEMENT
9
DEPOPULATED SOLDER BALLS
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.
g1007 \ f16-038.63 \ 08.18.10
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S71VS/XS-R Memory Subsystem Solutions
S71VS_XS-R_00_17 October 2, 2012
Data
She et
Figure 4.5 RSD056—56-ball VFRBGA 7.7 x 6.2 mm
NOTES:
PACKAGE
RSD 056
JEDEC
N/A
DxE
SYMBOL
7.70 mm x 6.20 mm
PACKAGE
MIN
NOM
NOTE
A
0.80
0.90
1.00
0.18
---
---
A2
0.62
BALL POSITION DESIGNATION PER JEP95, SECTION 4.3,
SPP-010.
---
0.74
PROFILE
e REPRESENTS THE SOLDER BALL GRID PITCH.
BALL HEIGHT
5.
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
BODY THICKNESS
7.70 BSC
BODY SIZE
E
6.20 BSC
BODY SIZE
D1
6.50 BSC
MATRIX FOOTPRINT
E1
4.50 BSC
MD
14
MATRIX SIZE D DIRECTION
ME
10
MATRIX SIZE E DIRECTION
n
56
BALL COUNT
0.30
ALL DIMENSIONS ARE IN MILLIMETERS.
3.
4.
D
0.25
DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2.
MAX
A1
Øb
1.
MATRIX FOOTPRINT
0.35
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
BALL DIAMETER
eE
0.50 BSC
BALL PITCH
eD
0.50 BSC
BALL PITCH
SE SD
0.25 BSC
SOLDER BALL PLACEMENT
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
8.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
DEPOPULATED SOLDER BALLS
10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.
3719 \ f16-038.63 \ 1.26.9
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Figure 4.6 RSE052—52-ball VFRBGA 6.0 x 5.0 mm
NOTES:
PACKAGE
RSE 052
JEDEC
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
N/A
2. ALL DIMENSIONS ARE IN MILLIMETERS.
DXE
6.00 mm x 5.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JEP 95, SECTION 4.3, SPP-010.
SYMBOL
MIN
NOM
MAX
A
---
---
1.00
A1
0.18
---
---
D
6.00 BSC.
NOTE
PROFILE
5.00 BSC.
BODY SIZE
4.50 BSC.
MATRIX FOOTPRINT
E1
2.50 BSC.
MATRIX FOOTPRINT
MD
10
MATRIX SIZE D DIRECTION
ME
6
MATRIX SIZE E DIRECTION
b
52
0.25
0.30
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
BODY SIZE
E
n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
BALL COUNT
0.35
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW SD OR SE = 0.000.
BALL DIAMETER
e
0.50 BSC.
BALL PITCH
SE / SD
0.25 BSC.
SOLDER BALL PLACEMENT
e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE
"D" DIRECTION.
BALL HEIGHT
D1
n
4.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
8. “+” INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
3A,3F,4A,4F,7A,7F,8A,8F
DEPOPULATED SOLDER BALLS
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
g1004-1 \ f16-038.63 \ 08.25.10
14
S71VS/XS-R Memory Subsystem Solutions
S71VS_XS-R_00_17 October 2, 2012
Data
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5. Revision History
Section
Description
Revision 01 (August 25, 2008)
Initial release
Revision 02 (November 4, 2008)
Global
Added OPNs S71VS064RB0AHT00/04/80/84
Connection Diagrams
Added S71VS-R 52-ball connection diagram
Physical Dimensions
Added RSB052
General Description
Changed 128 Mb Mux pSRAM PID from TBD to pSRAM_39
Revision 03 (November 10, 2008)
General Description
Changed 64 Mb MUX pSRAM Type 3 PID from muxpsram_14 to muxpsram_15
Revision 04 (January 13, 2009)
Physical Dimensions
Replaced NLD056 with NSD056
Revision 05 (January 23, 2009)
Valid Combinations
Added OPN S71VS128RC0AHK20
Physical Dimensions
Added RSD056
Revision 06 (March 11, 2009)
Valid Combinations
Added 108 MHz speed grade to S71VS128RC0 and S71VS256RC0
Revision 07 (September 29, 2009)
General Description
Added S71VS128RB0; added muxpsram_10
Valid Combinations
Added OPN S71VS128RB0
Revision 08 (April 9, 2010)
General Description
Added SWM064D108M1R
Updated pSRAM documentation names
Added OPNs:
Valid Combinations
S71VS128RC0AHK4L
S71VS256RC0AHK4L
Connection Diagrams
Updated VSSQ ball to VSS
Removed Bottom Boot options
Revision 09 (May 4, 2010)
General Description
Added reference to S29VS064R data sheet
Removed CustComspec_01 for 32 Mb MUX pSRAM
Corrected pSRAM type for S71VS064RB0 from CustComspec_01 to SWM032D108M1R
Valid Combinations
Added OPNs:
S71VS064RB0AHT0L
S71VS256RD0AHK40
Revision 10 (June 14, 2010)
Removed S71XS256RD0 from table
General Description
Unified data sheet reference for S29VS/XS-R
Removed MUX pSRAM Type 3
Added SWM128D108M1R
Restored necessary bottom boot options.
Added OPNs: S71VS256RD0AHK3L/BL/3C/BC
Removed OPNs: S71VS064RB0AHT00/04
Valid Combinations
October 2, 2012 S71VS_XS-R_00_17
Updated MUX pSRAM Type 3 entries to the Common RAM type specifications
Removed table after Figure 4.3 S71XS-R 56-ball Fine-Pitch Ball Grid Array
S71VS/XS-R Memory Subsystem Solutions
15
D at a
S hee t
Section
Description
Revision 11 (July 28, 2010)
Features
Ordering Information
Corrected MCP BGA Packages information
Corrected Package Modifier information
Removed 7 inch Tape and Reel option
Corrected package information for S71VS064RB0AHT0L
Valid Combinations
Added OPN S71VS064RB0AHT8L, S71VS128RC0AHKCL, S71VS256RC0AHKCL
Removed OPN S71VS256RD0AHK40
MCP Block Diagram
Removed figure S71XS-R MCP Block Diagram
Corrected figure S71VS-R 52-ball Fine-Pitch Ball Grid Array
Connection Diagrams/Physical
Dimensions
Removed figure S71XS-R 56-ball Fine-Pitch Ball Grid Array
Replaced figure RSB052—52-ball VFBGA 5.0 x 7.5 mm
with RSE052—52-ball VFRBGA 6.0 x 5.0 mm
Refreshed DNU/RFU/NC definitions
Revision 12 (August 27, 2010)
Valid Combinations
Corrected package information for S71VS128RB0AHK0L/8L (RLA056)
Corrected speed for OPNs S71VS256RD0AHK3L/BL to 108 MHz
Connection Diagrams
Reverted DNU balls to RFU
Physical Dimensions
Added diagram for RLA056
Revision 13 (December 9, 2010)
Features
Added Industrial temperature
General Description
Added references to S29VS_XS-R_SP, S29VS064R_XS064R_SP, SWM032D108M3R,
SWM128D108M3R
Valid Combinations
Added OPNs S71VS064RB0AHT3L/BL/0M/8M, S71VS128RB0AHK3L/BL, S71VS256RD0AHK3M,
S71VS256RD0AHK40/C0
Added Temperature Range Column
Revision 14 (April 13, 2011)
General Description
Removed SWM032D108M1N and SWM064D108M1N references
Valid Combinations
Removed OPNs S71VS064RB0AHT3M/BM, S71VS128RB0AHK2L/AL, S71VS128RC0AHK20,
S71VS128RC0ZHKxx, S71VS256RC0ZHKxx, S71VS256RD0ZHExx
Physical Dimensions: Removed NLB056 and NSD056 diagrams. Added diagram for RLG052
Revision 15 (June 20, 2011)
Valid Combinations
Added OPNs S71VS128RB0AHK4L/CL, , S71VS064RB0AHT4L/CL
Revision 16 (June 29, 2012)
Valid Combinations
Added OPNs S71VS064RB0AHT3M/BM
Revision 17 (October 2, 2012)
Valid Combinations
16
Updated the S71VS256RC0AHK4L/CL package from RSD056 to RLA056
S71VS/XS-R Memory Subsystem Solutions
S71VS_XS-R_00_17 October 2, 2012
Data
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Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
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the prior authorization by the respective government entity will be required for export of those products.
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The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
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merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
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combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used
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October 2, 2012 S71VS_XS-R_00_17
S71VS/XS-R Memory Subsystem Solutions
17
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