STK14D88
32Kx8 AutoStore nvSRAM
Features
Description
■
25, 35, 45 ns Read Access and R/W Cycle Time
■
Unlimited Read/Write Endurance
The Cypress STK14D88 is a 256Kb fast static RAM with a
nonvolatile Quantum Trap storage element included with each
memory cell.
■
Automatic Nonvolatile STORE on Power Loss
■
Nonvolatile STORE Under Hardware or Software Control
■
Automatic RECALL to SRAM on Power Up
■
Unlimited RECALL Cycles
■
200K STORE Cycles
■
20-Year Nonvolatile Data Retention
■
Single 3.0V +20%, -10% Power Supply
■
Commercial, Industrial Temperatures
■
Small Footprint SOIC and SSOP Packages (RoHS-Compliant)
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ns
The SRAM provides fast access and cycle times, ease of use,
and unlimited read and write endurance of a normal SRAM.
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Data transfers automatically to the nonvolatile storage cells
when power loss is detected (the STORE operation). On power
up, data is automatically restored to the SRAM (the RECALL
operation). Both STORE and RECALL operations are also
available under software control.
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The Cypress nvSRAM is the first monolithic nonvolatile memory
to offer unlimited writes and reads. It is the highest performance,
most reliable nonvolatile memory available.
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Logic Block Diagram
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VCCX
POWER
CONTROL
en
STORE
RECALL
STORE/
RECALL
CONTROL
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STATIC RAM
ARRAY
512 x 512
SOFTWARE
DETECT
ec
R
INPUT BUFFERS
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N
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
ROW DECODER
A5
A6
A7
A8
A9
A11
A12
A13
A14
de
Quantum Trap
512 x 512
VCAP
COLUMN I/O
HSB
A0 - A13
COLUMN DEC
A0 A1 A2 A3 A4 A10
G
E
W
Cypress Semiconductor Corporation
Document Number: 001-52037 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 01, 2009
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STK14D88
Contents
Features................................................................................ 1
Description........................................................................... 1
Logic Block Diagram........................................................... 1
Contents ............................................................................... 2
Pin Configurations .............................................................. 3
Pin Descriptions .................................................................. 3
Absolute Maximum Ratings ............................................... 4
DC Characteristics .............................................................. 4
AC Test Conditions ............................................................. 5
Capacitance ......................................................................... 5
SRAM READ Cycles #1 and #2 ..................................... 6
SRAM WRITE Cycle #1 and #2 ..................................... 7
AutoStore/POWER UP RECALL ......................................... 8
Software-Controlled STORE/RECALL Cycle..................... 9
Hardware STORE Cycle ..................................................... 10
Soft Sequence Commands ............................................... 10
Mode Selection ................................................................... 11
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nvSRAM Operation............................................................ 12
nvSRAM ....................................................................... 12
SRAM READ ................................................................ 12
SRAM WRITE .............................................................. 12
AutoStore Operation...................................................... 12
Hardware STORE (HSB) Operation............................. 12
Software STORE.......................................................... 12
Software RECALL ........................................................ 13
Data Protection............................................................. 13
Best Practices .............................................................. 13
Low Average Active Power .......................................... 13
Noise Considerations ................................................... 14
Preventing AutoStore ................................................... 14
Part Numbering Nomenclature......................................... 16
Package Diagrams............................................................. 17
Document History Page ..................................................... 19
Sales, Solutions, and Legal Information ......................... 19
Worldwide Sales and Design Support.......................... 19
Products ....................................................................... 19
Document Number: 001-52037 Rev. *A
Page 2 of 18
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STK14D88
Pin Configurations
Figure 1. Pin Diagram 48-Pin SSOP/32-SOIC
32-SOIC
48-Pin SSOP
48
2
47
VCC
NC
3
46
HSB
A12
A7
4
5
45
44
A6
A5
6
43
7
42
W
A13
A8
A9
NC
A4
8
41
NC
9
40
A11
NC
10
39
NC
NC
NC
VSS
11
38
NC
37
13
36
NC
NC
DQ0
14
35
NC
VSS
NC
15
34
16
33
A3
A2
17
32
18
31
G
A10
A1
19
30
E
A0
DQ1
DQ2
20
29
21
28
22
23
27
24
25
DQ7
DQ5
DQ4
DQ3
VCC
I/O
E
Input
W
Input
VCC
HSB
30
4
A6
A5
5
29
28
6
27
W
A13
A8
A9
A4
A3
7
26
A11
25
NC
A2
9
24
G
NC
8
TOP
23
A10
11
22
12
21
E
DQ7
DQ0
DQ1
13
20
DQ6
14
19
DQ5
DQ2
VSS
15
18
16
17
DQ4
DQ3
10
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Description
Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array
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Input
N
G
3
Relative PCB Area Usage[1]
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Input
A12
A7
Data: Bi-directional 8-bit data bus for accessing the nvSRAM
Chip Enable: The active low E input selects the device
Write Enable: The active low W enables data on the DQ pins to be written to the address location
latched by the falling edge of E
R
A14-A0
DQ7-DQ0
HSB
ec
I/O
NC
DQ6
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Pin Descriptions
Pin Name
VCC
31
SSOP
26
32
2
A1
A0
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TOP
1
A14
en
NC
NC
12
VCAP
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ns
1
NC
A14
es
VCAP
Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tri-state.
Power Supply Power: 3.0V, +20%, -10%
I/O
Hardware Store Busy: When low this output indicates a Store is in progress. When pulled low
external to the chip, it initiates a nonvolatile STORE operation. A weak pull up resistor keeps this pin
high if not connected. (Connection Optional).
VCAP
Power Supply AutoStore Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to
nonvolatile storage elements.
VSS
Power Supply Ground
NC
No Connect
Unlabeled pins have no internal connections.
Note
1. See “Package Diagrams” on page 16 for detailed package size specifications.
Document Number: 001-52037 Rev. *A
Page 3 of 18
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STK14D88
Absolute Maximum Ratings
Voltage on Input Relative to Ground.................–0.5V to 4.1V
Note: Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device
at conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
Voltage on Input Relative to VSS ...........–0.6V to (VCC + 0.5V)
Voltage on DQ0-7 or HSB ......................–0.5V to (VCC + 0.5V)
Temperature under Bias ............................... –55°C to 125°C
Storage Temperature .................................... –65°C to 140°C
Power Dissipation............................................................. 1W
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ns
DC Output Current (1 output at a time, 1s duration).... 15 mA
NF (SOP-32) PACKAGE THERMAL CHARACTERISTICS
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θjc 5.4 C/W; θja 44.3 [0 fpm], 37.9 [200 fpm], 35.1 C/W [500 fpm].
RF (SSOP-48) PACKAGE THERMAL CHARACTERISTICS
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θjc 6.2 C/W; θja 51.1 [0 fpm], 44.7 [200 fpm], 41.8 C/W [500 fpm].
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DC Characteristics
(VCC = 2.7V-3.6V)
Commercial
Parameter[2]
Min
Industrial
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Symbol
Max
Min
Max
Unit
Notes
mA
mA
mA
tAVAV = 25 ns
tAVAV = 35 ns
tAVAV = 45 ns
Dependent on output loading and
cycle rate. Values obtained without
output loads.
3
mA
All Inputs Don’t Care, VCC = max
Average current for duration of
STORE cycle (tSTORE)
10
10
mA
W ≥ (V CC – 0.2V)
All Others Cycling, CMOS Levels
Dependent on output loading and
cycle rate. Values obtained without
output loads.
3
3
mA
All Inputs Don’t Care
Average current for duration of
STORE cycle (tSTORE)
VCC Standby Current
(Standby, Stable CMOS Input
Levels)
3
3
mA
E ≥ (V CC – 0.2V)
All Others VIN ≤ 0.2V or ≥ (VCC – 0.2V)
Standby current level after nonvolatile
cycle complete
IILK
Input Leakage Current
±1
±1
μA
VCC = max
VIN = VSS to VCC
IOLK
Off State Output Leakage Current
±1
±1
μA
VCC = max
VIN = VSS to VCC, E or G ≥ VIH
VIH
Input Logic “1” Voltage
2.0
VCC + .5
2.0
VCC + .5
V
All Inputs
VSS – .5
0.8
VSS – .5
0.8
65
55
50
ICC2
Average VCC Current during
STORE
ICC3
Average VCC Current at tAVAV =
200ns
3V, 25°C, Typical
ICC4
Average VCAP Current during
AutoStore Cycle
ISB
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Average VCC Current
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70
60
55
ICC1
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3
VIL
Input Logic “0” Voltage
VOH
Output Logic “1” Voltage
VOL
Output Logic “0” Voltage
2.4
2.4
0.4
0.4
V
All Inputs
V
IOUT = – 2 mA
V
IOUT = 4 mA
Note:
2. The HSB pin has IOUT=-10uA for VOH of 2.4V, this parameter is characterized but not tested
Document Number: 001-52037 Rev. *A
Page 4 of 18
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STK14D88
DC Characteristics (continued)
(VCC = 2.7V-3.6V)
Commercial
Parameter[2]
Symbol
TA
Operating Temperature
Industrial
Min
Max
Min
Max
0
70
- 40
85
Unit
Notes
°C
VCC
Operating Voltage
2.7
3.6
2.7
3.6
V
3.3V +20%, -10%
VCAP
Storage Capacitance
17
120
17
120
μF
Between VCAP pin and VSS, 5V Rated
DATAR
Data Retention
20
20
NVC
Nonvolatile STORE Operations
200
200
K
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ns
Years At 55°C
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AC Test Conditions
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Input Pulse Levels .................................................... 0V to 3V
Input Rise and Fall Times ............................................
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